Mercurial > hg > release > icedtea7-forest-2.6 > hotspot
changeset 6728:c98fe53cf02b
8151340, PR3741: aarch64: prefetch the destination word for write prior to ldxr/stxr loops.
Summary: aarch64: add prefetch for write prior to ldxr/stxr loops.
Reviewed-by: aph
Contributed-by: felix.yang@linaro.org
| author | fyang |
|---|---|
| date | Tue, 16 Jul 2019 06:37:47 +0100 |
| parents | b000b342ce37 |
| children | 12eb373fbf8f |
| files | src/cpu/aarch64/vm/aarch64.ad src/cpu/aarch64/vm/assembler_aarch64.cpp src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp |
| diffstat | 3 files changed, 10 insertions(+), 2 deletions(-) [+] |
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--- a/src/cpu/aarch64/vm/aarch64.ad Tue May 28 09:03:15 2019 -0400 +++ b/src/cpu/aarch64/vm/aarch64.ad Tue Jul 16 06:37:47 2019 +0100 @@ -2954,6 +2954,7 @@ // membar_acquire_lock(). { Label retry_load; + __ prfm(Address(oop), PSTL1STRM); __ bind(retry_load); __ ldxr(tmp, oop); __ cmp(tmp, disp_hdr); @@ -3004,6 +3005,7 @@ { Label retry_load, fail; + __ prfm(Address(tmp), PSTL1STRM); __ bind(retry_load); __ ldxr(rscratch1, tmp); __ cmp(disp_hdr, rscratch1); @@ -3093,6 +3095,7 @@ { Label retry_load; + __ prfm(Address(oop), PSTL1STRM); __ bind(retry_load); __ ldxr(tmp, oop); __ cmp(box, tmp);
--- a/src/cpu/aarch64/vm/assembler_aarch64.cpp Tue May 28 09:03:15 2019 -0400 +++ b/src/cpu/aarch64/vm/assembler_aarch64.cpp Tue Jul 16 06:37:47 2019 +0100 @@ -3146,6 +3146,7 @@ void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) { Label retry_load; + prfm(Address(counter_addr), PSTL1STRM); bind(retry_load); // flush and load exclusive from the memory location ldxrw(tmp, counter_addr); @@ -3571,7 +3572,7 @@ // addr identifies memory word to compare against/update // tmp returns 0/1 for success/failure Label retry_load, nope; - + prfm(Address(addr), PSTL1STRM); bind(retry_load); // flush and load exclusive from the memory location // and fail if it is not what we expect @@ -3599,7 +3600,7 @@ // addr identifies memory word to compare against/update // tmp returns 0/1 for success/failure Label retry_load, nope; - + prfm(Address(addr), PSTL1STRM); bind(retry_load); // flush and load exclusive from the memory location // and fail if it is not what we expect @@ -3634,6 +3635,7 @@ result = different(prev, incr, addr) ? prev : rscratch2; \ \ Label retry_load; \ + prfm(Address(addr), PSTL1STRM); \ bind(retry_load); \ LDXR(result, addr); \ OP(rscratch1, result, incr); \ @@ -3656,6 +3658,7 @@ result = different(prev, newv, addr) ? prev : rscratch2; \ \ Label retry_load; \ + prfm(Address(addr), PSTL1STRM); \ bind(retry_load); \ LDXR(result, addr); \ STXR(rscratch1, newv, addr); \
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Tue May 28 09:03:15 2019 -0400 +++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Tue Jul 16 06:37:47 2019 +0100 @@ -1512,6 +1512,7 @@ Label retry_load, nope; // flush and load exclusive from the memory location // and fail if it is not what we expect + __ prfm(Address(addr), PSTL1STRM); __ bind(retry_load); __ ldaxrw(rscratch1, addr); __ cmpw(rscratch1, cmpval); @@ -1530,6 +1531,7 @@ Label retry_load, nope; // flush and load exclusive from the memory location // and fail if it is not what we expect + __ prfm(Address(addr), PSTL1STRM); __ bind(retry_load); __ ldaxr(rscratch1, addr); __ cmp(rscratch1, cmpval);