Mercurial > hg > release > icedtea7-forest-2.6 > hotspot
changeset 6726:1dcb48440774
8186325, PR3741: AArch64: jtreg test hotspot/test/gc/g1/TestJNIWeakG1/TestJNIWeakG1.java SEGV
Reviewed-by: adinn, aph
Contributed-by: stuart.monteith@linaro.org
| author | njian |
|---|---|
| date | Mon, 15 Jul 2019 19:07:27 +0100 |
| parents | 1bf03fa0773b |
| children | b000b342ce37 |
| files | src/cpu/aarch64/vm/assembler_aarch64.cpp src/cpu/aarch64/vm/templateTable_aarch64.cpp |
| diffstat | 2 files changed, 19 insertions(+), 5 deletions(-) [+] |
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--- a/src/cpu/aarch64/vm/assembler_aarch64.cpp Thu Apr 18 04:21:39 2019 +0100 +++ b/src/cpu/aarch64/vm/assembler_aarch64.cpp Mon Jul 15 19:07:27 2019 +0100 @@ -4444,6 +4444,12 @@ } #ifndef SERIALGC +/* + * g1_write_barrier_pre -- G1GC pre-write barrier for store of new_val at + * store_addr. + * + * Allocates rscratch1 + */ void MacroAssembler::g1_write_barrier_pre(Register obj, Register pre_val, Register thread, @@ -4461,10 +4467,8 @@ Label done; Label runtime; - assert(pre_val != noreg, "check this code"); - - if (obj != noreg) - assert_different_registers(obj, pre_val, tmp); + assert_different_registers(obj, pre_val, tmp, rscratch1); + assert(pre_val != noreg && tmp != noreg, "expecting a register"); Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_active())); @@ -4538,6 +4542,12 @@ bind(done); } +/* + * g1_write_barrier_post -- G1GC post-write barrier for store of new_val at + * store_addr + * + * Allocates rscratch1 + */ void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register thread, @@ -4546,6 +4556,10 @@ #ifdef _LP64 assert(thread == rthread, "must be"); #endif // _LP64 + assert_different_registers(store_addr, new_val, thread, tmp, tmp2, + rscratch1); + assert(store_addr != noreg && new_val != noreg && tmp != noreg + && tmp2 != noreg, "expecting a register"); Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + PtrQueue::byte_offset_of_index()));
--- a/src/cpu/aarch64/vm/templateTable_aarch64.cpp Thu Apr 18 04:21:39 2019 +0100 +++ b/src/cpu/aarch64/vm/templateTable_aarch64.cpp Mon Jul 15 19:07:27 2019 +0100 @@ -172,7 +172,7 @@ // G1 barrier needs uncompressed oop for region cross check. Register new_val = val; if (UseCompressedOops) { - new_val = rscratch1; + new_val = rscratch2; __ mov(new_val, val); } __ store_heap_oop(Address(r3, 0), val);