Mercurial > hg > release > icedtea7-2.5
changeset 1782:28c8fa90206c
2009-04-23 Xerxes R?nby <xerxes@zafena.se>
* ports/hotspot/src/share/vm/shark/sharkBuilder.cpp
(SharkBuilder::init_external_functions): Use memory address to
kernel helper __kernel_dmb on arm for memory barrier.
* ports/hotspot/src/os_cpu/linux_zero/vm/orderAccess_linux_zero.inline.hpp
(__kernel_dmb_t): New type.
(__kernel_dmb): New macro.
(FULL_MEM_BARRIER): New macro that uses __kernel_dmb on arm
and __sync_synchronize on all other architectures.
(READ_MEM_BARRIER): Updated to use __kernel_dmb on arm.
(WRITE_MEM_BARRIER): Likewise.
(OrderAccess::fence): Updated to use FULL_MEM_BARRIER.
author | Xerxes R?nby <xerxes@zafena.se> |
---|---|
date | Thu, 23 Apr 2009 16:59:47 +0200 |
parents | e8364b501de4 |
children | ee08e16e223e |
files | ChangeLog ports/hotspot/src/os_cpu/linux_zero/vm/orderAccess_linux_zero.inline.hpp ports/hotspot/src/share/vm/shark/sharkBuilder.cpp |
diffstat | 3 files changed, 49 insertions(+), 1 deletions(-) [+] |
line wrap: on
line diff
--- a/ChangeLog Tue May 19 15:58:51 2009 +0100 +++ b/ChangeLog Thu Apr 23 16:59:47 2009 +0200 @@ -1,3 +1,17 @@ +2009-04-23 Xerxes Rånby <xerxes@zafena.se> + + * ports/hotspot/src/share/vm/shark/sharkBuilder.cpp + (SharkBuilder::init_external_functions): Use memory address to + kernel helper __kernel_dmb on arm for memory barrier. + * ports/hotspot/src/os_cpu/linux_zero/vm/orderAccess_linux_zero.inline.hpp + (__kernel_dmb_t): New type. + (__kernel_dmb): New macro. + (FULL_MEM_BARRIER): New macro that uses __kernel_dmb on arm + and __sync_synchronize on all other architectures. + (READ_MEM_BARRIER): Updated to use __kernel_dmb on arm. + (WRITE_MEM_BARRIER): Likewise. + (OrderAccess::fence): Updated to use FULL_MEM_BARRIER. + 2009-04-23 Xerxes Rånby <xerxes@zafena.se> * ports/hotspot/src/share/vm/shark/sharkBuilder.cpp
--- a/ports/hotspot/src/os_cpu/linux_zero/vm/orderAccess_linux_zero.inline.hpp Tue May 19 15:58:51 2009 +0100 +++ b/ports/hotspot/src/os_cpu/linux_zero/vm/orderAccess_linux_zero.inline.hpp Thu Apr 23 16:59:47 2009 +0200 @@ -23,6 +23,25 @@ * */ +#ifdef ARM + +/* + * ARM Kernel helper for memory barrier. + * Using __asm __volatile ("":::"memory") does not work reliable on ARM + * and gcc __sync_synchronize(); implementation does not use the kernel + * helper for all gcc versions so it is unreliable to use as well. + */ +typedef void (__kernel_dmb_t) (void); +#define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0) + +#define FULL_MEM_BARRIER __kernel_dmb() +#define READ_MEM_BARRIER __kernel_dmb() +#define WRITE_MEM_BARRIER __kernel_dmb() + +#else // ARM + +#define FULL_MEM_BARRIER __sync_synchronize() + #ifdef PPC #define READ_MEM_BARRIER __asm __volatile ("isync":::"memory") @@ -39,6 +58,7 @@ #endif // PPC +#endif // ARM inline void OrderAccess::loadload() { acquire(); } @@ -58,7 +78,7 @@ inline void OrderAccess::fence() { - __sync_synchronize(); + FULL_MEM_BARRIER; } inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { jbyte data = *p; acquire(); return data; }
--- a/ports/hotspot/src/share/vm/shark/sharkBuilder.cpp Tue May 19 15:58:51 2009 +0100 +++ b/ports/hotspot/src/share/vm/shark/sharkBuilder.cpp Thu Apr 23 16:59:47 2009 +0200 @@ -138,12 +138,26 @@ "llvm.atomic.cmp.swap.i" LP64_ONLY("64") NOT_LP64("32"), type)); #endif + /* + * The five booleans passed to llvm.memory.barrier are used like this: + * The first four arguments enables a specific barrier in this order: + * load-load, load-store, store-load and store-store. + * The fith argument specifies that the barrier applies to io or device + * or uncached memory. + */ params.clear(); for (int i = 0; i < 5; i++) params.push_back(Type::Int1Ty); type = FunctionType::get(Type::VoidTy, params, false); set_llvm_memory_barrier_fn( +#ifdef ARM + make_function( + 0xffff0fa0, // __kernel_dmb + type, + "__kernel_dmb")); +#else module()->getOrInsertFunction("llvm.memory.barrier", type)); +#endif params.clear(); params.push_back(SharkType::jdouble_type());