Mercurial > hg > openjdk6-mips
changeset 11:d3aee0aef6b6
Avoid anti-dependency when moving long operand between registers(reg2reg) and enable the safepoint return.
1. Avoid anti-dependency when moving long operand between registers(reg2reg)
2. Enable the safepoint return.
3. Do some codes cleaning work.
| author | YANG Yongqiang <yangyongqiang@loongson.cn> |
|---|---|
| date | Sun, 24 Oct 2010 14:32:13 +0000 |
| parents | 7eeee95a5a53 |
| children | 89199c685d4a |
| files | hotspot/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp hotspot/src/share/vm/oops/oop.inline.hpp hotspot/src/share/vm/runtime/reflection.cpp |
| diffstat | 3 files changed, 1306 insertions(+), 1417 deletions(-) [+] |
line wrap: on
line diff
--- a/hotspot/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp Sat Oct 23 21:08:56 2010 +0000 +++ b/hotspot/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp Sun Oct 24 14:32:13 2010 +0000 @@ -53,7 +53,6 @@ assert_different_registers(tmp1, tmp2, tmp3, extra); tmp1 = extra; } else if (tmp2 == preserve) { - //////assert_different_registers(tmp1, tmp2, tmp3, extra); tmp2 = extra; } else if (tmp3 == preserve) { assert_different_registers(tmp1, tmp2, tmp3, extra); @@ -79,7 +78,6 @@ } //FIXME, which register should be used? LIR_Opr LIR_Assembler::receiverOpr() { - //return FrameMap::ecx_oop_opr; return FrameMap::_t0_oop_opr; } @@ -165,7 +163,6 @@ } else { ShouldNotReachHere(); } - } else { ShouldNotReachHere(); } @@ -173,7 +170,6 @@ void LIR_Assembler::pop(LIR_Opr opr) { if (opr->is_single_cpu() ) { - // __ pop(opr->rinfo().as_register()); __ pop(opr->as_register()); } else { assert(false, "Must be single word register or floating-point register"); @@ -184,7 +180,6 @@ Address LIR_Assembler::as_Address(LIR_Address* addr) { Register reg = addr->base()->as_register(); // now we need this for parameter pass - //assert(reg != SP && reg != FP, "address must be in heap, not stack"); return Address(reg, addr->disp()); } @@ -244,7 +239,7 @@ Register OSR_buf = osrBufferPointer()->as_register(); - // note: we do osr only if the expression stack at the loop beginning is empty, + // note: we do osr only if the expression stack at the loop beginning is empty, // in which case the spill area is empty too and we don't have to setup // spilled locals // @@ -320,11 +315,8 @@ Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); __ lea(lock_reg, lock_addr); // unlock object - // MonitorAccessStub* slow_case = new MonitorExitStub(lock_, true, monitor_no); MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); - // _slow_case_stubs->append(slow_case); // temporary fix: must be created after exceptionhandler, therefore as call stub - //_call_stubs->append(slow_case); _slow_case_stubs->append(slow_case); if (UseFastLocking) { // try inlined fast unlocking first, revert to slow locking if it fails @@ -368,13 +360,11 @@ // but since this never gets executed it doesn't really make // much difference. // -// for (int i = 0; i < (NativeCall::instruction_size/4 + 1) ; i++ ) { - for (int i = 0; i < (NativeCall::instruction_size/2+1) ; i++ ) { + for (int i = 0; i < (NativeCall::instruction_size/4 + 1) ; i++ ) { __ nop(); } // generate code for exception handler - //address handler_base = __ start_a_stub(1*K);//by_css address handler_base = __ start_a_stub(exception_handler_size); if (handler_base == NULL) { //no enough space @@ -390,8 +380,6 @@ if (compilation()->has_exception_handlers() || JvmtiExport::can_post_exceptions()) { // the exception oop and pc are in V0 and V1 // no other registers need to be preserved, so invalidate them -// __ invalidate_registers(false, true, true, false, true, true); - // check that there is really an exception __ verify_not_null_oop(V0); @@ -405,8 +393,6 @@ // the exception oop is in V0 // no other registers need to be preserved, so invalidate them -// __ invalidate_registers(false, true, true, true, true, true); - // check that there is really an exception __ verify_not_null_oop(V0); @@ -419,19 +405,11 @@ // unwind activation and forward exception to caller // V0: exception - /*if (compilation()->jvmpi_event_method_exit_enabled()) { - __ jmp(Runtime1::entry_for(Runtime1::jvmpi_unwind_exception_id), + __ jmp(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); - } else*/ { - __ jmp(Runtime1::entry_for(Runtime1::unwind_exception_id), - relocInfo::runtime_call_type); - } __ delayed()->nop(); __ end_a_stub(); - - - - } +} void LIR_Assembler::emit_deopt_handler() { // if the last instruction is a call (typically to do a throw which @@ -459,11 +437,6 @@ //FIXE:: may be wrong, Address_Literal __ lw(AT, __ as_Address(here) ); __ push(AT); - - //XXXXX:FIXE need jump - -// __ jr(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); - assert(code_offset() - offset <= deopt_handler_size, "overflow"); __ end_a_stub(); @@ -478,12 +451,6 @@ // get two string object in T0&T1 //receiver already in T0 __ lw(T1, arg1->as_register()); - - // Get addresses of first characters from both Strings - { - // CodeEmitInfo* info = new CodeEmitInfo(scope, 0, NULL); - // add_debug_info_for_null_check_here(info); - } __ lw (T2, T0, java_lang_String::value_offset_in_bytes()); //value, T_CHAR array __ lw (AT, T0, java_lang_String::offset_offset_in_bytes()); //offset __ shl(AT, 1); @@ -491,10 +458,7 @@ __ addi(T2, T2, arrayOopDesc::base_offset_in_bytes(T_CHAR)); // Now T2 is the address of the first char in first string(T0) - { - // CodeEmitInfo* info = new CodeEmitInfo(scope, 0, NULL); - add_debug_info_for_null_check_here(info); - } + add_debug_info_for_null_check_here(info); __ lw (T3, T1, java_lang_String::value_offset_in_bytes()); __ lw (AT, T1, java_lang_String::offset_offset_in_bytes()); __ shl(AT, 1); @@ -537,24 +501,20 @@ __ subu(V0, T5, T6); __ bind(LoopEnd); - //return_op(FrameMap::_v0RInfo, false); - //FIXME return_op(FrameMap::_v0_opr); } -//void LIR_Assembler::return_op(RInfo result, bool result_is_oop) { void LIR_Assembler::return_op(LIR_Opr result) { assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == V0, "word returns are in V0"); // Pop the stack before the safepoint code __ leave(); - //FIXME I have no idea it is safe to use A0 -/* __ lui(AT, Assembler::split_high((intptr_t)os::get_polling_page() + __ lui(AT, Assembler::split_high((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()))); __ relocate(relocInfo::poll_return_type); __ lw(AT, AT, Assembler::split_low((intptr_t)os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()))); -*/ + __ jr(RA); __ delayed()->nop(); } @@ -589,115 +549,112 @@ assert(dest->is_register(), "should not call otherwise"); LIR_Const* c = src->as_constant_ptr(); switch (c->type()) { - case T_INT: - { - jint con = c->as_jint(); - if (dest->is_single_cpu()) { - assert(patch_code == lir_patch_none, "no patching handled here"); - __ move(dest->as_register(), con); - } else { - assert(dest->is_single_fpu(), "wrong register kind"); - __ move(AT, con); - __ mtc1(AT, dest->as_float_reg()); - } - } - break; - - case T_LONG: - { - jlong con = c->as_jlong(); - jint* conhi = (jint*)&con + 1; - jint* conlow = (jint*)&con; - - if (dest->is_double_cpu()) { - __ move(dest->as_register_lo(), *conlow); - __ move(dest->as_register_hi(), *conhi); - } else { - // assert(dest->is_double(), "wrong register kind"); - __ move(AT, *conlow); - __ mtc1(AT, dest->as_double_reg()); - __ move(AT, *conhi); - __ mtc1(AT, dest->as_double_reg()+1); - } - } - break; - - case T_OBJECT: - { - if (patch_code == lir_patch_none) { - if (c->as_jobject() == NULL) { - NEEDS_CLEANUP - int oop_index = __ oop_recorder()->allocate_index(c->as_jobject()); - RelocationHolder rspec = oop_Relocation::spec(oop_index); - __ relocate(rspec); - __ lui(dest->as_register(), Assembler::split_high((int) c->as_jobject() )); - __ addiu( dest->as_register() , dest->as_register() , Assembler::split_low((int) c->as_jobject())); - - - //__ move(dest->as_register(), ZERO); - } else { - int oop_index = __ oop_recorder()->find_index(c->as_jobject()); - RelocationHolder rspec = oop_Relocation::spec(oop_index); - __ relocate(rspec); - __ lui(dest->as_register(), Assembler::split_high((int)c->as_jobject())); - __ addiu(dest->as_register(), dest->as_register(), Assembler::split_low((int)c->as_jobject())); - } - } else { - jobject2reg_with_patching(dest->as_register(), info); - } - } - break; - - case T_FLOAT: - { - address const_addr = float_constant(c->as_jfloat()); - assert (const_addr != NULL, "must create float constant in the constant table"); - - if (dest->is_single_fpu()) { - __ relocate(relocInfo::internal_pc_type); - __ lui(AT, Assembler::split_high((int)const_addr)); - __ addiu(AT, AT, Assembler::split_low((int)const_addr)); - __ lwc1(dest->as_float_reg(), AT, 0); - - } else { - assert(dest->is_single_cpu(), "Must be a cpu register."); - assert(dest->as_register() != AT, "AT can not be allocated."); - - __ relocate(relocInfo::internal_pc_type); - __ lui(AT, Assembler::split_high((int)const_addr)); - __ addiu(AT, AT, Assembler::split_low((int)const_addr)); - __ lw(dest->as_register(), AT, 0); - } - } - break; - - case T_DOUBLE: - { - address const_addr = double_constant(c->as_jdouble()); - assert (const_addr != NULL, "must create double constant in the constant table"); - - if (dest->is_double_fpu()) { - __ relocate(relocInfo::internal_pc_type); - __ lui(AT, Assembler::split_high((int)const_addr)); - __ addiu(AT, AT, Assembler::split_low((int)const_addr)); - __ lwc1(dest->as_double_reg(), AT, 0); - __ lwc1(dest->as_double_reg()+1, AT, 4); - } else { -// assert(dest->is_long(), "Must be a long register."); - assert(dest->as_register_lo() != AT, "AT can not be allocated."); - assert(dest->as_register_hi() != AT, "AT can not be allocated."); - - __ relocate(relocInfo::internal_pc_type); - __ lui(AT, Assembler::split_high((int)const_addr)); - __ addiu(AT, AT, Assembler::split_low((int)const_addr)); - __ lw(dest->as_register_lo(), AT, 0); - __ lw(dest->as_register_hi(), AT, 4); - } - } - break; - - default: - ShouldNotReachHere(); + case T_INT: + { + jint con = c->as_jint(); + if (dest->is_single_cpu()) { + assert(patch_code == lir_patch_none, "no patching handled here"); + __ move(dest->as_register(), con); + } else { + assert(dest->is_single_fpu(), "wrong register kind"); + __ move(AT, con); + __ mtc1(AT, dest->as_float_reg()); + } + } + break; + + case T_LONG: + { + jlong con = c->as_jlong(); + jint* conhi = (jint*)&con + 1; + jint* conlow = (jint*)&con; + + if (dest->is_double_cpu()) { + __ move(dest->as_register_lo(), *conlow); + __ move(dest->as_register_hi(), *conhi); + } else { + // assert(dest->is_double(), "wrong register kind"); + __ move(AT, *conlow); + __ mtc1(AT, dest->as_double_reg()); + __ move(AT, *conhi); + __ mtc1(AT, dest->as_double_reg()+1); + } + } + break; + + case T_OBJECT: + { + if (patch_code == lir_patch_none) { + if (c->as_jobject() == NULL) { + NEEDS_CLEANUP + int oop_index = __ oop_recorder()->allocate_index(c->as_jobject()); + RelocationHolder rspec = oop_Relocation::spec(oop_index); + __ relocate(rspec); + __ lui(dest->as_register(), Assembler::split_high((int) c->as_jobject() )); + __ addiu( dest->as_register() , dest->as_register() , + Assembler::split_low((int) c->as_jobject())); + } else { + int oop_index = __ oop_recorder()->find_index(c->as_jobject()); + RelocationHolder rspec = oop_Relocation::spec(oop_index); + __ relocate(rspec); + __ lui(dest->as_register(), Assembler::split_high((int)c->as_jobject())); + __ addiu(dest->as_register(), dest->as_register(), Assembler::split_low((int)c->as_jobject())); + } + } else { + jobject2reg_with_patching(dest->as_register(), info); + } + } + break; + + case T_FLOAT: + { + address const_addr = float_constant(c->as_jfloat()); + assert (const_addr != NULL, "must create float constant in the constant table"); + + if (dest->is_single_fpu()) { + __ relocate(relocInfo::internal_pc_type); + __ lui(AT, Assembler::split_high((int)const_addr)); + __ addiu(AT, AT, Assembler::split_low((int)const_addr)); + __ lwc1(dest->as_float_reg(), AT, 0); + + } else { + assert(dest->is_single_cpu(), "Must be a cpu register."); + assert(dest->as_register() != AT, "AT can not be allocated."); + + __ relocate(relocInfo::internal_pc_type); + __ lui(AT, Assembler::split_high((int)const_addr)); + __ addiu(AT, AT, Assembler::split_low((int)const_addr)); + __ lw(dest->as_register(), AT, 0); + } + } + break; + + case T_DOUBLE: + { + address const_addr = double_constant(c->as_jdouble()); + assert (const_addr != NULL, "must create double constant in the constant table"); + + if (dest->is_double_fpu()) { + __ relocate(relocInfo::internal_pc_type); + __ lui(AT, Assembler::split_high((int)const_addr)); + __ addiu(AT, AT, Assembler::split_low((int)const_addr)); + __ lwc1(dest->as_double_reg(), AT, 0); + __ lwc1(dest->as_double_reg()+1, AT, 4); + } else { + assert(dest->as_register_lo() != AT, "AT can not be allocated."); + assert(dest->as_register_hi() != AT, "AT can not be allocated."); + + __ relocate(relocInfo::internal_pc_type); + __ lui(AT, Assembler::split_high((int)const_addr)); + __ addiu(AT, AT, Assembler::split_low((int)const_addr)); + __ lw(dest->as_register_lo(), AT, 0); + __ lw(dest->as_register_hi(), AT, 4); + } + } + break; + + default: + ShouldNotReachHere(); } } @@ -804,8 +761,16 @@ } else if (dest->is_double_cpu()) { // assert(src->is_double_cpu() && !src->overlaps(dest), "must match and not overlap"); assert(src->is_double_cpu(),"must match and not overlap"); - move_regs(src->as_register_lo(), dest->as_register_lo()); - move_regs(src->as_register_hi(), dest->as_register_hi()); + if (src->as_register_hi() != dest->as_register_lo()) { + move_regs(src->as_register_lo(), dest->as_register_lo()); + move_regs(src->as_register_hi(), dest->as_register_hi()); + } else if (src->as_register_lo() != dest->as_register_hi()) { + move_regs(src->as_register_hi(), dest->as_register_hi()); + move_regs(src->as_register_lo(), dest->as_register_lo()); + } else { + swap_reg(src->as_register_lo(), src->as_register_hi()); + } + } } else { // float to int or int to float moves @@ -855,15 +820,15 @@ } else { ShouldNotReachHere(); } - - } +} + //FIXME void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info,bool pop_fpu_stack, bool/*unaliged*/) { - LIR_Address* to_addr = dest->as_address_ptr(); - Register dest_reg = to_addr->base()->as_register(); + LIR_Address* to_addr = dest->as_address_ptr(); + Register dest_reg = to_addr->base()->as_register(); PatchingStub* patch = NULL; bool needs_patching = (patch_code != lir_patch_none); - Register disp_reg = NOREG; + Register disp_reg = NOREG; int disp_value = to_addr->disp(); if (type == T_ARRAY || type == T_OBJECT) { @@ -879,8 +844,8 @@ } if (info != NULL) { - add_debug_info_for_null_check_here(info); - } + add_debug_info_for_null_check_here(info); + } if (needs_patching) { disp_reg = AT; __ lui(AT, Assembler::split_high(disp_value)); @@ -926,41 +891,36 @@ } break; - case T_LONG:{ - - Register from_lo = src->as_register_lo(); - Register from_hi = src->as_register_hi(); - Register base = to_addr->base()->as_register(); - Register index = noreg; - if (to_addr->index()->is_register()) { - index = to_addr->index()->as_register(); - } - if (base == from_lo || index == from_lo) { - assert(base != from_hi, "can't be"); - assert(index == noreg || (index != base && index != from_hi), "can't handle this"); - // __ movl(as_Address_hi(to_addr), from_hi); - __ sw(from_hi,as_Address_hi(to_addr)); - if (patch != NULL) { - patching_epilog(patch, lir_patch_high, base, info); - patch = new PatchingStub(_masm, PatchingStub::access_field_id); - patch_code = lir_patch_low; - } - //__ movl(as_Address_lo(to_addr), from_lo); - __ sw(from_lo,as_Address_lo(to_addr)); - } else { - assert(index == noreg || (index != base && index != from_lo), "can't handle this"); - // __ movl(as_Address_lo(to_addr), from_lo); - __ sw(from_lo,as_Address_lo(to_addr)); - if (patch != NULL) { - patching_epilog(patch, lir_patch_low, base, info); - patch = new PatchingStub(_masm, PatchingStub::access_field_id); - patch_code = lir_patch_high; - } - //__ movl(as_Address_hi(to_addr), from_hi); - __ sw(from_hi,as_Address_hi(to_addr)); - } + case T_LONG: { + Register from_lo = src->as_register_lo(); + Register from_hi = src->as_register_hi(); + Register base = to_addr->base()->as_register(); + Register index = noreg; + if (to_addr->index()->is_register()) { + index = to_addr->index()->as_register(); + } + if (base == from_lo || index == from_lo) { + assert(base != from_hi, "can't be"); + assert(index == noreg || (index != base && index != from_hi), "can't handle this"); + __ sw(from_hi,as_Address_hi(to_addr)); + if (patch != NULL) { + patching_epilog(patch, lir_patch_high, base, info); + patch = new PatchingStub(_masm, PatchingStub::access_field_id); + patch_code = lir_patch_low; + } + __ sw(from_lo,as_Address_lo(to_addr)); + } else { + assert(index == noreg || (index != base && index != from_lo), "can't handle this"); + __ sw(from_lo,as_Address_lo(to_addr)); + if (patch != NULL) { + patching_epilog(patch, lir_patch_low, base, info); + patch = new PatchingStub(_masm, PatchingStub::access_field_id); + patch_code = lir_patch_high; + } + __ sw(from_hi,as_Address_hi(to_addr)); + } break; - } + } case T_ADDRESS: case T_ARRAY: case T_OBJECT: @@ -1020,8 +980,6 @@ if (needs_patching) { patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); } - - } @@ -1030,7 +988,6 @@ assert(src->is_stack(), "should not call otherwise"); assert(dest->is_register(), "should not call otherwise"); if (dest->is_single_cpu()) { - // __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); __ lw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); if (type == T_ARRAY || type == T_OBJECT) { __ verify_oop(dest->as_register()); @@ -1058,29 +1015,13 @@ void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { if (src->is_single_stack()) { -// __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); __ lw(AT, frame_map()->address_for_slot(src ->single_stack_ix())); - //__ push(AT); - //__ push(frame_map()->address_for_slot(src ->single_stack_ix())); - // __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); - // __ pop (frame_map()->address_for_slot(dest->single_stack_ix())); __ sw(AT, frame_map()->address_for_slot(dest->single_stack_ix())); - } else if (src->is_double_stack()) { - //__ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); - // __ push(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); __ lw(AT, frame_map()->address_for_slot(src ->double_stack_ix())); __ sw(AT, frame_map()->address_for_slot(dest->double_stack_ix())); - // __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 4)); - // __ push(frame_map()->address_for_slot(src ->double_stack_ix(), 4)); __ lw(AT, frame_map()->address_for_slot(src ->double_stack_ix(),4)); __ sw(AT, frame_map()->address_for_slot(dest ->double_stack_ix(),4)); - - //__ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 4)); - //__ pop (frame_map()->address_for_slot(dest->double_stack_ix(), 4)); - //__ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); - // __ pop (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); - } else { ShouldNotReachHere(); } @@ -1089,12 +1030,11 @@ // if patching needed, be sure the instruction at offset is a MoveMemReg -//void LIR_Assembler::mem2reg(LIR_Address* addr, RInfo to_reg, BasicType type, LIR_Op1::LIR_PatchCode patch_code, CodeEmitInfo* info) { void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool) { assert(src->is_address(), "should not call otherwise"); - assert(dest->is_register(), "should not call otherwise"); - LIR_Address* addr = src->as_address_ptr(); - Address from_addr = as_Address(addr); + assert(dest->is_register(), "should not call otherwise"); + LIR_Address* addr = src->as_address_ptr(); + Address from_addr = as_Address(addr); Register src_reg = addr->base()->as_register(); Register disp_reg = noreg; @@ -1124,155 +1064,146 @@ switch(type) { case T_BOOLEAN: - case T_BYTE: - { - //assert(to_reg.is_word(), "just check"); - if (disp_reg == noreg) { - __ lb(dest->as_register(), src_reg, disp_value); - } else if (needs_patching) { - __ add(AT, src_reg, disp_reg); - offset = code_offset(); - __ lb(dest->as_register(), AT, 0); - } else { - __ add(AT, src_reg, disp_reg); - offset = code_offset(); - __ lb(dest->as_register(), AT, Assembler::split_low(disp_value)); - } + case T_BYTE: { + //assert(to_reg.is_word(), "just check"); + if (disp_reg == noreg) { + __ lb(dest->as_register(), src_reg, disp_value); + } else if (needs_patching) { + __ add(AT, src_reg, disp_reg); + offset = code_offset(); + __ lb(dest->as_register(), AT, 0); + } else { + __ add(AT, src_reg, disp_reg); + offset = code_offset(); + __ lb(dest->as_register(), AT, Assembler::split_low(disp_value)); } - break; + } + break; - case T_CHAR: - { + case T_CHAR: { //assert(to_reg.is_word(), "just check"); - - if (disp_reg == noreg) { - __ lhu(dest->as_register(), src_reg, disp_value); - } else if (needs_patching) { - __ add(AT, src_reg, disp_reg); - offset = code_offset(); - __ lhu(dest->as_register(), AT, 0); - } else { - __ add(AT, src_reg, disp_reg); - offset = code_offset(); - __ lhu(dest->as_register(), AT, Assembler::split_low(disp_value)); - } + if (disp_reg == noreg) { + __ lhu(dest->as_register(), src_reg, disp_value); + } else if (needs_patching) { + __ add(AT, src_reg, disp_reg); + offset = code_offset(); + __ lhu(dest->as_register(), AT, 0); + } else { + __ add(AT, src_reg, disp_reg); + offset = code_offset(); + __ lhu(dest->as_register(), AT, Assembler::split_low(disp_value)); } - break; + } + break; - case T_SHORT: - { + case T_SHORT: { // assert(to_reg.is_word(), "just check"); - - if (disp_reg == noreg) { - __ lh(dest->as_register(), src_reg, disp_value); - } else if (needs_patching) { - __ add(AT, src_reg, disp_reg); - offset = code_offset(); - __ lh(dest->as_register(), AT, 0); - } else { - __ add(AT, src_reg, disp_reg); - offset = code_offset(); - __ lh(dest->as_register(), AT, Assembler::split_low(disp_value)); - } + if (disp_reg == noreg) { + __ lh(dest->as_register(), src_reg, disp_value); + } else if (needs_patching) { + __ add(AT, src_reg, disp_reg); + offset = code_offset(); + __ lh(dest->as_register(), AT, 0); + } else { + __ add(AT, src_reg, disp_reg); + offset = code_offset(); + __ lh(dest->as_register(), AT, Assembler::split_low(disp_value)); } - break; + } + break; case T_INT: case T_OBJECT: - case T_ARRAY: - { + case T_ARRAY: { //assert(to_reg.is_word(), "just check"); - - if (disp_reg == noreg) { - __ lw(dest->as_register(), src_reg, disp_value); - } else if (needs_patching) { - __ add(AT, src_reg, disp_reg); - offset = code_offset(); - __ lw(dest->as_register(), AT, 0); - } else { - __ add(AT, src_reg, disp_reg); - offset = code_offset(); - __ lw(dest->as_register(), AT, Assembler::split_low(disp_value)); - } + if (disp_reg == noreg) { + __ lw(dest->as_register(), src_reg, disp_value); + } else if (needs_patching) { + __ add(AT, src_reg, disp_reg); + offset = code_offset(); + __ lw(dest->as_register(), AT, 0); + } else { + __ add(AT, src_reg, disp_reg); + offset = code_offset(); + __ lw(dest->as_register(), AT, Assembler::split_low(disp_value)); } - break; + } + break; - case T_LONG: - { + case T_LONG: { Register to_lo = dest->as_register_lo(); - Register to_hi = dest->as_register_hi(); - Register base = addr->base()->as_register(); - Register index = noreg; - if (addr->index()->is_register()) { - index = addr->index()->as_register(); - } - if ((base == to_lo && index == to_hi) ||(base == to_hi && index == to_lo)) { - // addresses with 2 registers are only formed as a result of - // array access so this code will never have to deal with - // patches or null checks. - assert(info == NULL && patch == NULL, "must be"); - __ lea(to_hi, as_Address(addr)); - __ lw(to_lo, Address(to_hi)); - __ lw(to_hi, Address(to_hi, BytesPerWord)); - } else if (base == to_lo || index == to_lo) { - assert(base != to_hi, "can't be"); - assert(index == noreg || (index != base && index != to_hi), "can't handle this"); - __ lw(to_hi, as_Address_hi(addr)); - if (patch != NULL) { - patching_epilog(patch, lir_patch_high, base, info); - patch = new PatchingStub(_masm, PatchingStub::access_field_id); - patch_code = lir_patch_low; - } - __ lw(to_lo, as_Address_lo(addr)); - } else { - assert(index == noreg || (index != base && index != to_lo), "can't handle this"); - __ lw(to_lo, as_Address_lo(addr)); - if (patch != NULL) { - patching_epilog(patch, lir_patch_low, base, info); - patch = new PatchingStub(_masm, PatchingStub::access_field_id); - patch_code = lir_patch_high; - } - __ lw(to_hi, as_Address_hi(addr)); - } - break; - } - case T_FLOAT: - { - //assert(to_reg.is_float(), "just check"); - if (disp_reg == noreg) { - __ lwc1(dest->as_float_reg(), src_reg, disp_value); - } else if (needs_patching) { - __ add(AT, src_reg, disp_reg); - offset = code_offset(); - __ lwc1(dest->as_float_reg(), AT, 0); - } else { - __ add(AT, src_reg, disp_reg); - offset = code_offset(); - __ lwc1(dest->as_float_reg(), AT, Assembler::split_low(disp_value)); - } + Register to_hi = dest->as_register_hi(); + Register base = addr->base()->as_register(); + Register index = noreg; + if (addr->index()->is_register()) { + index = addr->index()->as_register(); + } + if ((base == to_lo && index == to_hi) ||(base == to_hi && index == to_lo)) { + // addresses with 2 registers are only formed as a result of + // array access so this code will never have to deal with + // patches or null checks. + assert(info == NULL && patch == NULL, "must be"); + __ lea(to_hi, as_Address(addr)); + __ lw(to_lo, Address(to_hi)); + __ lw(to_hi, Address(to_hi, BytesPerWord)); + } else if (base == to_lo || index == to_lo) { + assert(base != to_hi, "can't be"); + assert(index == noreg || (index != base && index != to_hi), "can't handle this"); + __ lw(to_hi, as_Address_hi(addr)); + if (patch != NULL) { + patching_epilog(patch, lir_patch_high, base, info); + patch = new PatchingStub(_masm, PatchingStub::access_field_id); + patch_code = lir_patch_low; + } + __ lw(to_lo, as_Address_lo(addr)); + } else { + assert(index == noreg || (index != base && index != to_lo), "can't handle this"); + __ lw(to_lo, as_Address_lo(addr)); + if (patch != NULL) { + patching_epilog(patch, lir_patch_low, base, info); + patch = new PatchingStub(_masm, PatchingStub::access_field_id); + patch_code = lir_patch_high; + } + __ lw(to_hi, as_Address_hi(addr)); + } + } + break; + + case T_FLOAT: { + //assert(to_reg.is_float(), "just check"); + if (disp_reg == noreg) { + __ lwc1(dest->as_float_reg(), src_reg, disp_value); + } else if (needs_patching) { + __ add(AT, src_reg, disp_reg); + offset = code_offset(); + __ lwc1(dest->as_float_reg(), AT, 0); + } else { + __ add(AT, src_reg, disp_reg); + offset = code_offset(); + __ lwc1(dest->as_float_reg(), AT, Assembler::split_low(disp_value)); } - break; + } + break; - case T_DOUBLE: - { - //assert(to_reg.is_double(), "just check"); + case T_DOUBLE: { + //assert(to_reg.is_double(), "just check"); - if (disp_reg == noreg) { - __ lwc1(dest->as_double_reg(), src_reg, disp_value); - __ lwc1(dest->as_double_reg()+1, src_reg, disp_value+4); - } else if (needs_patching) { - __ add(AT, src_reg, disp_reg); - offset = code_offset(); - __ lwc1(dest->as_double_reg(), AT, 0); - __ lwc1(dest->as_double_reg()+1, AT, 4); - } else { - __ add(AT, src_reg, disp_reg); - offset = code_offset(); - __ lwc1(dest->as_double_reg(), AT, Assembler::split_low(disp_value)); - __ lwc1(dest->as_double_reg()+1, AT, Assembler::split_low(disp_value) + 4); - } + if (disp_reg == noreg) { + __ lwc1(dest->as_double_reg(), src_reg, disp_value); + __ lwc1(dest->as_double_reg()+1, src_reg, disp_value+4); + } else if (needs_patching) { + __ add(AT, src_reg, disp_reg); + offset = code_offset(); + __ lwc1(dest->as_double_reg(), AT, 0); + __ lwc1(dest->as_double_reg()+1, AT, 4); + } else { + __ add(AT, src_reg, disp_reg); + offset = code_offset(); + __ lwc1(dest->as_double_reg(), AT, Assembler::split_low(disp_value)); + __ lwc1(dest->as_double_reg()+1, AT, Assembler::split_low(disp_value) + 4); } - break; + } + break; default: ShouldNotReachHere(); @@ -1340,7 +1271,6 @@ return; } if (opr1->is_single_cpu()) { - Register reg_op1 = opr1->as_register(); if (opr2->is_single_cpu()) { #ifdef OPT_RANGECHECK @@ -1348,43 +1278,43 @@ #endif Register reg_op2 = opr2->as_register(); switch (condition) { - case lir_cond_equal: - __ beq(reg_op1, reg_op2, *op->label()); - break; - case lir_cond_notEqual: - __ bne(reg_op1, reg_op2, *op->label()); - break; - case lir_cond_less: - // AT = 1 TRUE - __ slt(AT, reg_op1, reg_op2); - __ bne(AT, ZERO, *op->label()); - break; - case lir_cond_lessEqual: - // AT = 0 TRUE - __ slt(AT, reg_op2, reg_op1); - __ beq(AT, ZERO, *op->label()); - break; - case lir_cond_belowEqual: - // AT = 0 TRUE - __ sltu(AT, reg_op2, reg_op1); - __ beq(AT, ZERO, *op->label()); - break; - case lir_cond_greaterEqual: - // AT = 0 TRUE - __ slt(AT, reg_op1, reg_op2); - __ beq(AT, ZERO, *op->label()); - break; - case lir_cond_aboveEqual: - // AT = 0 TRUE - __ sltu(AT, reg_op1, reg_op2); - __ beq(AT, ZERO, *op->label()); - break; - case lir_cond_greater: - // AT = 1 TRUE - __ slt(AT, reg_op2, reg_op1); - __ bne(AT, ZERO, *op->label()); - break; - default: ShouldNotReachHere(); + case lir_cond_equal: + __ beq(reg_op1, reg_op2, *op->label()); + break; + case lir_cond_notEqual: + __ bne(reg_op1, reg_op2, *op->label()); + break; + case lir_cond_less: + // AT = 1 TRUE + __ slt(AT, reg_op1, reg_op2); + __ bne(AT, ZERO, *op->label()); + break; + case lir_cond_lessEqual: + // AT = 0 TRUE + __ slt(AT, reg_op2, reg_op1); + __ beq(AT, ZERO, *op->label()); + break; + case lir_cond_belowEqual: + // AT = 0 TRUE + __ sltu(AT, reg_op2, reg_op1); + __ beq(AT, ZERO, *op->label()); + break; + case lir_cond_greaterEqual: + // AT = 0 TRUE + __ slt(AT, reg_op1, reg_op2); + __ beq(AT, ZERO, *op->label()); + break; + case lir_cond_aboveEqual: + // AT = 0 TRUE + __ sltu(AT, reg_op1, reg_op2); + __ beq(AT, ZERO, *op->label()); + break; + case lir_cond_greater: + // AT = 1 TRUE + __ slt(AT, reg_op2, reg_op1); + __ bne(AT, ZERO, *op->label()); + break; + default: ShouldNotReachHere(); } } else if (opr2->is_constant()) { jint temp_value; @@ -1399,825 +1329,814 @@ } switch (condition) { - case lir_cond_equal: + case lir_cond_equal: #ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); + assert(!op->check(), "just check"); #endif - if (temp_value) { - if (is_object) { - int oop_index = __ oop_recorder()->allocate_index((jobject)temp_value); - RelocationHolder rspec = oop_Relocation::spec(oop_index); - __ relocate(rspec); - } - __ move(AT, temp_value); - __ beq(reg_op1, AT, *op->label()); - } else { - __ beq(reg_op1, ZERO, *op->label()); - } - break; - - case lir_cond_notEqual: + if (temp_value) { + if (is_object) { + int oop_index = __ oop_recorder()->allocate_index((jobject)temp_value); + RelocationHolder rspec = oop_Relocation::spec(oop_index); + __ relocate(rspec); + } + __ move(AT, temp_value); + __ beq(reg_op1, AT, *op->label()); + } else { + __ beq(reg_op1, ZERO, *op->label()); + } + break; + + case lir_cond_notEqual: #ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); + assert(!op->check(), "just check"); +#endif + if (temp_value) { + if (is_object) { + int oop_index = __ oop_recorder()->allocate_index((jobject)temp_value); + RelocationHolder rspec = oop_Relocation::spec(oop_index); + __ relocate(rspec); + } + __ move(AT, temp_value); + __ bne(reg_op1, AT, *op->label()); + } else { + __ bne(reg_op1, ZERO, *op->label()); + } + break; + + case lir_cond_less: +#ifdef OPT_RANGECHECK + assert(!op->check(), "just check"); #endif - if (temp_value) { - if (is_object) { - int oop_index = __ oop_recorder()->allocate_index((jobject)temp_value); - RelocationHolder rspec = oop_Relocation::spec(oop_index); - __ relocate(rspec); - } - __ move(AT, temp_value); - __ bne(reg_op1, AT, *op->label()); - } else { - __ bne(reg_op1, ZERO, *op->label()); - } - break; + // AT = 1 TRUE + if (Assembler::is_simm16(temp_value)) { + __ slti(AT, reg_op1, temp_value); + } else { + __ move(AT, temp_value); + __ slt(AT, reg_op1, AT); + } + __ bne(AT, ZERO, *op->label()); + break; - case lir_cond_less: + case lir_cond_lessEqual: #ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); + assert(!op->check(), "just check"); #endif - // AT = 1 TRUE - if (Assembler::is_simm16(temp_value)) { - __ slti(AT, reg_op1, temp_value); - } else { - __ move(AT, temp_value); - __ slt(AT, reg_op1, AT); - } - __ bne(AT, ZERO, *op->label()); - break; + // AT = 0 TRUE + __ move(AT, temp_value); + __ slt(AT, AT, reg_op1); + __ beq(AT, ZERO, *op->label()); + break; + + case lir_cond_belowEqual: + // AT = 0 TRUE +#ifdef OPT_RANGECHECK + if (op->check()) { + __ move(AT, temp_value); + add_debug_info_for_range_check_here(op->info(), temp_value); + __ tgeu(AT, reg_op1, 29); + } else { +#endif + __ move(AT, temp_value); + __ sltu(AT, AT, reg_op1); + __ beq(AT, ZERO, *op->label()); +#ifdef OPT_RANGECHECK + } +#endif + break; - case lir_cond_lessEqual: + case lir_cond_greaterEqual: #ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); + assert(!op->check(), "just check"); #endif - // AT = 0 TRUE - __ move(AT, temp_value); - __ slt(AT, AT, reg_op1); - __ beq(AT, ZERO, *op->label()); - break; + // AT = 0 TRUE + if (Assembler::is_simm16(temp_value)) { + __ slti(AT, reg_op1, temp_value); + } else { + __ move(AT, temp_value); + __ slt(AT, reg_op1, AT); + } + __ beq(AT, ZERO, *op->label()); + break; - case lir_cond_belowEqual: - // AT = 0 TRUE + case lir_cond_aboveEqual: #ifdef OPT_RANGECHECK - if (op->check()) { - __ move(AT, temp_value); - add_debug_info_for_range_check_here(op->info(), temp_value); - __ tgeu(AT, reg_op1, 29); - } else { + assert(!op->check(), "just check"); #endif - __ move(AT, temp_value); - __ sltu(AT, AT, reg_op1); - __ beq(AT, ZERO, *op->label()); -#ifdef OPT_RANGECHECK - } -#endif - break; - - case lir_cond_greaterEqual: + // AT = 0 TRUE + if (Assembler::is_simm16(temp_value)) { + __ sltiu(AT, reg_op1, temp_value); + } else { + __ move(AT, temp_value); + __ sltu(AT, reg_op1, AT); + } + __ beq(AT, ZERO, *op->label()); + break; + + case lir_cond_greater: #ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); + assert(!op->check(), "just check"); #endif - // AT = 0 TRUE - if (Assembler::is_simm16(temp_value)) { - __ slti(AT, reg_op1, temp_value); - } else { - __ move(AT, temp_value); - __ slt(AT, reg_op1, AT); - } - __ beq(AT, ZERO, *op->label()); - break; - - case lir_cond_aboveEqual: + // AT = 1 TRUE + __ move(AT, temp_value); + __ slt(AT, AT, reg_op1); + __ bne(AT, ZERO, *op->label()); + break; + + default: ShouldNotReachHere(); + } + + } else { + if (opr2->is_address()) { + __ lw(AT, as_Address(opr2->pointer()->as_address())); + } else if (opr2->is_stack()) { + __ lw(AT, frame_map()->address_for_slot(opr2->single_stack_ix())); + } else { + ShouldNotReachHere(); + } + switch (condition) { + case lir_cond_equal: #ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); + assert(!op->check(), "just check"); +#endif + __ beq(reg_op1, AT, *op->label()); + break; + case lir_cond_notEqual: +#ifdef OPT_RANGECHECK + assert(!op->check(), "just check"); +#endif + __ bne(reg_op1, AT, *op->label()); + break; + case lir_cond_less: +#ifdef OPT_RANGECHECK + assert(!op->check(), "just check"); #endif - // AT = 0 TRUE - if (Assembler::is_simm16(temp_value)) { - __ sltiu(AT, reg_op1, temp_value); - } else { - __ move(AT, temp_value); - __ sltu(AT, reg_op1, AT); - } - __ beq(AT, ZERO, *op->label()); - break; - - case lir_cond_greater: + // AT = 1 TRUE + __ slt(AT, reg_op1, AT); + __ bne(AT, ZERO, *op->label()); + break; + case lir_cond_lessEqual: #ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); + assert(!op->check(), "just check"); +#endif + // AT = 0 TRUE + __ slt(AT, AT, reg_op1); + __ beq(AT, ZERO, *op->label()); + break; + case lir_cond_belowEqual: +#ifdef OPT_RANGECHECK + assert(!op->check(), "just check"); +#endif + // AT = 0 TRUE + __ sltu(AT, AT, reg_op1); + __ beq(AT, ZERO, *op->label()); + break; + case lir_cond_greaterEqual: +#ifdef OPT_RANGECHECK + assert(!op->check(), "just check"); #endif - // AT = 1 TRUE - __ move(AT, temp_value); - __ slt(AT, AT, reg_op1); - __ bne(AT, ZERO, *op->label()); - break; - - default: ShouldNotReachHere(); - } - - } else { - if (opr2->is_address()) { - __ lw(AT, as_Address(opr2->pointer()->as_address())); - } else if (opr2->is_stack()) { - __ lw(AT, frame_map()->address_for_slot(opr2->single_stack_ix())); - } else { - ShouldNotReachHere(); - } - switch (condition) { - case lir_cond_equal: + // AT = 0 TRUE + __ slt(AT, reg_op1, AT); + __ beq(AT, ZERO, *op->label()); + break; + case lir_cond_aboveEqual: + // AT = 0 TRUE +#ifdef OPT_RANGECHECK + if (op->check()) { + add_debug_info_for_range_check_here(op->info(), opr1->rinfo()); + __ tgeu(reg_op1, AT, 29); + } else { +#endif + __ sltu(AT, reg_op1, AT); + __ beq(AT, ZERO, *op->label()); #ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); + } +#endif + break; + case lir_cond_greater: +#ifdef OPT_RANGECHECK + assert(!op->check(), "just check"); #endif - __ beq(reg_op1, AT, *op->label()); - break; - case lir_cond_notEqual: + // AT = 1 TRUE + __ slt(AT, AT, reg_op1); + __ bne(AT, ZERO, *op->label()); + break; + default: ShouldNotReachHere(); + } + } +#ifdef OPT_RANGECHECK + if (!op->check()) +#endif + __ delayed()->nop(); + + } else if(opr1->is_address() || opr1->is_stack()) { #ifdef OPT_RANGECHECK assert(!op->check(), "just check"); #endif - __ bne(reg_op1, AT, *op->label()); - break; - case lir_cond_less: -#ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); -#endif - // AT = 1 TRUE - __ slt(AT, reg_op1, AT); - __ bne(AT, ZERO, *op->label()); - break; - case lir_cond_lessEqual: -#ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); -#endif - // AT = 0 TRUE - __ slt(AT, AT, reg_op1); - __ beq(AT, ZERO, *op->label()); - break; - case lir_cond_belowEqual: -#ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); -#endif - // AT = 0 TRUE - __ sltu(AT, AT, reg_op1); - __ beq(AT, ZERO, *op->label()); - break; - case lir_cond_greaterEqual: -#ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); -#endif - // AT = 0 TRUE - __ slt(AT, reg_op1, AT); - __ beq(AT, ZERO, *op->label()); - break; - case lir_cond_aboveEqual: - // AT = 0 TRUE -#ifdef OPT_RANGECHECK - if (op->check()) { - add_debug_info_for_range_check_here(op->info(), opr1->rinfo()); - __ tgeu(reg_op1, AT, 29); - } else { -#endif - __ sltu(AT, reg_op1, AT); - __ beq(AT, ZERO, *op->label()); -#ifdef OPT_RANGECHECK - } -#endif - break; - case lir_cond_greater: -#ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); -#endif - // AT = 1 TRUE - __ slt(AT, AT, reg_op1); - __ bne(AT, ZERO, *op->label()); - break; - default: ShouldNotReachHere(); - } - } -#ifdef OPT_RANGECHECK - if (!op->check()) -#endif - __ delayed()->nop(); - - } else if(opr1->is_address() || opr1->is_stack()) { -#ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); -#endif - if (opr2->is_constant()) { - jint temp_value; - if (opr2->as_constant_ptr()->type() == T_INT) { - temp_value = (jint)opr2->as_constant_ptr()->as_jint(); - } else if (opr2->as_constant_ptr()->type() == T_OBJECT) { - temp_value = (jint)opr2->as_constant_ptr()->as_jobject(); + if (opr2->is_constant()) { + jint temp_value; + if (opr2->as_constant_ptr()->type() == T_INT) { + temp_value = (jint)opr2->as_constant_ptr()->as_jint(); + } else if (opr2->as_constant_ptr()->type() == T_OBJECT) { + temp_value = (jint)opr2->as_constant_ptr()->as_jobject(); + } else { + ShouldNotReachHere(); + } + + if (Assembler::is_simm16(temp_value)) { + if (opr1->is_address()) { + __ lw(AT, as_Address(opr1->pointer()->as_address())); + } else { + __ lw(AT, frame_map()->address_for_slot(opr1->single_stack_ix())); + } + + switch(condition) { + + case lir_cond_equal: + __ addi(AT, AT, -(int)temp_value); + __ beq(AT, ZERO, *op->label()); + break; + case lir_cond_notEqual: + __ addi(AT, AT, -(int)temp_value); + __ bne(AT, ZERO, *op->label()); + break; + case lir_cond_less: + // AT = 1 TRUE + __ slti(AT, AT, temp_value); + __ bne(AT, ZERO, *op->label()); + break; + case lir_cond_lessEqual: + // AT = 0 TRUE + __ addi(AT, AT, -temp_value); + __ slt(AT, ZERO, AT); + __ beq(AT, ZERO, *op->label()); + break; + case lir_cond_belowEqual: + // AT = 0 TRUE + __ addiu(AT, AT, -temp_value); + __ sltu(AT, ZERO, AT); + __ beq(AT, ZERO, *op->label()); + break; + case lir_cond_greaterEqual: + // AT = 0 TRUE + __ slti(AT, AT, temp_value); + __ beq(AT, ZERO, *op->label()); + break; + case lir_cond_aboveEqual: + // AT = 0 TRUE + __ sltiu(AT, AT, temp_value); + __ beq(AT, ZERO, *op->label()); + break; + case lir_cond_greater: + // AT = 1 TRUE + __ addi(AT, AT, -temp_value); + __ slt(AT, ZERO, AT); + __ bne(AT, ZERO, *op->label()); + break; + + default: + Unimplemented(); + } + } else { + Unimplemented(); + } } else { - ShouldNotReachHere(); - } - - if (Assembler::is_simm16(temp_value)) { - if (opr1->is_address()) { - __ lw(AT, as_Address(opr1->pointer()->as_address())); - } else { - __ lw(AT, frame_map()->address_for_slot(opr1->single_stack_ix())); - } - - switch(condition) { - - case lir_cond_equal: - __ addi(AT, AT, -(int)temp_value); - __ beq(AT, ZERO, *op->label()); - break; - case lir_cond_notEqual: - __ addi(AT, AT, -(int)temp_value); - __ bne(AT, ZERO, *op->label()); - break; - case lir_cond_less: - // AT = 1 TRUE - __ slti(AT, AT, temp_value); - __ bne(AT, ZERO, *op->label()); - break; - case lir_cond_lessEqual: - // AT = 0 TRUE - __ addi(AT, AT, -temp_value); - __ slt(AT, ZERO, AT); - __ beq(AT, ZERO, *op->label()); - break; - case lir_cond_belowEqual: - // AT = 0 TRUE - __ addiu(AT, AT, -temp_value); - __ sltu(AT, ZERO, AT); - __ beq(AT, ZERO, *op->label()); - break; - case lir_cond_greaterEqual: - // AT = 0 TRUE - __ slti(AT, AT, temp_value); - __ beq(AT, ZERO, *op->label()); - break; - case lir_cond_aboveEqual: - // AT = 0 TRUE - __ sltiu(AT, AT, temp_value); - __ beq(AT, ZERO, *op->label()); - break; - case lir_cond_greater: - // AT = 1 TRUE - __ addi(AT, AT, -temp_value); - __ slt(AT, ZERO, AT); - __ bne(AT, ZERO, *op->label()); - break; - - - default: - //jerome_for_debug - Unimplemented(); - } - } else { Unimplemented(); } - } else { - Unimplemented(); - } - - __ delayed()->nop(); - - } else if(opr1->is_double_cpu()) { + __ delayed()->nop(); + + } else if(opr1->is_double_cpu()) { #ifdef OPT_RANGECHECK assert(!op->check(), "just check"); #endif - Register opr1_lo = opr1->as_register_lo(); - Register opr1_hi = opr1->as_register_hi(); - - if (opr2->is_double_cpu()) { - Register opr2_lo = opr2->as_register_lo(); - Register opr2_hi = opr2->as_register_hi(); - switch (condition) { - case lir_cond_equal: - { - Label L; - __ bne(opr1_lo, opr2_lo, L); - __ delayed()->nop(); - __ beq(opr1_hi, opr2_hi, *op->label()); - __ delayed()->nop(); - __ bind(L); - } - break; - - case lir_cond_notEqual: - __ bne(opr1_lo, opr2_lo, *op->label()); - __ delayed()->nop(); - __ bne(opr1_hi, opr2_hi, *op->label()); - __ delayed()->nop(); - break; - - case lir_cond_less: - { - Label L; - - // if hi less then jump - __ slt(AT, opr1_hi, opr2_hi); - __ bne(AT, ZERO, *op->label()); - __ delayed()->nop(); - - // if hi great then fail - __ bne(opr1_hi, opr2_hi, L); - __ delayed(); - - // now just comp lo as unsigned - __ sltu(AT, opr1_lo, opr2_lo); - __ bne(AT, ZERO, *op->label()); - __ delayed()->nop(); - - __ bind(L); - } - break; - - case lir_cond_lessEqual: - { - Label L; - - // if hi great then fail - __ slt(AT, opr2_hi, opr1_hi); - __ bne(AT, ZERO, L); - __ delayed()->nop(); - - // if hi less then jump - __ bne(opr2_hi, opr1_hi, *op->label()); - __ delayed(); - - // now just comp lo as unsigned - __ sltu(AT, opr2_lo, opr1_lo); - __ beq(AT, ZERO, *op->label()); - __ delayed()->nop(); - - __ bind(L); - } - break; - - case lir_cond_belowEqual: - { - Label L; - - // if hi great then fail - __ sltu(AT, opr2_hi, opr1_hi); - __ bne(AT, ZERO, L); - __ delayed()->nop(); - - // if hi less then jump - __ bne(opr2_hi, opr1_hi, *op->label()); - __ delayed(); - - // now just comp lo as unsigned - __ sltu(AT, opr2_lo, opr1_lo); - __ beq(AT, ZERO, *op->label()); - __ delayed()->nop(); - - __ bind(L); - } - break; - - case lir_cond_greaterEqual: - { - Label L; - - // if hi less then fail - __ slt(AT, opr1_hi, opr2_hi); - __ bne(AT, ZERO, L); - __ delayed()->nop(); - - // if hi great then jump - __ bne(opr2_hi, opr1_hi, *op->label()); - __ delayed(); - - // now just comp lo as unsigned - __ sltu(AT, opr1_lo, opr2_lo); - __ beq(AT, ZERO, *op->label()); - __ delayed()->nop(); - - __ bind(L); - } - break; - - case lir_cond_aboveEqual: - { - Label L; - - // if hi less then fail - __ sltu(AT, opr1_hi, opr2_hi); - __ bne(AT, ZERO, L); - __ delayed()->nop(); - - // if hi great then jump - __ bne(opr2_hi, opr1_hi, *op->label()); - __ delayed(); - - // now just comp lo as unsigned - __ sltu(AT, opr1_lo, opr2_lo); - __ beq(AT, ZERO, *op->label()); - __ delayed()->nop(); - - __ bind(L); - } - break; - - case lir_cond_greater: - { - Label L; - - // if hi great then jump - __ slt(AT, opr2_hi, opr1_hi); - __ bne(AT, ZERO, *op->label()); - __ delayed()->nop(); - - // if hi less then fail - __ bne(opr2_hi, opr1_hi, L); - __ delayed(); - - // now just comp lo as unsigned - __ sltu(AT, opr2_lo, opr1_lo); - __ bne(AT, ZERO, *op->label()); - __ delayed()->nop(); - - __ bind(L); - } - break; - - default: ShouldNotReachHere(); - } - - } else if(opr2->is_constant()) { - jlong lv = opr2->as_jlong(); - jint iv_lo = (jint)lv; - jint iv_hi = (jint)(lv>>32); - bool is_zero = (lv==0); - - switch (condition) { - case lir_cond_equal: - if (is_zero) { - __ orr(AT, opr1_lo, opr1_hi); - __ beq(AT, ZERO, *op->label()); - __ delayed()->nop(); - } else { - Label L; - __ move(T8, iv_lo); - __ bne(opr1_lo, T8, L); - __ delayed(); - __ move(T8, iv_hi); - __ beq(opr1_hi, T8, *op->label()); - __ delayed()->nop(); - __ bind(L); - } - break; - - case lir_cond_notEqual: - if (is_zero) { - __ orr(AT, opr1_lo, opr1_hi); - __ bne(AT, ZERO, *op->label()); - __ delayed()->nop(); - } else { - __ move(T8, iv_lo); - __ bne(opr1_lo, T8, *op->label()); - __ delayed(); - __ move(T8, iv_hi); - __ bne(opr1_hi, T8, *op->label()); - __ delayed()->nop(); - } - break; - - case lir_cond_less: - if (is_zero) { - __ bltz(opr1_hi, *op->label()); - __ delayed()->nop(); - } else { - Label L; - - // if hi less then jump - __ move(T8, iv_hi); - __ slt(AT, opr1_hi, T8); - __ bne(AT, ZERO, *op->label()); - __ delayed()->nop(); - - // if hi great then fail - __ bne(opr1_hi, T8, L); - __ delayed(); - - // now just comp lo as unsigned - if (Assembler::is_simm16(iv_lo)) { - __ sltiu(AT, opr1_lo, iv_lo); - } else { - __ move(T8, iv_lo); - __ sltu(AT, opr1_lo, T8); - } - __ bne(AT, ZERO, *op->label()); - __ delayed()->nop(); - - __ bind(L); - } - break; - - case lir_cond_lessEqual: - if (is_zero) { - __ bltz(opr1_hi, *op->label()); - __ delayed()->nop(); - __ orr(AT, opr1_hi, opr1_lo); - __ beq(AT, ZERO, *op->label()); - __ delayed(); - } else { - Label L; - - // if hi great then fail - __ move(T8, iv_hi); - __ slt(AT, T8, opr1_hi); - __ bne(AT, ZERO, L); - __ delayed()->nop(); - - // if hi less then jump - __ bne(T8, opr1_hi, *op->label()); - __ delayed(); - - // now just comp lo as unsigned - __ move(T8, iv_lo); - __ sltu(AT, T8, opr1_lo); - __ beq(AT, ZERO, *op->label()); - __ delayed()->nop(); - - __ bind(L); - } - break; - - case lir_cond_belowEqual: - if (is_zero) { - __ orr(AT, opr1_hi, opr1_lo); - __ beq(AT, ZERO, *op->label()); - __ delayed()->nop(); - } else { - Label L; - - // if hi great then fail - __ move(T8, iv_hi); - __ sltu(AT, T8, opr1_hi); - __ bne(AT, ZERO, L); - __ delayed()->nop(); - - // if hi less then jump - __ bne(T8, opr1_hi, *op->label()); - __ delayed(); - - // now just comp lo as unsigned - __ move(T8, iv_lo); - __ sltu(AT, T8, opr1_lo); - __ beq(AT, ZERO, *op->label()); - __ delayed()->nop(); - - __ bind(L); - } - break; - - case lir_cond_greaterEqual: - if (is_zero) { - __ bgez(opr1_hi, *op->label()); - __ delayed()->nop(); - } else { - Label L; - - // if hi less then fail - __ move(T8, iv_hi); - __ slt(AT, opr1_hi, T8); - __ bne(AT, ZERO, L); - __ delayed()->nop(); - - // if hi great then jump - __ bne(T8, opr1_hi, *op->label()); - __ delayed(); - - // now just comp lo as unsigned - if (Assembler::is_simm16(iv_lo)) { - __ sltiu(AT, opr1_lo, iv_lo); - } else { - __ move(T8, iv_lo); - __ sltu(AT, opr1_lo, T8); - } - __ beq(AT, ZERO, *op->label()); - __ delayed()->nop(); - - __ bind(L); - } - break; - - case lir_cond_aboveEqual: - if (is_zero) { - __ b(*op->label()); - __ delayed()->nop(); - } else { - Label L; - - // if hi less then fail - __ move(T8, iv_hi); - __ sltu(AT, opr1_hi, T8); - __ bne(AT, ZERO, L); - __ delayed()->nop(); - - // if hi great then jump - __ bne(T8, opr1_hi, *op->label()); - __ delayed(); - - // now just comp lo as unsigned - if (Assembler::is_simm16(iv_lo)) { - __ sltiu(AT, opr1_lo, iv_lo); - } else { - __ move(T8, iv_lo); - __ sltu(AT, opr1_lo, T8); - } - __ beq(AT, ZERO, *op->label()); - __ delayed()->nop(); - - __ bind(L); - } - break; - - case lir_cond_greater: - if (is_zero) { - Label L; - __ bgtz(opr1_hi, *op->label()); - __ delayed()->nop(); - __ bne(opr1_hi, ZERO, L); - __ delayed()->nop(); - __ bne(opr1_lo, ZERO, *op->label()); - __ delayed()->nop(); - __ bind(L); - } else { - Label L; - - // if hi great then jump - __ move(T8, iv_hi); - __ slt(AT, T8, opr1_hi); - __ bne(AT, ZERO, *op->label()); - __ delayed()->nop(); - - // if hi less then fail - __ bne(T8, opr1_hi, L); - __ delayed(); - - // now just comp lo as unsigned - __ move(T8, iv_lo); - __ sltu(AT, T8, opr1_lo); - __ bne(AT, ZERO, *op->label()); - __ delayed()->nop(); - - __ bind(L); - } - break; - - default: - ShouldNotReachHere(); - } - } else { - Unimplemented(); - } - } else if (opr1->is_single_fpu()) { + Register opr1_lo = opr1->as_register_lo(); + Register opr1_hi = opr1->as_register_hi(); + + if (opr2->is_double_cpu()) { + Register opr2_lo = opr2->as_register_lo(); + Register opr2_hi = opr2->as_register_hi(); + switch (condition) { + case lir_cond_equal: { + Label L; + __ bne(opr1_lo, opr2_lo, L); + __ delayed()->nop(); + __ beq(opr1_hi, opr2_hi, *op->label()); + __ delayed()->nop(); + __ bind(L); + } + break; + + case lir_cond_notEqual: + __ bne(opr1_lo, opr2_lo, *op->label()); + __ delayed()->nop(); + __ bne(opr1_hi, opr2_hi, *op->label()); + __ delayed()->nop(); + break; + + case lir_cond_less: { + Label L; + + // if hi less then jump + __ slt(AT, opr1_hi, opr2_hi); + __ bne(AT, ZERO, *op->label()); + __ delayed()->nop(); + + // if hi great then fail + __ bne(opr1_hi, opr2_hi, L); + __ delayed(); + + // now just comp lo as unsigned + __ sltu(AT, opr1_lo, opr2_lo); + __ bne(AT, ZERO, *op->label()); + __ delayed()->nop(); + + __ bind(L); + } + break; + + case lir_cond_lessEqual: { + Label L; + + // if hi great then fail + __ slt(AT, opr2_hi, opr1_hi); + __ bne(AT, ZERO, L); + __ delayed()->nop(); + + // if hi less then jump + __ bne(opr2_hi, opr1_hi, *op->label()); + __ delayed(); + + // now just comp lo as unsigned + __ sltu(AT, opr2_lo, opr1_lo); + __ beq(AT, ZERO, *op->label()); + __ delayed()->nop(); + + __ bind(L); + } + break; + + case lir_cond_belowEqual: { + Label L; + + // if hi great then fail + __ sltu(AT, opr2_hi, opr1_hi); + __ bne(AT, ZERO, L); + __ delayed()->nop(); + + // if hi less then jump + __ bne(opr2_hi, opr1_hi, *op->label()); + __ delayed(); + + // now just comp lo as unsigned + __ sltu(AT, opr2_lo, opr1_lo); + __ beq(AT, ZERO, *op->label()); + __ delayed()->nop(); + + __ bind(L); + } + break; + + case lir_cond_greaterEqual: { + Label L; + + // if hi less then fail + __ slt(AT, opr1_hi, opr2_hi); + __ bne(AT, ZERO, L); + __ delayed()->nop(); + + // if hi great then jump + __ bne(opr2_hi, opr1_hi, *op->label()); + __ delayed(); + + // now just comp lo as unsigned + __ sltu(AT, opr1_lo, opr2_lo); + __ beq(AT, ZERO, *op->label()); + __ delayed()->nop(); + + __ bind(L); + } + break; + + case lir_cond_aboveEqual: { + Label L; + + // if hi less then fail + __ sltu(AT, opr1_hi, opr2_hi); + __ bne(AT, ZERO, L); + __ delayed()->nop(); + + // if hi great then jump + __ bne(opr2_hi, opr1_hi, *op->label()); + __ delayed(); + + // now just comp lo as unsigned + __ sltu(AT, opr1_lo, opr2_lo); + __ beq(AT, ZERO, *op->label()); + __ delayed()->nop(); + + __ bind(L); + } + break; + + case lir_cond_greater: { + Label L; + + // if hi great then jump + __ slt(AT, opr2_hi, opr1_hi); + __ bne(AT, ZERO, *op->label()); + __ delayed()->nop(); + + // if hi less then fail + __ bne(opr2_hi, opr1_hi, L); + __ delayed(); + + // now just comp lo as unsigned + __ sltu(AT, opr2_lo, opr1_lo); + __ bne(AT, ZERO, *op->label()); + __ delayed()->nop(); + + __ bind(L); + } + break; + + default: ShouldNotReachHere(); + } + + } else if(opr2->is_constant()) { + jlong lv = opr2->as_jlong(); + jint iv_lo = (jint)lv; + jint iv_hi = (jint)(lv>>32); + bool is_zero = (lv==0); + + switch (condition) { + case lir_cond_equal: + if (is_zero) { + __ orr(AT, opr1_lo, opr1_hi); + __ beq(AT, ZERO, *op->label()); + __ delayed()->nop(); + } else { + Label L; + __ move(T8, iv_lo); + __ bne(opr1_lo, T8, L); + __ delayed(); + __ move(T8, iv_hi); + __ beq(opr1_hi, T8, *op->label()); + __ delayed()->nop(); + __ bind(L); + } + break; + + case lir_cond_notEqual: + if (is_zero) { + __ orr(AT, opr1_lo, opr1_hi); + __ bne(AT, ZERO, *op->label()); + __ delayed()->nop(); + } else { + __ move(T8, iv_lo); + __ bne(opr1_lo, T8, *op->label()); + __ delayed(); + __ move(T8, iv_hi); + __ bne(opr1_hi, T8, *op->label()); + __ delayed()->nop(); + } + break; + + case lir_cond_less: + if (is_zero) { + __ bltz(opr1_hi, *op->label()); + __ delayed()->nop(); + } else { + Label L; + + // if hi less then jump + __ move(T8, iv_hi); + __ slt(AT, opr1_hi, T8); + __ bne(AT, ZERO, *op->label()); + __ delayed()->nop(); + + // if hi great then fail + __ bne(opr1_hi, T8, L); + __ delayed(); + + // now just comp lo as unsigned + if (Assembler::is_simm16(iv_lo)) { + __ sltiu(AT, opr1_lo, iv_lo); + } else { + __ move(T8, iv_lo); + __ sltu(AT, opr1_lo, T8); + } + __ bne(AT, ZERO, *op->label()); + __ delayed()->nop(); + + __ bind(L); + } + break; + + case lir_cond_lessEqual: + if (is_zero) { + __ bltz(opr1_hi, *op->label()); + __ delayed()->nop(); + __ orr(AT, opr1_hi, opr1_lo); + __ beq(AT, ZERO, *op->label()); + __ delayed(); + } else { + Label L; + + // if hi great then fail + __ move(T8, iv_hi); + __ slt(AT, T8, opr1_hi); + __ bne(AT, ZERO, L); + __ delayed()->nop(); + + // if hi less then jump + __ bne(T8, opr1_hi, *op->label()); + __ delayed(); + + // now just comp lo as unsigned + __ move(T8, iv_lo); + __ sltu(AT, T8, opr1_lo); + __ beq(AT, ZERO, *op->label()); + __ delayed()->nop(); + + __ bind(L); + } + break; + + case lir_cond_belowEqual: + if (is_zero) { + __ orr(AT, opr1_hi, opr1_lo); + __ beq(AT, ZERO, *op->label()); + __ delayed()->nop(); + } else { + Label L; + + // if hi great then fail + __ move(T8, iv_hi); + __ sltu(AT, T8, opr1_hi); + __ bne(AT, ZERO, L); + __ delayed()->nop(); + + // if hi less then jump + __ bne(T8, opr1_hi, *op->label()); + __ delayed(); + + // now just comp lo as unsigned + __ move(T8, iv_lo); + __ sltu(AT, T8, opr1_lo); + __ beq(AT, ZERO, *op->label()); + __ delayed()->nop(); + + __ bind(L); + } + break; + + case lir_cond_greaterEqual: + if (is_zero) { + __ bgez(opr1_hi, *op->label()); + __ delayed()->nop(); + } else { + Label L; + + // if hi less then fail + __ move(T8, iv_hi); + __ slt(AT, opr1_hi, T8); + __ bne(AT, ZERO, L); + __ delayed()->nop(); + + // if hi great then jump + __ bne(T8, opr1_hi, *op->label()); + __ delayed(); + + // now just comp lo as unsigned + if (Assembler::is_simm16(iv_lo)) { + __ sltiu(AT, opr1_lo, iv_lo); + } else { + __ move(T8, iv_lo); + __ sltu(AT, opr1_lo, T8); + } + __ beq(AT, ZERO, *op->label()); + __ delayed()->nop(); + + __ bind(L); + } + break; + + case lir_cond_aboveEqual: + if (is_zero) { + __ b(*op->label()); + __ delayed()->nop(); + } else { + Label L; + + // if hi less then fail + __ move(T8, iv_hi); + __ sltu(AT, opr1_hi, T8); + __ bne(AT, ZERO, L); + __ delayed()->nop(); + + // if hi great then jump + __ bne(T8, opr1_hi, *op->label()); + __ delayed(); + + // now just comp lo as unsigned + if (Assembler::is_simm16(iv_lo)) { + __ sltiu(AT, opr1_lo, iv_lo); + } else { + __ move(T8, iv_lo); + __ sltu(AT, opr1_lo, T8); + } + __ beq(AT, ZERO, *op->label()); + __ delayed()->nop(); + + __ bind(L); + } + break; + + case lir_cond_greater: + if (is_zero) { + Label L; + __ bgtz(opr1_hi, *op->label()); + __ delayed()->nop(); + __ bne(opr1_hi, ZERO, L); + __ delayed()->nop(); + __ bne(opr1_lo, ZERO, *op->label()); + __ delayed()->nop(); + __ bind(L); + } else { + Label L; + + // if hi great then jump + __ move(T8, iv_hi); + __ slt(AT, T8, opr1_hi); + __ bne(AT, ZERO, *op->label()); + __ delayed()->nop(); + + // if hi less then fail + __ bne(T8, opr1_hi, L); + __ delayed(); + + // now just comp lo as unsigned + __ move(T8, iv_lo); + __ sltu(AT, T8, opr1_lo); + __ bne(AT, ZERO, *op->label()); + __ delayed()->nop(); + + __ bind(L); + } + break; + + default: + ShouldNotReachHere(); + } + } else { + Unimplemented(); + } + } else if (opr1->is_single_fpu()) { #ifdef OPT_RANGECHECK assert(!op->check(), "just check"); #endif - assert(opr2->is_single_fpu(), "change the code"); - - FloatRegister reg_op1 = opr1->as_float_reg(); - FloatRegister reg_op2 = opr2->as_float_reg(); - // bool un_ls - bool un_jump = (op->ublock()->label()==op->label()); - - Label& L = *op->label(); - - switch (condition) { - case lir_cond_equal: - if (un_jump) - __ c_ueq_s(reg_op1, reg_op2); - else - __ c_eq_s(reg_op1, reg_op2); - __ bc1t(L); - - break; - - case lir_cond_notEqual: - if (un_jump) - __ c_eq_s(reg_op1, reg_op2); - else - __ c_ueq_s(reg_op1, reg_op2); - __ bc1f(L); - - break; - - case lir_cond_less: - if (un_jump) - __ c_ult_s(reg_op1, reg_op2); - else - __ c_olt_s(reg_op1, reg_op2); - __ bc1t(L); - - break; - - case lir_cond_lessEqual: - case lir_cond_belowEqual: - if (un_jump) - __ c_ule_s(reg_op1, reg_op2); - else - __ c_ole_s(reg_op1, reg_op2); - __ bc1t(L); - - break; - - case lir_cond_greaterEqual: - case lir_cond_aboveEqual: - if (un_jump) - __ c_olt_s(reg_op1, reg_op2); - else - __ c_ult_s(reg_op1, reg_op2); - __ bc1f(L); - - break; - - case lir_cond_greater: - if (un_jump) - __ c_ole_s(reg_op1, reg_op2); - else - __ c_ule_s(reg_op1, reg_op2); - __ bc1f(L); - - break; - - default: - ShouldNotReachHere(); - } - __ delayed()->nop(); - } else if (opr1->is_double_fpu()) { + assert(opr2->is_single_fpu(), "change the code"); + + FloatRegister reg_op1 = opr1->as_float_reg(); + FloatRegister reg_op2 = opr2->as_float_reg(); + // bool un_ls + bool un_jump = (op->ublock()->label()==op->label()); + + Label& L = *op->label(); + + switch (condition) { + case lir_cond_equal: + if (un_jump) + __ c_ueq_s(reg_op1, reg_op2); + else + __ c_eq_s(reg_op1, reg_op2); + __ bc1t(L); + + break; + + case lir_cond_notEqual: + if (un_jump) + __ c_eq_s(reg_op1, reg_op2); + else + __ c_ueq_s(reg_op1, reg_op2); + __ bc1f(L); + + break; + + case lir_cond_less: + if (un_jump) + __ c_ult_s(reg_op1, reg_op2); + else + __ c_olt_s(reg_op1, reg_op2); + __ bc1t(L); + + break; + + case lir_cond_lessEqual: + case lir_cond_belowEqual: + if (un_jump) + __ c_ule_s(reg_op1, reg_op2); + else + __ c_ole_s(reg_op1, reg_op2); + __ bc1t(L); + + break; + + case lir_cond_greaterEqual: + case lir_cond_aboveEqual: + if (un_jump) + __ c_olt_s(reg_op1, reg_op2); + else + __ c_ult_s(reg_op1, reg_op2); + __ bc1f(L); + + break; + + case lir_cond_greater: + if (un_jump) + __ c_ole_s(reg_op1, reg_op2); + else + __ c_ule_s(reg_op1, reg_op2); + __ bc1f(L); + + break; + + default: + ShouldNotReachHere(); + } + __ delayed()->nop(); + } else if (opr1->is_double_fpu()) { #ifdef OPT_RANGECHECK - assert(!op->check(), "just check"); + assert(!op->check(), "just check"); #endif - assert(opr2->is_double_fpu(), "change the code"); - - FloatRegister reg_op1 = opr1->as_double_reg(); - FloatRegister reg_op2 = opr2->as_double_reg(); - bool un_jump = (op->ublock()->label()==op->label()); - Label& L = *op->label(); - - switch (condition) { - case lir_cond_equal: - if (un_jump) - __ c_ueq_d(reg_op1, reg_op2); - else - __ c_eq_d(reg_op1, reg_op2); - __ bc1t(L); - - break; - - case lir_cond_notEqual: - if (un_jump) - __ c_eq_d(reg_op1, reg_op2); - else - __ c_ueq_d(reg_op1, reg_op2); - __ bc1f(L); - - break; - - case lir_cond_less: - if (un_jump) - __ c_ult_d(reg_op1, reg_op2); - else - __ c_olt_d(reg_op1, reg_op2); - __ bc1t(L); - - break; - - case lir_cond_lessEqual: - case lir_cond_belowEqual: - if (un_jump) - __ c_ule_d(reg_op1, reg_op2); - else - __ c_ole_d(reg_op1, reg_op2); - __ bc1t(L); - - break; - - case lir_cond_greaterEqual: - case lir_cond_aboveEqual: - if (un_jump) - __ c_olt_d(reg_op1, reg_op2); - else - __ c_ult_d(reg_op1, reg_op2); - __ bc1f(L); - - break; - - case lir_cond_greater: - if (un_jump) - __ c_ole_d(reg_op1, reg_op2); - else - __ c_ule_d(reg_op1, reg_op2); - __ bc1f(L); - - break; - - default: - ShouldNotReachHere(); - } - - __ delayed()->nop(); - } else { + assert(opr2->is_double_fpu(), "change the code"); + + FloatRegister reg_op1 = opr1->as_double_reg(); + FloatRegister reg_op2 = opr2->as_double_reg(); + bool un_jump = (op->ublock()->label()==op->label()); + Label& L = *op->label(); + + switch (condition) { + case lir_cond_equal: + if (un_jump) + __ c_ueq_d(reg_op1, reg_op2); + else + __ c_eq_d(reg_op1, reg_op2); + __ bc1t(L); + + break; + + case lir_cond_notEqual: + if (un_jump) + __ c_eq_d(reg_op1, reg_op2); + else + __ c_ueq_d(reg_op1, reg_op2); + __ bc1f(L); + + break; + + case lir_cond_less: + if (un_jump) + __ c_ult_d(reg_op1, reg_op2); + else + __ c_olt_d(reg_op1, reg_op2); + __ bc1t(L); + + break; + + case lir_cond_lessEqual: + case lir_cond_belowEqual: + if (un_jump) + __ c_ule_d(reg_op1, reg_op2); + else + __ c_ole_d(reg_op1, reg_op2); + __ bc1t(L); + + break; + + case lir_cond_greaterEqual: + case lir_cond_aboveEqual: + if (un_jump) + __ c_olt_d(reg_op1, reg_op2); + else + __ c_ult_d(reg_op1, reg_op2); + __ bc1f(L); + + break; + + case lir_cond_greater: + if (un_jump) + __ c_ole_d(reg_op1, reg_op2); + else + __ c_ule_d(reg_op1, reg_op2); + __ bc1f(L); + + break; + + default: + ShouldNotReachHere(); + } + __ delayed()->nop(); + } else { Unimplemented(); } } @@ -2226,7 +2145,6 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { LIR_Opr value = op->in_opr(); LIR_Opr src = op->in_opr(); - // RInfo dst = op->result_opr()->rinfo(); LIR_Opr dest = op->result_opr(); Bytecodes::Code code = op->bytecode(); @@ -2235,191 +2153,180 @@ move_regs(src->as_register(), dest->as_register_lo()); __ sra (dest->as_register_hi(), dest->as_register_lo(), 31); break; - case Bytecodes::_l2i: move_regs (src->as_register_lo(), dest->as_register()); break; + case Bytecodes::_i2b: - move_regs (src->as_register(), dest->as_register()); + move_regs (src->as_register(), dest->as_register()); __ sign_extend_byte(dest->as_register()); break; + case Bytecodes::_i2c: __ andi(dest->as_register(), src->as_register(), 0xFFFF); break; + case Bytecodes::_i2s: - move_regs (src->as_register(), dest->as_register()); + move_regs (src->as_register(), dest->as_register()); __ sign_extend_short(dest->as_register()); break; - case Bytecodes::_f2d: - __ cvt_d_s(dest->as_double_reg(), src->as_float_reg()); + + case Bytecodes::_f2d: + __ cvt_d_s(dest->as_double_reg(), src->as_float_reg()); break; + case Bytecodes::_d2f: - __ cvt_s_d(dest->as_float_reg(), src->as_double_reg()); - break; - case Bytecodes::_i2f: - { - FloatRegister df = dest->as_float_reg(); - if(src->is_single_cpu()) { - __ mtc1(src->as_register(), df); - __ cvt_s_w(df, df); - } else if (src->is_stack()) { - Address src_addr = src->is_single_stack() - ? frame_map()->address_for_slot(src->single_stack_ix()) - : frame_map()->address_for_slot(src->double_stack_ix()); - __ lw(AT, src_addr); - __ mtc1(AT, df); - __ cvt_s_w(df, df); - } else { - Unimplemented(); - } - - - } - break; - case Bytecodes::_i2d: - { - FloatRegister dd = dest->as_double_reg(); - if (src->is_single_cpu()) { - __ mtc1(src->as_register(), dd); - __ cvt_d_w(dd, dd); - } else if (src->is_stack()) { - Address src_addr = src->is_single_stack() - ? frame_map()->address_for_slot(value->single_stack_ix()) - : frame_map()->address_for_slot(value->double_stack_ix()); - __ lw(AT, src_addr); - __ mtc1(AT, dd); - __ cvt_d_w(dd, dd); - } else { - Unimplemented(); - } - } - break; - case Bytecodes::_f2i: - { - FloatRegister fval = src->as_float_reg(); - Register dreg = dest->as_register(); - - Label L; - __ c_un_s(fval, fval); //NaN? - __ bc1t(L); - __ delayed(); - __ move(dreg, ZERO); - - __ trunc_w_s(F30, fval); - __ mfc1(dreg, F30); - __ bind(L); - } - break; - case Bytecodes::_d2i: - { - FloatRegister dval = src->as_double_reg(); - Register dreg = dest->as_register(); - - Label L; - __ c_un_d(dval, dval); //NaN? - __ bc1t(L); - __ delayed(); - __ move(dreg, ZERO); - - __ trunc_w_d(F30, dval); - __ mfc1(dreg, F30); - __ bind(L); - } - break; - case Bytecodes::_l2f: - { - FloatRegister ldf = dest->as_float_reg(); - if (src->is_double_cpu()) { - __ mtc1(src->as_register_lo(), ldf); - __ mtc1(src->as_register_hi(), ldf + 1); - __ cvt_s_l(ldf, ldf); - } else if (src->is_double_stack()) { - Address src_addr=frame_map()->address_for_slot(value->double_stack_ix()); - __ lw(AT, src_addr); - __ mtc1(AT, ldf); - __ lw(AT, src_addr.base(), src_addr.disp() + 4); - __ mtc1(AT, ldf + 1); - __ cvt_s_l(ldf, ldf); - } else { - Unimplemented(); - } - } - break; - case Bytecodes::_l2d: - { - FloatRegister ldd = dest->as_double_reg(); - if (src->is_double_cpu()) { - __ mtc1(src->as_register_lo(), ldd); - __ mtc1(src->as_register_hi(), ldd + 1); - __ cvt_d_l(ldd, ldd); - } else if (src->is_double_stack()) { - Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); - __ lw(AT, src_addr); - __ mtc1(AT, ldd); - __ lw(AT, src_addr.base(), src_addr.disp() + 4); - __ mtc1(AT, ldd + 1); - __ cvt_d_l(ldd, ldd); - } else { - Unimplemented(); - } - } - break; - + __ cvt_s_d(dest->as_float_reg(), src->as_double_reg()); + break; + case Bytecodes::_i2f: { + FloatRegister df = dest->as_float_reg(); + if(src->is_single_cpu()) { + __ mtc1(src->as_register(), df); + __ cvt_s_w(df, df); + } else if (src->is_stack()) { + Address src_addr = src->is_single_stack() + ? frame_map()->address_for_slot(src->single_stack_ix()) + : frame_map()->address_for_slot(src->double_stack_ix()); + __ lw(AT, src_addr); + __ mtc1(AT, df); + __ cvt_s_w(df, df); + } else { + Unimplemented(); + } + break; + } + case Bytecodes::_i2d: { + FloatRegister dd = dest->as_double_reg(); + if (src->is_single_cpu()) { + __ mtc1(src->as_register(), dd); + __ cvt_d_w(dd, dd); + } else if (src->is_stack()) { + Address src_addr = src->is_single_stack() + ? frame_map()->address_for_slot(value->single_stack_ix()) + : frame_map()->address_for_slot(value->double_stack_ix()); + __ lw(AT, src_addr); + __ mtc1(AT, dd); + __ cvt_d_w(dd, dd); + } else { + Unimplemented(); + } + break; + } + case Bytecodes::_f2i: { + FloatRegister fval = src->as_float_reg(); + Register dreg = dest->as_register(); + + Label L; + __ c_un_s(fval, fval); //NaN? + __ bc1t(L); + __ delayed(); + __ move(dreg, ZERO); + + __ trunc_w_s(F30, fval); + __ mfc1(dreg, F30); + __ bind(L); + break; + } + case Bytecodes::_d2i: { + FloatRegister dval = src->as_double_reg(); + Register dreg = dest->as_register(); + + Label L; + __ c_un_d(dval, dval); //NaN? + __ bc1t(L); + __ delayed(); + __ move(dreg, ZERO); - case Bytecodes::_f2l: - { - FloatRegister fval = src->as_float_reg(); - Register dlo = dest->as_register_lo(); - Register dhi = dest->as_register_hi(); - - Label L; - __ move(dhi, ZERO); - __ c_un_s(fval, fval); //NaN? - __ bc1t(L); - __ delayed(); - __ move(dlo, ZERO); - - __ trunc_l_s(F30, fval); - __ mfc1(dlo, F30); - __ mfc1(dhi, F31); - __ bind(L); - } - break; - case Bytecodes::_d2l: - { - FloatRegister dval = src->as_double_reg(); - Register dlo = dest->as_register_lo(); - Register dhi = dest->as_register_hi(); - - Label L; - __ move(dhi, ZERO); - __ c_un_d(dval, dval); //NaN? - __ bc1t(L); - __ delayed(); - __ move(dlo, ZERO); - - __ trunc_l_d(F30, dval); - __ mfc1(dlo, F30); - __ mfc1(dhi, F31); - __ bind(L); - } - break; - - - default: ShouldNotReachHere(); + __ trunc_w_d(F30, dval); + __ mfc1(dreg, F30); + __ bind(L); + break; + } + case Bytecodes::_l2f: { + FloatRegister ldf = dest->as_float_reg(); + if (src->is_double_cpu()) { + __ mtc1(src->as_register_lo(), ldf); + __ mtc1(src->as_register_hi(), ldf + 1); + __ cvt_s_l(ldf, ldf); + } else if (src->is_double_stack()) { + Address src_addr=frame_map()->address_for_slot(value->double_stack_ix()); + __ lw(AT, src_addr); + __ mtc1(AT, ldf); + __ lw(AT, src_addr.base(), src_addr.disp() + 4); + __ mtc1(AT, ldf + 1); + __ cvt_s_l(ldf, ldf); + } else { + Unimplemented(); + } + break; + } + case Bytecodes::_l2d: { + FloatRegister ldd = dest->as_double_reg(); + if (src->is_double_cpu()) { + __ mtc1(src->as_register_lo(), ldd); + __ mtc1(src->as_register_hi(), ldd + 1); + __ cvt_d_l(ldd, ldd); + } else if (src->is_double_stack()) { + Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); + __ lw(AT, src_addr); + __ mtc1(AT, ldd); + __ lw(AT, src_addr.base(), src_addr.disp() + 4); + __ mtc1(AT, ldd + 1); + __ cvt_d_l(ldd, ldd); + } else { + Unimplemented(); + } + break; + } + + case Bytecodes::_f2l: { + FloatRegister fval = src->as_float_reg(); + Register dlo = dest->as_register_lo(); + Register dhi = dest->as_register_hi(); + + Label L; + __ move(dhi, ZERO); + __ c_un_s(fval, fval); //NaN? + __ bc1t(L); + __ delayed(); + __ move(dlo, ZERO); + + __ trunc_l_s(F30, fval); + __ mfc1(dlo, F30); + __ mfc1(dhi, F31); + __ bind(L); + break; + } + case Bytecodes::_d2l: { + FloatRegister dval = src->as_double_reg(); + Register dlo = dest->as_register_lo(); + Register dhi = dest->as_register_hi(); + + Label L; + __ move(dhi, ZERO); + __ c_un_d(dval, dval); //NaN? + __ bc1t(L); + __ delayed(); + __ move(dlo, ZERO); + + __ trunc_l_d(F30, dval); + __ mfc1(dlo, F30); + __ mfc1(dhi, F31); + __ bind(L); + break; + } + + default: ShouldNotReachHere(); } } void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { if (op->init_check()) { - // __ cmpl(Address(op->klass()->as_register(), - // instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), - // instanceKlass::fully_initialized); add_debug_info_for_null_check_here(op->stub()->info()); - // __ jcc(Assembler::notEqual, *op->stub()->entry()); - __ lw(AT,Address(op->klass()->as_register(),instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc))); - __ addi(AT, AT, -instanceKlass::fully_initialized); + __ lw(AT,Address(op->klass()->as_register(), + instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc))); + __ addi(AT, AT, -instanceKlass::fully_initialized); __ bne(AT,ZERO,*op->stub()->entry()); __ delayed()->nop(); } @@ -2436,8 +2343,6 @@ } void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { - - if (UseSlowPath || (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { @@ -2483,7 +2388,7 @@ __ lw(k_RInfo, k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)); // get super_check_offset - //for SIGBUS, FIXME, Jerome + //for SIGBUS, FIXME, Jerome __ nop(); __ nop(); __ lw(T9, k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes()); @@ -2604,16 +2509,12 @@ __ delayed()->nop(); __ bind(profile_done); } else { - // __ jcc(Assembler::equal, done); __ beq(obj, ZERO, done); __ delayed()->nop(); } __ verify_oop(obj); - // __ beq(obj, ZERO, done); - // __ delayed()->nop(); - if (op->fast_check()) { // get object class // not a safepoint as obj null check happens earlier @@ -2672,7 +2573,6 @@ // assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); // super_check_offset - // __ lw(T9, k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes()); __ lw(Rtmp1, k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes()); // See if we get an immediate positive hit __ add(AT, klass_RInfo, Rtmp1); @@ -2731,8 +2631,8 @@ Label one; if (obj == k_RInfo) { - k_RInfo = klass_RInfo; - klass_RInfo = obj; + k_RInfo = klass_RInfo; + klass_RInfo = obj; } // patching may screw with our temporaries on sparc, @@ -2740,7 +2640,6 @@ if (!k->is_loaded()) { jobject2reg_with_patching(k_RInfo, op->info_for_patch()); } else { - // ciObject2reg(k, k_RInfo); jobject2reg(k->encoding(), k_RInfo); } @@ -2761,7 +2660,7 @@ // not a safepoint as obj null check happens earlier __ lw(klass_RInfo, obj, oopDesc::klass_offset_in_bytes()); if (k->is_loaded()) { - // assert(dst != obj, "need different registers so we have a temporary"); + // assert(dst != obj, "need different registers so we have a temporary"); // See if we get an immediate positive hit __ lw(AT, klass_RInfo, k->super_check_offset()); @@ -2770,10 +2669,9 @@ if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() == k->super_check_offset()) { // check for self //ciObject2reg(k, AT); - jobject2reg(k->encoding(), AT); - - __ beq(klass_RInfo, k_RInfo, one); - __ delayed()->nop(); + jobject2reg(k->encoding(), AT); + __ beq(klass_RInfo, k_RInfo, one); + __ delayed()->nop(); // array __ lw(T8, klass_RInfo, sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()); @@ -2884,13 +2782,8 @@ } void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { - } - - - - - -//void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) { +} + void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info,bool pop_fpu_stack) { assert(info == NULL || ((code == lir_rem || code == lir_div || code == lir_sub) && right->is_double_cpu()), "info is only for ldiv/lrem"); if (left->is_double_cpu()) { @@ -3533,9 +3426,6 @@ } */ __ relocate(static_stub_Relocation::spec(call_pc)); - //__ movl(ebx, (jobject)NULL); - //__ lw(T7, (jobject)NULL); -// __ move(T7, ZERO); jobject o=NULL; int oop_index = __ oop_recorder()->allocate_index((jobject)o); RelocationHolder rspec = oop_Relocation::spec(oop_index); @@ -3545,16 +3435,12 @@ // must be set to -1 at code generation time // assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); - //__ jmp((address)-1, relocInfo::runtime_call_type); - //jerome_for_debug - __ lui(AT, Assembler::split_high((int)-1)); + __ lui(AT, Assembler::split_high((int)-1)); __ addiu(AT, AT, Assembler::split_low((int)-1)); - __ jr(AT); + __ jr(AT); __ delayed()->nop(); assert(__ offset() - start <= call_stub_size, "stub too big") __ end_a_stub(); - - } @@ -3928,11 +3814,11 @@ __ andr(SP, SP, AT); // push argument __ sw(length, SP, 4 * wordSize); - /*if (dst_pos != A3)*/ __ move(A3, dst_pos); - /*if (dst != A2)*/ __ move(A2, dst); - /*if (src_pos != A1)*/ __ move(A1, src_pos); - /*if (src != A0)*/ __ move(A0, src); - // make call + __ move(A3, dst_pos); + __ move(A2, dst); + __ move(A1, src_pos); + __ move(A0, src); + // make call address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); __ call(entry, relocInfo::runtime_call_type); __ delayed()->nop(); @@ -3942,20 +3828,19 @@ #endif __ lw(SP, java_thread, in_bytes(JavaThread::last_Java_sp_offset())); -// __ beq(V0, ZERO, done); __ beq(V0, ZERO, *stub->continuation()); __ delayed()->nop(); - __ super_pop(length); - __ super_pop(dst_pos); - __ super_pop(src_pos); - __ super_pop(dst); - __ super_pop(src); - - - __ b(*stub->entry()); - __ delayed()->nop(); - __ bind(*stub->continuation()); - return; + __ super_pop(length); + __ super_pop(dst_pos); + __ super_pop(src_pos); + __ super_pop(dst); + __ super_pop(src); + + + __ b(*stub->entry()); + __ delayed()->nop(); + __ bind(*stub->continuation()); + return; } assert(default_type != NULL && default_type->is_array_klass() @@ -4061,8 +3946,8 @@ if (length!=A2) __ move(A2, length); } - __ move(A3, src_pos ); - assert_different_registers(A0, dst_pos, dst); + __ move(A3, src_pos ); + assert_different_registers(A0, dst_pos, dst); __ sll(AT, AT, shift_amount); __ addi(AT, AT, arrayOopDesc::base_offset_in_bytes(basic_type)); __ add(A1, dst, AT); @@ -4078,11 +3963,11 @@ } else { __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 3); } - __ super_pop(length); - __ super_pop(dst_pos); - __ super_pop(src_pos); - __ super_pop(dst); - __ super_pop(src); + __ super_pop(length); + __ super_pop(dst_pos); + __ super_pop(src_pos); + __ super_pop(dst); + __ super_pop(src); __ bind(*stub->continuation()); } @@ -4240,12 +4125,12 @@ } void LIR_Assembler::emit_delay(LIR_OpDelay*) { - Unimplemented(); + Unimplemented(); } void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { - __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); + __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); } void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { @@ -4256,6 +4141,7 @@ Register hi = left->as_register_hi(); Register dlo = dest->as_register_lo(); Register dhi = dest->as_register_hi(); + assert(dlo != hi, "register checks"); __ nor(dlo, ZERO, lo); __ addiu(dlo, dlo, 1); __ sltiu(AT, dlo, 1); @@ -4291,7 +4177,6 @@ __ relocate(rspec); __ lui(reg, Assembler::split_high((int)o)); __ addiu(reg, reg, Assembler::split_low((int)o)); - // __ move(reg, ZERO); } else { int oop_index = __ oop_recorder()->find_index(o); RelocationHolder rspec = oop_Relocation::spec(oop_index); @@ -4303,11 +4188,11 @@ void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { assert(!tmp->is_valid(), "don't need temporary"); - __ call(dest, relocInfo::runtime_call_type); - __ delayed()->nop(); - if (info != NULL) { - add_call_info_here(info); - } + __ call(dest, relocInfo::runtime_call_type); + __ delayed()->nop(); + if (info != NULL) { + add_call_info_here(info); + } } /* by yyq 7/22/2009 @@ -4323,32 +4208,30 @@ if(src->is_register() && dest->is_address()) { if(src->is_double_cpu()) { - __ sw(src->as_register_lo(), as_Address(dest->as_address_ptr())); - __ sw(src->as_register_hi(), as_Address(dest->as_address_ptr()).base(), + __ sw(src->as_register_lo(), as_Address(dest->as_address_ptr())); + __ sw(src->as_register_hi(), as_Address(dest->as_address_ptr()).base(), as_Address(dest->as_address_ptr()).disp() +4); } else if (src->is_double_fpu()) { - __ swc1(src->as_fpu_lo(), as_Address(dest->as_address_ptr())); - __ swc1(src->as_fpu_hi(), as_Address(dest->as_address_ptr()).base(), + __ swc1(src->as_fpu_lo(), as_Address(dest->as_address_ptr())); + __ swc1(src->as_fpu_hi(), as_Address(dest->as_address_ptr()).base(), as_Address(dest->as_address_ptr()).disp() +4); - } else { - ShouldNotReachHere(); + ShouldNotReachHere(); } } else if (src->is_address() && dest->is_register()){ if(dest->is_double_cpu()) { - __ lw(dest->as_register_lo(), as_Address(src->as_address_ptr())); - __ lw(dest->as_register_hi(), as_Address(src->as_address_ptr()).base(), + __ lw(dest->as_register_lo(), as_Address(src->as_address_ptr())); + __ lw(dest->as_register_hi(), as_Address(src->as_address_ptr()).base(), as_Address(src->as_address_ptr()).disp() +4); } else if (dest->is_double_fpu()) { - __ lwc1(dest->as_fpu_lo(), as_Address(src->as_address_ptr())); - __ lwc1(dest->as_fpu_hi(), as_Address(src->as_address_ptr()).base(), + __ lwc1(dest->as_fpu_lo(), as_Address(src->as_address_ptr())); + __ lwc1(dest->as_fpu_hi(), as_Address(src->as_address_ptr()).base(), as_Address(src->as_address_ptr()).disp() +4); } else { - ShouldNotReachHere(); + ShouldNotReachHere(); } - } else { - ShouldNotReachHere(); + ShouldNotReachHere(); } }
--- a/hotspot/src/share/vm/oops/oop.inline.hpp Sat Oct 23 21:08:56 2010 +0000 +++ b/hotspot/src/share/vm/oops/oop.inline.hpp Sun Oct 24 14:32:13 2010 +0000 @@ -341,6 +341,10 @@ inline void oopDesc::release_double_field_put(int offset, jdouble contents) { OrderAccess::release_store(double_field_addr(offset), contents); } inline int oopDesc::size_given_klass(Klass* klass) { + if (klass == NULL) { + tty->print_cr("null klass %p", __builtin_return_address(0)); + } + int lh = klass->layout_helper(); int s = lh >> LogHeapWordSize; // deliver size scaled by wordSize
--- a/hotspot/src/share/vm/runtime/reflection.cpp Sat Oct 23 21:08:56 2010 +0000 +++ b/hotspot/src/share/vm/runtime/reflection.cpp Sun Oct 24 14:32:13 2010 +0000 @@ -862,6 +862,7 @@ // resolve based on the receiver if (instanceKlass::cast(reflected_method->method_holder())->is_interface()) { // resolve interface call + tty->print_cr("resolve interface call"); if (ReflectionWrapResolutionErrors) { // new default: 6531596 // Match resolution errors with those thrown due to reflection inlining @@ -881,6 +882,7 @@ } } else { // if the method can be overridden, we resolve using the vtable index. + tty->print_cr("resolve not interface call"); int index = reflected_method->vtable_index(); method = reflected_method; if (index != methodOopDesc::nonvirtual_vtable_index) { @@ -949,7 +951,6 @@ if (ptypes->length() != args_len) { THROW_MSG_0(vmSymbols::java_lang_IllegalArgumentException(), "wrong number of arguments"); } - // Create object to contain parameters for the JavaCall JavaCallArguments java_args(method->size_of_parameters()); @@ -1000,6 +1001,7 @@ if (HAS_PENDING_EXCEPTION) { // Method threw an exception; wrap it in an InvocationTargetException + method->print_on(tty); oop target_exception = PENDING_EXCEPTION; CLEAR_PENDING_EXCEPTION; JavaCallArguments args(Handle(THREAD, target_exception));