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changeset 12476:6c9ce2c9e650

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Merge
author kvn
date Wed, 21 Dec 2016 17:27:25 +0000
parents a3bd5804b4be (current diff) a04e67d8ad3c (diff)
children e4d0894a53a3 b552b596203f
files
diffstat 1 files changed, 3 insertions(+), 3 deletions(-) [+]
line wrap: on
line diff
--- a/src/cpu/arm/vm/sharedRuntime_arm.cpp	Tue Dec 20 15:49:30 2016 -0500
+++ b/src/cpu/arm/vm/sharedRuntime_arm.cpp	Wed Dec 21 17:27:25 2016 +0000
@@ -453,7 +453,7 @@
       }
       break;
     case T_LONG:
-      assert(sig_bt[i+1] == T_VOID, "missing Half" );
+      assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
       // fall through
     case T_ARRAY:
     case T_OBJECT:
@@ -478,7 +478,7 @@
       }
       break;
     case T_DOUBLE:
-      assert(sig_bt[i+1] == T_VOID, "missing Half" );
+      assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
       if (fp_reg < FPR_PARAMS) {
         FloatRegister r = as_FloatRegister(fp_reg);
         regs[i].set2(r->as_VMReg());
@@ -532,7 +532,7 @@
 #ifndef __ABI_HARD__
     case T_DOUBLE:
 #endif // !__ABI_HARD__
-      assert(sig_bt[i+1] == T_VOID, "missing Half" );
+      assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
       if (ireg <= 2) {
 #if (ALIGN_WIDE_ARGUMENTS == 1)
         if(ireg & 1) ireg++;  // Aligned location required