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changeset 9472:54326de2a1d7 jdk8u302-b05

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8267689: [aarch64] Crash due to bad shift in indirect addressing mode Reviewed-by: adinn, aph, phh
author simonis
date Fri, 07 May 2021 19:42:53 +0000
parents 36b8f4cb56c2
children f5e5d3ac66a0
files src/cpu/aarch64/vm/aarch64.ad
diffstat 1 files changed, 43 insertions(+), 5 deletions(-) [+]
line wrap: on
line diff
--- a/src/cpu/aarch64/vm/aarch64.ad	Mon Aug 10 22:42:09 2020 +0300
+++ b/src/cpu/aarch64/vm/aarch64.ad	Fri May 07 19:42:53 2021 +0000
@@ -926,6 +926,8 @@
 
 source_hpp %{
 
+#include "opto/addnode.hpp"
+
 class CallStubImpl {
  
   //--------------------------------------------------------------
@@ -980,6 +982,9 @@
 
   // predicate controlling translation of StoreCM
   bool unnecessary_storestore(const Node *storecm);
+
+  // predicate controlling addressing modes
+  bool size_fits_all_mem_uses(AddPNode* addp, int shift);
 %}
 
 source %{
@@ -2159,6 +2164,19 @@
   return FP_REG_mask();
 }
 
+bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
+  for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
+    Node* u = addp->fast_out(i);
+    if (u->is_Mem()) {
+      int opsize = u->as_Mem()->memory_size();
+      assert(opsize > 0, "unexpected memory operand size");
+      if (u->as_Mem()->memory_size() != (1<<shift)) {
+        return false;
+      }
+    }
+  }
+  return true;
+}
 
 #define MOV_VOLATILE(REG, BASE, INDEX, SCALE, DISP, SCRATCH, INSN)	\
   MacroAssembler _masm(&cbuf);						\
@@ -4755,6 +4773,8 @@
 
 operand indIndexScaledOffsetI(iRegP reg, iRegL lreg, immIScale scale, immIU12 off)
 %{
+  predicate(size_fits_all_mem_uses(n->as_AddP(),
+                                   n->in(AddPNode::Address)->in(AddPNode::Offset)->in(2)->get_int()));
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP (AddP reg (LShiftL lreg scale)) off);
   op_cost(INSN_COST);
@@ -4769,6 +4789,8 @@
 
 operand indIndexScaledOffsetL(iRegP reg, iRegL lreg, immIScale scale, immLU12 off)
 %{
+  predicate(size_fits_all_mem_uses(n->as_AddP(),
+                                   n->in(AddPNode::Address)->in(AddPNode::Offset)->in(2)->get_int()));
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP (AddP reg (LShiftL lreg scale)) off);
   op_cost(INSN_COST);
@@ -4797,6 +4819,8 @@
 
 operand indIndexScaledOffsetI2L(iRegP reg, iRegI ireg, immIScale scale, immLU12 off)
 %{
+  predicate(size_fits_all_mem_uses(n->as_AddP(),
+                                   n->in(AddPNode::Address)->in(AddPNode::Offset)->in(2)->get_int()));
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP (AddP reg (LShiftL (ConvI2L ireg) scale)) off);
   op_cost(INSN_COST);
@@ -4811,6 +4835,8 @@
 
 operand indIndexScaledI2L(iRegP reg, iRegI ireg, immIScale scale)
 %{
+  predicate(size_fits_all_mem_uses(n->as_AddP(),
+                                   n->in(AddPNode::Offset)->in(2)->get_int()));
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP reg (LShiftL (ConvI2L ireg) scale));
   op_cost(0);
@@ -4825,6 +4851,8 @@
 
 operand indIndexScaled(iRegP reg, iRegL lreg, immIScale scale)
 %{
+  predicate(size_fits_all_mem_uses(n->as_AddP(),
+                                   n->in(AddPNode::Offset)->in(2)->get_int()));
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP reg (LShiftL lreg scale));
   op_cost(0);
@@ -4980,7 +5008,9 @@
 
 operand indIndexScaledOffsetIN(iRegN reg, iRegL lreg, immIScale scale, immIU12 off)
 %{
-  predicate(Universe::narrow_oop_shift() == 0);
+  predicate(Universe::narrow_oop_shift() == 0 &&
+            size_fits_all_mem_uses(n->as_AddP(),
+                                   n->in(AddPNode::Address)->in(AddPNode::Offset)->in(2)->get_int()));
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
   op_cost(0);
@@ -4995,7 +5025,9 @@
 
 operand indIndexScaledOffsetLN(iRegN reg, iRegL lreg, immIScale scale, immLU12 off)
 %{
-  predicate(Universe::narrow_oop_shift() == 0);
+  predicate(Universe::narrow_oop_shift() == 0 &&
+            size_fits_all_mem_uses(n->as_AddP(),
+                                   n->in(AddPNode::Address)->in(AddPNode::Offset)->in(2)->get_int()));
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
   op_cost(INSN_COST);
@@ -5025,7 +5057,9 @@
 
 operand indIndexScaledOffsetI2LN(iRegN reg, iRegI ireg, immIScale scale, immLU12 off)
 %{
-  predicate(Universe::narrow_oop_shift() == 0);
+  predicate(Universe::narrow_oop_shift() == 0 &&
+            size_fits_all_mem_uses(n->as_AddP(),
+                                   n->in(AddPNode::Address)->in(AddPNode::Offset)->in(2)->get_int()));
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L ireg) scale)) off);
   op_cost(INSN_COST);
@@ -5040,7 +5074,9 @@
 
 operand indIndexScaledI2LN(iRegN reg, iRegI ireg, immIScale scale)
 %{
-  predicate(Universe::narrow_oop_shift() == 0);
+  predicate(Universe::narrow_oop_shift() == 0 &&
+            size_fits_all_mem_uses(n->as_AddP(),
+                                   n->in(AddPNode::Offset)->in(2)->get_int()));
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP (DecodeN reg) (LShiftL (ConvI2L ireg) scale));
   op_cost(0);
@@ -5055,7 +5091,9 @@
 
 operand indIndexScaledN(iRegN reg, iRegL lreg, immIScale scale)
 %{
-  predicate(Universe::narrow_oop_shift() == 0);
+  predicate(Universe::narrow_oop_shift() == 0 &&
+            size_fits_all_mem_uses(n->as_AddP(),
+                                   n->in(AddPNode::Offset)->in(2)->get_int()));
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP (DecodeN reg) (LShiftL lreg scale));
   op_cost(0);