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changeset 2449:da880ba4edf9

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7031385: incorrect register allocation in release_store_fence on linux x86 Summary: Since gcc 4.5 the inline assembly trying to use r register for an atomic 8-bit exchange and it leads to compilation error Reviewed-by: dsamersoff, dholmes Contributed-by: dbhole@redhat.com
author dsamersoff
date Tue, 03 May 2011 18:43:18 +0400
parents 405c634f4aaa
children f78b3a5497f2
files src/os_cpu/linux_x86/vm/orderAccess_linux_x86.inline.hpp
diffstat 1 files changed, 2 insertions(+), 2 deletions(-) [+]
line wrap: on
line diff
--- a/src/os_cpu/linux_x86/vm/orderAccess_linux_x86.inline.hpp	Mon May 02 14:53:49 2011 -0700
+++ b/src/os_cpu/linux_x86/vm/orderAccess_linux_x86.inline.hpp	Tue May 03 18:43:18 2011 +0400
@@ -93,7 +93,7 @@
 
 inline void     OrderAccess::store_fence(jbyte*  p, jbyte  v) {
   __asm__ volatile (  "xchgb (%2),%0"
-                    : "=r" (v)
+                    : "=q" (v)
                     : "0" (v), "r" (p)
                     : "memory");
 }
@@ -155,7 +155,7 @@
 // Must duplicate definitions instead of calling store_fence because we don't want to cast away volatile.
 inline void     OrderAccess::release_store_fence(volatile jbyte*  p, jbyte  v) {
   __asm__ volatile (  "xchgb (%2),%0"
-                    : "=r" (v)
+                    : "=q" (v)
                     : "0" (v), "r" (p)
                     : "memory");
 }