Mercurial > hg > openjdk > hsx21
changeset 2246:7e88bdae86ec
7029017: Additional architecture support for c2 compiler
Summary: Enables cross building of a c2 VM. Support masking of shift counts when the processor architecture mandates it.
Reviewed-by: kvn, never
| author | roland |
|---|---|
| date | Fri, 25 Mar 2011 09:35:39 +0100 |
| parents | b2949bf39900 |
| children | 244bf8afbbd3 |
| files | make/linux/makefiles/adlc.make make/linux/makefiles/gcc.make make/linux/makefiles/rules.make make/linux/makefiles/sparcWorks.make src/cpu/sparc/vm/sparc.ad src/cpu/x86/vm/x86_32.ad src/cpu/x86/vm/x86_64.ad src/share/vm/adlc/main.cpp src/share/vm/opto/chaitin.cpp src/share/vm/opto/compile.cpp src/share/vm/opto/lcm.cpp src/share/vm/opto/matcher.cpp src/share/vm/opto/matcher.hpp |
| diffstat | 13 files changed, 77 insertions(+), 4 deletions(-) [+] |
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--- a/make/linux/makefiles/adlc.make Fri Mar 25 18:19:22 2011 -0400 +++ b/make/linux/makefiles/adlc.make Fri Mar 25 09:35:39 2011 +0100 @@ -102,7 +102,7 @@ $(EXEC) : $(OBJECTS) @echo Making adlc - $(QUIETLY) $(LINK_NOPROF.CC) -o $(EXEC) $(OBJECTS) + $(QUIETLY) $(HOST.LINK_NOPROF.CC) -o $(EXEC) $(OBJECTS) # Random dependencies: $(OBJECTS): opcodes.hpp classes.hpp adlc.hpp adlcVMDeps.hpp adlparse.hpp archDesc.hpp arena.hpp dict2.hpp filebuff.hpp forms.hpp formsopt.hpp formssel.hpp @@ -204,14 +204,14 @@ $(OUTDIR)/%.o: %.cpp @echo Compiling $< $(QUIETLY) $(REMOVE_TARGET) - $(QUIETLY) $(COMPILE.CC) -o $@ $< $(COMPILE_DONE) + $(QUIETLY) $(HOST.COMPILE.CC) -o $@ $< $(COMPILE_DONE) # Some object files are given a prefix, to disambiguate # them from objects of the same name built for the VM. $(OUTDIR)/adlc-%.o: %.cpp @echo Compiling $< $(QUIETLY) $(REMOVE_TARGET) - $(QUIETLY) $(COMPILE.CC) -o $@ $< $(COMPILE_DONE) + $(QUIETLY) $(HOST.COMPILE.CC) -o $@ $< $(COMPILE_DONE) # #########################################################################
--- a/make/linux/makefiles/gcc.make Fri Mar 25 18:19:22 2011 -0400 +++ b/make/linux/makefiles/gcc.make Fri Mar 25 09:35:39 2011 +0100 @@ -30,9 +30,13 @@ ifdef CROSS_COMPILE_ARCH CPP = $(ALT_COMPILER_PATH)/g++ CC = $(ALT_COMPILER_PATH)/gcc +HOSTCPP = g++ +HOSTCC = gcc else CPP = g++ CC = gcc +HOSTCPP = $(CPP) +HOSTCC = $(CC) endif AS = $(CC) -c
--- a/make/linux/makefiles/rules.make Fri Mar 25 18:19:22 2011 -0400 +++ b/make/linux/makefiles/rules.make Fri Mar 25 09:35:39 2011 +0100 @@ -55,6 +55,14 @@ LINK_LIB.CC = $(CCC) $(LFLAGS) $(SHARED_FLAG) PREPROCESS.CC = $(CC_COMPILE) -E +# cross compiling the jvm with c2 requires host compilers to build +# adlc tool + +HOST.CC_COMPILE = $(HOSTCPP) $(CPPFLAGS) $(CFLAGS) +HOST.COMPILE.CC = $(HOST.CC_COMPILE) -c +HOST.LINK_NOPROF.CC = $(HOSTCPP) $(LFLAGS) $(AOUT_FLAGS) + + # Effect of REMOVE_TARGET is to delete out-of-date files during "gnumake -k". REMOVE_TARGET = rm -f $@
--- a/make/linux/makefiles/sparcWorks.make Fri Mar 25 18:19:22 2011 -0400 +++ b/make/linux/makefiles/sparcWorks.make Fri Mar 25 09:35:39 2011 +0100 @@ -29,6 +29,9 @@ CC = cc AS = $(CC) -c +HOSTCPP = $(CPP) +HOSTCC = $(CC) + ARCHFLAG = $(ARCHFLAG/$(BUILDARCH)) ARCHFLAG/i486 = -m32 ARCHFLAG/amd64 = -m64
--- a/src/cpu/sparc/vm/sparc.ad Fri Mar 25 18:19:22 2011 -0400 +++ b/src/cpu/sparc/vm/sparc.ad Fri Mar 25 09:35:39 2011 +0100 @@ -1843,6 +1843,10 @@ // registers? True for Intel but false for most RISCs const bool Matcher::clone_shift_expressions = false; +// Do we need to mask the count passed to shift instructions or does +// the cpu only look at the lower 5/6 bits anyway? +const bool Matcher::need_masked_shift_count = false; + bool Matcher::narrow_oop_use_complex_address() { NOT_LP64(ShouldNotCallThis()); assert(UseCompressedOops, "only for compressed oops code");
--- a/src/cpu/x86/vm/x86_32.ad Fri Mar 25 18:19:22 2011 -0400 +++ b/src/cpu/x86/vm/x86_32.ad Fri Mar 25 09:35:39 2011 +0100 @@ -1393,6 +1393,10 @@ // registers? True for Intel but false for most RISCs const bool Matcher::clone_shift_expressions = true; +// Do we need to mask the count passed to shift instructions or does +// the cpu only look at the lower 5/6 bits anyway? +const bool Matcher::need_masked_shift_count = false; + bool Matcher::narrow_oop_use_complex_address() { ShouldNotCallThis(); return true;
--- a/src/cpu/x86/vm/x86_64.ad Fri Mar 25 18:19:22 2011 -0400 +++ b/src/cpu/x86/vm/x86_64.ad Fri Mar 25 09:35:39 2011 +0100 @@ -2000,6 +2000,10 @@ // into registers? True for Intel but false for most RISCs const bool Matcher::clone_shift_expressions = true; +// Do we need to mask the count passed to shift instructions or does +// the cpu only look at the lower 5/6 bits anyway? +const bool Matcher::need_masked_shift_count = false; + bool Matcher::narrow_oop_use_complex_address() { assert(UseCompressedOops, "only for compressed oops code"); return (LogMinObjAlignmentInBytes <= 3);
--- a/src/share/vm/adlc/main.cpp Fri Mar 25 18:19:22 2011 -0400 +++ b/src/share/vm/adlc/main.cpp Fri Mar 25 09:35:39 2011 +0100 @@ -240,6 +240,11 @@ AD.addInclude(AD._CPP_file, "nativeInst_sparc.hpp"); AD.addInclude(AD._CPP_file, "vmreg_sparc.inline.hpp"); #endif +#ifdef TARGET_ARCH_arm + AD.addInclude(AD._CPP_file, "assembler_arm.inline.hpp"); + AD.addInclude(AD._CPP_file, "nativeInst_arm.hpp"); + AD.addInclude(AD._CPP_file, "vmreg_arm.inline.hpp"); +#endif AD.addInclude(AD._HPP_file, "memory/allocation.hpp"); AD.addInclude(AD._HPP_file, "opto/machnode.hpp"); AD.addInclude(AD._HPP_file, "opto/node.hpp");
--- a/src/share/vm/opto/chaitin.cpp Fri Mar 25 18:19:22 2011 -0400 +++ b/src/share/vm/opto/chaitin.cpp Fri Mar 25 09:35:39 2011 +0100 @@ -673,7 +673,7 @@ case Op_RegD: lrg.set_num_regs(2); // Define platform specific register pressure -#ifdef SPARC +#if defined(SPARC) || defined(ARM) lrg.set_reg_pressure(2); #elif defined(IA32) if( ireg == Op_RegL ) {
--- a/src/share/vm/opto/compile.cpp Fri Mar 25 18:19:22 2011 -0400 +++ b/src/share/vm/opto/compile.cpp Fri Mar 25 09:35:39 2011 +0100 @@ -2544,6 +2544,36 @@ frc.inc_inner_loop_count(); } break; + case Op_LShiftI: + case Op_RShiftI: + case Op_URShiftI: + case Op_LShiftL: + case Op_RShiftL: + case Op_URShiftL: + if (Matcher::need_masked_shift_count) { + // The cpu's shift instructions don't restrict the count to the + // lower 5/6 bits. We need to do the masking ourselves. + Node* in2 = n->in(2); + juint mask = (n->bottom_type() == TypeInt::INT) ? (BitsPerInt - 1) : (BitsPerLong - 1); + const TypeInt* t = in2->find_int_type(); + if (t != NULL && t->is_con()) { + juint shift = t->get_con(); + if (shift > mask) { // Unsigned cmp + Compile* C = Compile::current(); + n->set_req(2, ConNode::make(C, TypeInt::make(shift & mask))); + } + } else { + if (t == NULL || t->_lo < 0 || t->_hi > (int)mask) { + Compile* C = Compile::current(); + Node* shift = new (C, 3) AndINode(in2, ConNode::make(C, TypeInt::make(mask))); + n->set_req(2, shift); + } + } + if (in2->outcnt() == 0) { // Remove dead node + in2->disconnect_inputs(NULL); + } + } + break; default: assert( !n->is_Call(), "" ); assert( !n->is_Mem(), "" );
--- a/src/share/vm/opto/lcm.cpp Fri Mar 25 18:19:22 2011 -0400 +++ b/src/share/vm/opto/lcm.cpp Fri Mar 25 09:35:39 2011 +0100 @@ -42,6 +42,9 @@ #ifdef TARGET_ARCH_MODEL_zero # include "adfiles/ad_zero.hpp" #endif +#ifdef TARGET_ARCH_MODEL_arm +# include "adfiles/ad_arm.hpp" +#endif // Optimization - Graph Style
--- a/src/share/vm/opto/matcher.cpp Fri Mar 25 18:19:22 2011 -0400 +++ b/src/share/vm/opto/matcher.cpp Fri Mar 25 09:35:39 2011 +0100 @@ -49,6 +49,9 @@ #ifdef TARGET_ARCH_MODEL_zero # include "adfiles/ad_zero.hpp" #endif +#ifdef TARGET_ARCH_MODEL_arm +# include "adfiles/ad_arm.hpp" +#endif OptoReg::Name OptoReg::c_frame_pointer;
--- a/src/share/vm/opto/matcher.hpp Fri Mar 25 18:19:22 2011 -0400 +++ b/src/share/vm/opto/matcher.hpp Fri Mar 25 09:35:39 2011 +0100 @@ -427,6 +427,11 @@ // Do ints take an entire long register or just half? static const bool int_in_long; + // Do the processor's shift instructions only use the low 5/6 bits + // of the count for 32/64 bit ints? If not we need to do the masking + // ourselves. + static const bool need_masked_shift_count; + // This routine is run whenever a graph fails to match. // If it returns, the compiler should bailout to interpreter without error. // In non-product mode, SoftMatchFailure is false to detect non-canonical