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changeset 8587:0dab40fe02b2

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8146843: aarch64: add scheduling support for FP and vector instructions Summary: add pipeline classes for FP/vector pipeline Reviewed-by: aph
author enevill
date Tue, 12 Jan 2016 14:55:15 +0000
parents 2cb7b89688d8
children 220fb5b3d9ce
files src/cpu/aarch64/vm/aarch64.ad
diffstat 1 files changed, 632 insertions(+), 137 deletions(-) [+]
line wrap: on
line diff
--- a/src/cpu/aarch64/vm/aarch64.ad	Fri Jan 08 11:39:47 2016 +0000
+++ b/src/cpu/aarch64/vm/aarch64.ad	Tue Jan 12 14:55:15 2016 +0000
@@ -6715,6 +6715,14 @@
 
 //----------PIPELINE-----------------------------------------------------------
 // Rules which define the behavior of the target architectures pipeline.
+
+// For specific pipelines, eg A53, define the stages of that pipeline
+//pipe_desc(ISS, EX1, EX2, WR);
+#define ISS S0
+#define EX1 S1
+#define EX2 S2
+#define WR  S3
+
 // Integer ALU reg operation
 pipeline %{
 
@@ -6749,12 +6757,499 @@
 //----------PIPELINE DESCRIPTION-----------------------------------------------
 // Pipeline Description specifies the stages in the machine's pipeline
 
-pipe_desc(ISS, EX1, EX2, WR);
+// Define the pipeline as a generic 6 stage pipeline
+pipe_desc(S0, S1, S2, S3, S4, S5);
 
 //----------PIPELINE CLASSES---------------------------------------------------
 // Pipeline Classes describe the stages in which input and output are
 // referenced by the hardware pipeline.
 
+pipe_class fp_dop_reg_reg_s(vRegF dst, vRegF src1, vRegF src2)
+%{
+  single_instruction;
+  src1   : S1(read);
+  src2   : S2(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_dop_reg_reg_d(vRegD dst, vRegD src1, vRegD src2)
+%{
+  single_instruction;
+  src1   : S1(read);
+  src2   : S2(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_uop_s(vRegF dst, vRegF src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_uop_d(vRegD dst, vRegD src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_d2f(vRegF dst, vRegD src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_f2d(vRegD dst, vRegF src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_f2i(iRegINoSp dst, vRegF src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_f2l(iRegLNoSp dst, vRegF src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_i2f(vRegF dst, iRegIorL2I src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_l2f(vRegF dst, iRegL src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_d2i(iRegINoSp dst, vRegD src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_d2l(iRegLNoSp dst, vRegD src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_i2d(vRegD dst, iRegIorL2I src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_l2d(vRegD dst, iRegIorL2I src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_div_s(vRegF dst, vRegF src1, vRegF src2)
+%{
+  single_instruction;
+  src1   : S1(read);
+  src2   : S2(read);
+  dst    : S5(write);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_div_d(vRegD dst, vRegD src1, vRegD src2)
+%{
+  single_instruction;
+  src1   : S1(read);
+  src2   : S2(read);
+  dst    : S5(write);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_cond_reg_reg_s(vRegF dst, vRegF src1, vRegF src2, rFlagsReg cr)
+%{
+  single_instruction;
+  cr     : S1(read);
+  src1   : S1(read);
+  src2   : S1(read);
+  dst    : S3(write);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class fp_cond_reg_reg_d(vRegD dst, vRegD src1, vRegD src2, rFlagsReg cr)
+%{
+  single_instruction;
+  cr     : S1(read);
+  src1   : S1(read);
+  src2   : S1(read);
+  dst    : S3(write);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class fp_imm_s(vRegF dst)
+%{
+  single_instruction;
+  dst    : S3(write);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class fp_imm_d(vRegD dst)
+%{
+  single_instruction;
+  dst    : S3(write);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class fp_load_constant_s(vRegF dst)
+%{
+  single_instruction;
+  dst    : S4(write);
+  INS01  : ISS;
+  NEON_FP : S4;
+%}
+
+pipe_class fp_load_constant_d(vRegD dst)
+%{
+  single_instruction;
+  dst    : S4(write);
+  INS01  : ISS;
+  NEON_FP : S4;
+%}
+
+pipe_class vmul64(vecD dst, vecD src1, vecD src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vmul128(vecX dst, vecX src1, vecX src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vmla64(vecD dst, vecD src1, vecD src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  dst    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vmla128(vecX dst, vecX src1, vecX src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  dst    : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vdop64(vecD dst, vecD src1, vecD src2)
+%{
+  single_instruction;
+  dst    : S4(write);
+  src1   : S2(read);
+  src2   : S2(read);
+  INS01  : ISS;
+  NEON_FP : S4;
+%}
+
+pipe_class vdop128(vecX dst, vecX src1, vecX src2)
+%{
+  single_instruction;
+  dst    : S4(write);
+  src1   : S2(read);
+  src2   : S2(read);
+  INS0   : ISS;
+  NEON_FP : S4;
+%}
+
+pipe_class vlogical64(vecD dst, vecD src1, vecD src2)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src1   : S2(read);
+  src2   : S2(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vlogical128(vecX dst, vecX src1, vecX src2)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src1   : S2(read);
+  src2   : S2(read);
+  INS0   : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vshift64(vecD dst, vecD src, vecX shift)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  shift  : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vshift128(vecX dst, vecX src, vecX shift)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  shift  : S1(read);
+  INS0   : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vshift64_imm(vecD dst, vecD src, immI shift)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vshift128_imm(vecX dst, vecX src, immI shift)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS0   : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vdop_fp64(vecD dst, vecD src1, vecD src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vdop_fp128(vecX dst, vecX src1, vecX src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vmuldiv_fp64(vecD dst, vecD src1, vecD src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vmuldiv_fp128(vecX dst, vecX src1, vecX src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vsqrt_fp128(vecX dst, vecX src)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src    : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vunop_fp64(vecD dst, vecD src)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vunop_fp128(vecX dst, vecX src)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src    : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vdup_reg_reg64(vecD dst, iRegI src)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vdup_reg_reg128(vecX dst, iRegI src)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vdup_reg_freg64(vecD dst, vRegF src)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vdup_reg_freg128(vecX dst, vRegF src)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vdup_reg_dreg128(vecX dst, vRegD src)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vmovi_reg_imm64(vecD dst)
+%{
+  single_instruction;
+  dst    : S3(write);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vmovi_reg_imm128(vecX dst)
+%{
+  single_instruction;
+  dst    : S3(write);
+  INS0   : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vload_reg_mem64(vecD dst, vmem mem)
+%{
+  single_instruction;
+  dst    : S5(write);
+  mem    : ISS(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vload_reg_mem128(vecX dst, vmem mem)
+%{
+  single_instruction;
+  dst    : S5(write);
+  mem    : ISS(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vstore_reg_mem64(vecD src, vmem mem)
+%{
+  single_instruction;
+  mem    : ISS(read);
+  src    : S2(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vstore_reg_mem128(vecD src, vmem mem)
+%{
+  single_instruction;
+  mem    : ISS(read);
+  src    : S2(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
 //------- Integer ALU operations --------------------------
 
 // Integer ALU reg-reg operation
@@ -7601,7 +8096,7 @@
     __ fmovs(as_FloatRegister($dst$$reg), (double)$con$$constant);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_imm_s);
 %}
 
 // Load Float Constant
@@ -7619,7 +8114,7 @@
     __ ldrs(as_FloatRegister($dst$$reg), $constantaddress($con));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_load_constant_s);
 %}
 
 // Load Packed Double Constant
@@ -7632,7 +8127,7 @@
     __ fmovd(as_FloatRegister($dst$$reg), $con$$constant);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_imm_d);
 %}
 
 // Load Double Constant
@@ -7649,7 +8144,7 @@
     __ ldrd(as_FloatRegister($dst$$reg), $constantaddress($con));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_load_constant_d);
 %}
 
 // Store Instructions
@@ -9632,7 +10127,7 @@
               cond);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_cond_reg_reg_s);
 %}
 
 instruct cmovUF_reg(cmpOpU cmp, rFlagsRegU cr, vRegF dst, vRegF src1,  vRegF src2)
@@ -9650,7 +10145,7 @@
               cond);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_cond_reg_reg_s);
 %}
 
 instruct cmovD_reg(cmpOp cmp, rFlagsReg cr, vRegD dst, vRegD src1,  vRegD src2)
@@ -9668,7 +10163,7 @@
               cond);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_cond_reg_reg_d);
 %}
 
 instruct cmovUD_reg(cmpOpU cmp, rFlagsRegU cr, vRegD dst, vRegD src1,  vRegD src2)
@@ -9686,7 +10181,7 @@
               cond);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_cond_reg_reg_d);
 %}
 
 // ============================================================================
@@ -12050,7 +12545,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_dop_reg_reg_s);
 %}
 
 instruct addD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
@@ -12065,7 +12560,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_dop_reg_reg_d);
 %}
 
 instruct subF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
@@ -12080,7 +12575,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_dop_reg_reg_s);
 %}
 
 instruct subD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
@@ -12095,7 +12590,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_dop_reg_reg_d);
 %}
 
 instruct mulF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
@@ -12110,7 +12605,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_dop_reg_reg_s);
 %}
 
 instruct mulD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
@@ -12125,7 +12620,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_dop_reg_reg_d);
 %}
 
 // We cannot use these fused mul w add/sub ops because they don't
@@ -12273,7 +12768,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_div_s);
 %}
 
 instruct divD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
@@ -12288,7 +12783,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_div_d);
 %}
 
 instruct negF_reg_reg(vRegF dst, vRegF src) %{
@@ -12302,7 +12797,7 @@
              as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_uop_s);
 %}
 
 instruct negD_reg_reg(vRegD dst, vRegD src) %{
@@ -12316,7 +12811,7 @@
              as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_uop_d);
 %}
 
 instruct absF_reg(vRegF dst, vRegF src) %{
@@ -12329,7 +12824,7 @@
              as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_uop_s);
 %}
 
 instruct absD_reg(vRegD dst, vRegD src) %{
@@ -12342,7 +12837,7 @@
              as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_uop_d);
 %}
 
 instruct sqrtD_reg(vRegD dst, vRegD src) %{
@@ -12355,7 +12850,7 @@
              as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_div_s);
 %}
 
 instruct sqrtF_reg(vRegF dst, vRegF src) %{
@@ -12368,7 +12863,7 @@
              as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_div_d);
 %}
 
 // ============================================================================
@@ -12655,7 +13150,7 @@
     __ fcvtd(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_d2f);
 %}
 
 instruct convF2D_reg(vRegD dst, vRegF src) %{
@@ -12668,7 +13163,7 @@
     __ fcvts(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_f2d);
 %}
 
 instruct convF2I_reg_reg(iRegINoSp dst, vRegF src) %{
@@ -12681,7 +13176,7 @@
     __ fcvtzsw(as_Register($dst$$reg), as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_f2i);
 %}
 
 instruct convF2L_reg_reg(iRegLNoSp dst, vRegF src) %{
@@ -12694,7 +13189,7 @@
     __ fcvtzs(as_Register($dst$$reg), as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_f2l);
 %}
 
 instruct convI2F_reg_reg(vRegF dst, iRegIorL2I src) %{
@@ -12707,7 +13202,7 @@
     __ scvtfws(as_FloatRegister($dst$$reg), as_Register($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_i2f);
 %}
 
 instruct convL2F_reg_reg(vRegF dst, iRegL src) %{
@@ -12720,7 +13215,7 @@
     __ scvtfs(as_FloatRegister($dst$$reg), as_Register($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_l2f);
 %}
 
 instruct convD2I_reg_reg(iRegINoSp dst, vRegD src) %{
@@ -12733,7 +13228,7 @@
     __ fcvtzdw(as_Register($dst$$reg), as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_d2i);
 %}
 
 instruct convD2L_reg_reg(iRegLNoSp dst, vRegD src) %{
@@ -12746,7 +13241,7 @@
     __ fcvtzd(as_Register($dst$$reg), as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_d2l);
 %}
 
 instruct convI2D_reg_reg(vRegD dst, iRegIorL2I src) %{
@@ -12759,7 +13254,7 @@
     __ scvtfwd(as_FloatRegister($dst$$reg), as_Register($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_i2d);
 %}
 
 instruct convL2D_reg_reg(vRegD dst, iRegL src) %{
@@ -12772,7 +13267,7 @@
     __ scvtfd(as_FloatRegister($dst$$reg), as_Register($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_l2d);
 %}
 
 // stack <-> reg and reg <-> reg shuffles with no conversion
@@ -14552,7 +15047,7 @@
   ins_cost(4 * INSN_COST);
   format %{ "ldrs   $dst,$mem\t# vector (32 bits)" %}
   ins_encode( aarch64_enc_ldrvS(dst, mem) );
-  ins_pipe(pipe_class_memory);
+  ins_pipe(vload_reg_mem64);
 %}
 
 // Load vector (64 bits)
@@ -14563,7 +15058,7 @@
   ins_cost(4 * INSN_COST);
   format %{ "ldrd   $dst,$mem\t# vector (64 bits)" %}
   ins_encode( aarch64_enc_ldrvD(dst, mem) );
-  ins_pipe(pipe_class_memory);
+  ins_pipe(vload_reg_mem64);
 %}
 
 // Load Vector (128 bits)
@@ -14574,7 +15069,7 @@
   ins_cost(4 * INSN_COST);
   format %{ "ldrq   $dst,$mem\t# vector (128 bits)" %}
   ins_encode( aarch64_enc_ldrvQ(dst, mem) );
-  ins_pipe(pipe_class_memory);
+  ins_pipe(vload_reg_mem128);
 %}
 
 // Store Vector (32 bits)
@@ -14585,7 +15080,7 @@
   ins_cost(4 * INSN_COST);
   format %{ "strs   $mem,$src\t# vector (32 bits)" %}
   ins_encode( aarch64_enc_strvS(src, mem) );
-  ins_pipe(pipe_class_memory);
+  ins_pipe(vstore_reg_mem64);
 %}
 
 // Store Vector (64 bits)
@@ -14596,7 +15091,7 @@
   ins_cost(4 * INSN_COST);
   format %{ "strd   $mem,$src\t# vector (64 bits)" %}
   ins_encode( aarch64_enc_strvD(src, mem) );
-  ins_pipe(pipe_class_memory);
+  ins_pipe(vstore_reg_mem64);
 %}
 
 // Store Vector (128 bits)
@@ -14607,7 +15102,7 @@
   ins_cost(4 * INSN_COST);
   format %{ "strq   $mem,$src\t# vector (128 bits)" %}
   ins_encode( aarch64_enc_strvQ(src, mem) );
-  ins_pipe(pipe_class_memory);
+  ins_pipe(vstore_reg_mem128);
 %}
 
 instruct replicate8B(vecD dst, iRegIorL2I src)
@@ -14620,7 +15115,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T8B, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg64);
 %}
 
 instruct replicate16B(vecX dst, iRegIorL2I src)
@@ -14632,7 +15127,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg128);
 %}
 
 instruct replicate8B_imm(vecD dst, immI con)
@@ -14645,7 +15140,7 @@
   ins_encode %{
     __ mov(as_FloatRegister($dst$$reg), __ T8B, $con$$constant & 0xff);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm64);
 %}
 
 instruct replicate16B_imm(vecX dst, immI con)
@@ -14657,7 +15152,7 @@
   ins_encode %{
     __ mov(as_FloatRegister($dst$$reg), __ T16B, $con$$constant & 0xff);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm128);
 %}
 
 instruct replicate4S(vecD dst, iRegIorL2I src)
@@ -14670,7 +15165,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T4H, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg64);
 %}
 
 instruct replicate8S(vecX dst, iRegIorL2I src)
@@ -14682,7 +15177,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T8H, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg128);
 %}
 
 instruct replicate4S_imm(vecD dst, immI con)
@@ -14695,7 +15190,7 @@
   ins_encode %{
     __ mov(as_FloatRegister($dst$$reg), __ T4H, $con$$constant & 0xffff);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm64);
 %}
 
 instruct replicate8S_imm(vecX dst, immI con)
@@ -14707,7 +15202,7 @@
   ins_encode %{
     __ mov(as_FloatRegister($dst$$reg), __ T8H, $con$$constant & 0xffff);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm128);
 %}
 
 instruct replicate2I(vecD dst, iRegIorL2I src)
@@ -14719,7 +15214,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T2S, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg64);
 %}
 
 instruct replicate4I(vecX dst, iRegIorL2I src)
@@ -14731,7 +15226,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T4S, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg128);
 %}
 
 instruct replicate2I_imm(vecD dst, immI con)
@@ -14743,7 +15238,7 @@
   ins_encode %{
     __ mov(as_FloatRegister($dst$$reg), __ T2S, $con$$constant);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm64);
 %}
 
 instruct replicate4I_imm(vecX dst, immI con)
@@ -14755,7 +15250,7 @@
   ins_encode %{
     __ mov(as_FloatRegister($dst$$reg), __ T4S, $con$$constant);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm128);
 %}
 
 instruct replicate2L(vecX dst, iRegL src)
@@ -14767,7 +15262,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T2D, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg128);
 %}
 
 instruct replicate2L_zero(vecX dst, immI0 zero)
@@ -14781,7 +15276,7 @@
            as_FloatRegister($dst$$reg),
            as_FloatRegister($dst$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm128);
 %}
 
 instruct replicate2F(vecD dst, vRegF src)
@@ -14794,7 +15289,7 @@
     __ dup(as_FloatRegister($dst$$reg), __ T2S,
            as_FloatRegister($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_freg64);
 %}
 
 instruct replicate4F(vecX dst, vRegF src)
@@ -14807,7 +15302,7 @@
     __ dup(as_FloatRegister($dst$$reg), __ T4S,
            as_FloatRegister($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_freg128);
 %}
 
 instruct replicate2D(vecX dst, vRegD src)
@@ -14820,7 +15315,7 @@
     __ dup(as_FloatRegister($dst$$reg), __ T2D,
            as_FloatRegister($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_dreg128);
 %}
 
 // ====================VECTOR ARITHMETIC=======================================
@@ -14839,7 +15334,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop64);
 %}
 
 instruct vadd16B(vecX dst, vecX src1, vecX src2)
@@ -14853,7 +15348,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vadd4S(vecD dst, vecD src1, vecD src2)
@@ -14868,7 +15363,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop64);
 %}
 
 instruct vadd8S(vecX dst, vecX src1, vecX src2)
@@ -14882,7 +15377,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vadd2I(vecD dst, vecD src1, vecD src2)
@@ -14896,7 +15391,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop64);
 %}
 
 instruct vadd4I(vecX dst, vecX src1, vecX src2)
@@ -14910,7 +15405,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vadd2L(vecX dst, vecX src1, vecX src2)
@@ -14924,7 +15419,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vadd2F(vecD dst, vecD src1, vecD src2)
@@ -14938,7 +15433,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop_fp64);
 %}
 
 instruct vadd4F(vecX dst, vecX src1, vecX src2)
@@ -14952,7 +15447,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop_fp128);
 %}
 
 instruct vadd2D(vecX dst, vecX src1, vecX src2)
@@ -14965,7 +15460,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop_fp128);
 %}
 
 // --------------------------------- SUB --------------------------------------
@@ -14982,7 +15477,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop64);
 %}
 
 instruct vsub16B(vecX dst, vecX src1, vecX src2)
@@ -14996,7 +15491,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vsub4S(vecD dst, vecD src1, vecD src2)
@@ -15011,7 +15506,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop64);
 %}
 
 instruct vsub8S(vecX dst, vecX src1, vecX src2)
@@ -15025,7 +15520,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vsub2I(vecD dst, vecD src1, vecD src2)
@@ -15039,7 +15534,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop64);
 %}
 
 instruct vsub4I(vecX dst, vecX src1, vecX src2)
@@ -15053,7 +15548,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vsub2L(vecX dst, vecX src1, vecX src2)
@@ -15067,7 +15562,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vsub2F(vecD dst, vecD src1, vecD src2)
@@ -15081,7 +15576,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop_fp64);
 %}
 
 instruct vsub4F(vecX dst, vecX src1, vecX src2)
@@ -15095,7 +15590,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop_fp128);
 %}
 
 instruct vsub2D(vecX dst, vecX src1, vecX src2)
@@ -15109,7 +15604,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop_fp128);
 %}
 
 // --------------------------------- MUL --------------------------------------
@@ -15126,7 +15621,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmul64);
 %}
 
 instruct vmul8S(vecX dst, vecX src1, vecX src2)
@@ -15140,7 +15635,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmul128);
 %}
 
 instruct vmul2I(vecD dst, vecD src1, vecD src2)
@@ -15154,7 +15649,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmul64);
 %}
 
 instruct vmul4I(vecX dst, vecX src1, vecX src2)
@@ -15168,7 +15663,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmul128);
 %}
 
 instruct vmul2F(vecD dst, vecD src1, vecD src2)
@@ -15182,7 +15677,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmuldiv_fp64);
 %}
 
 instruct vmul4F(vecX dst, vecX src1, vecX src2)
@@ -15196,7 +15691,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmuldiv_fp128);
 %}
 
 instruct vmul2D(vecX dst, vecX src1, vecX src2)
@@ -15210,7 +15705,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmuldiv_fp128);
 %}
 
 // --------------------------------- MLA --------------------------------------
@@ -15227,7 +15722,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla64);
 %}
 
 instruct vmla8S(vecX dst, vecX src1, vecX src2)
@@ -15241,7 +15736,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla128);
 %}
 
 instruct vmla2I(vecD dst, vecD src1, vecD src2)
@@ -15255,7 +15750,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla64);
 %}
 
 instruct vmla4I(vecX dst, vecX src1, vecX src2)
@@ -15269,7 +15764,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla128);
 %}
 
 // --------------------------------- MLS --------------------------------------
@@ -15286,7 +15781,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla64);
 %}
 
 instruct vmls8S(vecX dst, vecX src1, vecX src2)
@@ -15300,7 +15795,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla128);
 %}
 
 instruct vmls2I(vecD dst, vecD src1, vecD src2)
@@ -15314,7 +15809,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla64);
 %}
 
 instruct vmls4I(vecX dst, vecX src1, vecX src2)
@@ -15328,7 +15823,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla128);
 %}
 
 // --------------------------------- DIV --------------------------------------
@@ -15344,7 +15839,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmuldiv_fp64);
 %}
 
 instruct vdiv4F(vecX dst, vecX src1, vecX src2)
@@ -15358,7 +15853,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmuldiv_fp128);
 %}
 
 instruct vdiv2D(vecX dst, vecX src1, vecX src2)
@@ -15372,7 +15867,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmuldiv_fp128);
 %}
 
 // --------------------------------- AND --------------------------------------
@@ -15389,7 +15884,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vlogical64);
 %}
 
 instruct vand16B(vecX dst, vecX src1, vecX src2)
@@ -15403,7 +15898,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vlogical128);
 %}
 
 // --------------------------------- OR ---------------------------------------
@@ -15420,7 +15915,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vlogical64);
 %}
 
 instruct vor16B(vecX dst, vecX src1, vecX src2)
@@ -15434,7 +15929,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vlogical128);
 %}
 
 // --------------------------------- XOR --------------------------------------
@@ -15451,7 +15946,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vlogical64);
 %}
 
 instruct vxor16B(vecX dst, vecX src1, vecX src2)
@@ -15465,7 +15960,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vlogical128);
 %}
 
 // ------------------------------ Shift ---------------------------------------
@@ -15476,7 +15971,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg128);
 %}
 
 // Right shifts on aarch64 SIMD are implemented as left shift by -ve amount
@@ -15487,7 +15982,7 @@
     __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg));
     __ negr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg128);
 %}
 
 instruct vsll8B(vecD dst, vecD src, vecX shift) %{
@@ -15502,7 +15997,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64);
 %}
 
 instruct vsll16B(vecX dst, vecX src, vecX shift) %{
@@ -15516,7 +16011,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsrl8B(vecD dst, vecD src, vecX shift) %{
@@ -15530,7 +16025,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64);
 %}
 
 instruct vsrl16B(vecX dst, vecX src, vecX shift) %{
@@ -15543,7 +16038,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsll8B_imm(vecD dst, vecD src, immI shift) %{
@@ -15563,7 +16058,7 @@
              as_FloatRegister($src$$reg), sh);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsll16B_imm(vecX dst, vecX src, immI shift) %{
@@ -15582,7 +16077,7 @@
              as_FloatRegister($src$$reg), sh);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsra8B_imm(vecD dst, vecD src, immI shift) %{
@@ -15598,7 +16093,7 @@
     __ sshr(as_FloatRegister($dst$$reg), __ T8B,
            as_FloatRegister($src$$reg), sh);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsra16B_imm(vecX dst, vecX src, immI shift) %{
@@ -15613,7 +16108,7 @@
     __ sshr(as_FloatRegister($dst$$reg), __ T16B,
            as_FloatRegister($src$$reg), sh);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsrl8B_imm(vecD dst, vecD src, immI shift) %{
@@ -15633,7 +16128,7 @@
              as_FloatRegister($src$$reg), -sh & 7);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsrl16B_imm(vecX dst, vecX src, immI shift) %{
@@ -15652,7 +16147,7 @@
              as_FloatRegister($src$$reg), -sh & 7);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsll4S(vecD dst, vecD src, vecX shift) %{
@@ -15667,7 +16162,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64);
 %}
 
 instruct vsll8S(vecX dst, vecX src, vecX shift) %{
@@ -15681,7 +16176,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsrl4S(vecD dst, vecD src, vecX shift) %{
@@ -15695,7 +16190,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64);
 %}
 
 instruct vsrl8S(vecX dst, vecX src, vecX shift) %{
@@ -15708,7 +16203,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsll4S_imm(vecD dst, vecD src, immI shift) %{
@@ -15728,7 +16223,7 @@
              as_FloatRegister($src$$reg), sh);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsll8S_imm(vecX dst, vecX src, immI shift) %{
@@ -15747,7 +16242,7 @@
              as_FloatRegister($src$$reg), sh);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsra4S_imm(vecD dst, vecD src, immI shift) %{
@@ -15763,7 +16258,7 @@
     __ sshr(as_FloatRegister($dst$$reg), __ T4H,
            as_FloatRegister($src$$reg), sh);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsra8S_imm(vecX dst, vecX src, immI shift) %{
@@ -15778,7 +16273,7 @@
     __ sshr(as_FloatRegister($dst$$reg), __ T8H,
            as_FloatRegister($src$$reg), sh);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsrl4S_imm(vecD dst, vecD src, immI shift) %{
@@ -15798,7 +16293,7 @@
              as_FloatRegister($src$$reg), -sh & 15);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsrl8S_imm(vecX dst, vecX src, immI shift) %{
@@ -15817,7 +16312,7 @@
              as_FloatRegister($src$$reg), -sh & 15);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsll2I(vecD dst, vecD src, vecX shift) %{
@@ -15831,7 +16326,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsll4I(vecX dst, vecX src, vecX shift) %{
@@ -15845,7 +16340,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsrl2I(vecD dst, vecD src, vecX shift) %{
@@ -15858,7 +16353,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsrl4I(vecX dst, vecX src, vecX shift) %{
@@ -15871,7 +16366,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsll2I_imm(vecD dst, vecD src, immI shift) %{
@@ -15884,7 +16379,7 @@
            as_FloatRegister($src$$reg),
            (int)$shift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsll4I_imm(vecX dst, vecX src, immI shift) %{
@@ -15897,7 +16392,7 @@
            as_FloatRegister($src$$reg),
            (int)$shift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsra2I_imm(vecD dst, vecD src, immI shift) %{
@@ -15910,7 +16405,7 @@
             as_FloatRegister($src$$reg),
             -(int)$shift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsra4I_imm(vecX dst, vecX src, immI shift) %{
@@ -15923,7 +16418,7 @@
             as_FloatRegister($src$$reg),
             -(int)$shift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsrl2I_imm(vecD dst, vecD src, immI shift) %{
@@ -15936,7 +16431,7 @@
             as_FloatRegister($src$$reg),
             -(int)$shift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsrl4I_imm(vecX dst, vecX src, immI shift) %{
@@ -15949,7 +16444,7 @@
             as_FloatRegister($src$$reg),
             -(int)$shift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsll2L(vecX dst, vecX src, vecX shift) %{
@@ -15963,7 +16458,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsrl2L(vecX dst, vecX src, vecX shift) %{
@@ -15976,7 +16471,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsll2L_imm(vecX dst, vecX src, immI shift) %{
@@ -15989,7 +16484,7 @@
            as_FloatRegister($src$$reg),
            (int)$shift$$constant & 63);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{
@@ -16002,7 +16497,7 @@
             as_FloatRegister($src$$reg),
             -(int)$shift$$constant & 63);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{
@@ -16015,7 +16510,7 @@
             as_FloatRegister($src$$reg),
             -(int)$shift$$constant & 63);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 //----------PEEPHOLE RULES-----------------------------------------------------