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changeset 9701:6ed37de41ebb

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8135035: Reverse changes from 8075093 Summary: 8075093 turn on FPU spilling that need to be stabilized first Reviewed-by: kvn
author iveresov
date Thu, 03 Sep 2015 14:29:08 -0700
parents 979c4f71a3c8
children 66e8f7dba7d8
files src/cpu/sparc/vm/vm_version_sparc.cpp
diffstat 1 files changed, 3 insertions(+), 12 deletions(-) [+]
line wrap: on
line diff
--- a/src/cpu/sparc/vm/vm_version_sparc.cpp	Mon Aug 31 17:20:08 2015 +0200
+++ b/src/cpu/sparc/vm/vm_version_sparc.cpp	Thu Sep 03 14:29:08 2015 -0700
@@ -218,6 +218,9 @@
     FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
   }
 
+  // Currently not supported anywhere.
+  FLAG_SET_DEFAULT(UseFPUForSpilling, false);
+
   MaxVectorSize = 8;
 
   assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
@@ -263,18 +266,6 @@
   if (!has_vis1()) // Drop to 0 if no VIS1 support
     UseVIS = 0;
 
-  // Enable UseFPUForSpilling if low-latency GP-to-FP register move instructions are available
-  if (UseVIS > 2) { // FP spill use VIS3 MOVxTOd/MOVdTOx
-    if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
-      FLAG_SET_DEFAULT(UseFPUForSpilling, true);
-    }
-  } else if (UseFPUForSpilling) {
-    if (!FLAG_IS_DEFAULT(UseFPUForSpilling)) {
-      warning("Spill to float registers requires VIS3 instructions (not available on this CPU).");
-    }
-    FLAG_SET_DEFAULT(UseFPUForSpilling, false);
-  }
-
   // SPARC T4 and above should have support for AES instructions
   if (has_aes()) {
     if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3