Mercurial > hg > icedtea8-forest > hotspot
changeset 10922:27cf2684ed40
Normalise AArch64 sources, prior to merge of upstream version.
line wrap: on
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--- a/src/cpu/aarch64/vm/assembler_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/assembler_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -79,8 +79,8 @@ // { // for (int i = 0; i < 256; i+=16) // { - // printf("\"%20.20g\", ", unpack(i)); - // printf("\"%20.20g\", ", unpack(i+1)); + // printf("\"%20.20g\", ", unpack(i)); + // printf("\"%20.20g\", ", unpack(i+1)); // } // printf("\n"); // } @@ -96,531 +96,531 @@ __ bind(back); // ArithOp - __ add(r19, r22, r7, Assembler::LSL, 28); // add x19, x22, x7, LSL #28 - __ sub(r16, r11, r10, Assembler::LSR, 13); // sub x16, x11, x10, LSR #13 - __ adds(r27, r13, r28, Assembler::ASR, 2); // adds x27, x13, x28, ASR #2 - __ subs(r20, r28, r26, Assembler::ASR, 41); // subs x20, x28, x26, ASR #41 - __ addw(r8, r19, r19, Assembler::ASR, 19); // add w8, w19, w19, ASR #19 - __ subw(r4, r9, r10, Assembler::LSL, 14); // sub w4, w9, w10, LSL #14 - __ addsw(r8, r11, r30, Assembler::LSL, 13); // adds w8, w11, w30, LSL #13 - __ subsw(r0, r25, r19, Assembler::LSL, 9); // subs w0, w25, w19, LSL #9 - __ andr(r20, r0, r21, Assembler::LSL, 19); // and x20, x0, x21, LSL #19 - __ orr(r21, r14, r20, Assembler::LSL, 17); // orr x21, x14, x20, LSL #17 - __ eor(r25, r28, r1, Assembler::LSL, 51); // eor x25, x28, x1, LSL #51 - __ ands(r10, r27, r11, Assembler::ASR, 15); // ands x10, x27, x11, ASR #15 - __ andw(r25, r5, r12, Assembler::ASR, 23); // and w25, w5, w12, ASR #23 - __ orrw(r18, r14, r10, Assembler::LSR, 4); // orr w18, w14, w10, LSR #4 - __ eorw(r4, r21, r5, Assembler::ASR, 22); // eor w4, w21, w5, ASR #22 - __ andsw(r21, r0, r5, Assembler::ASR, 29); // ands w21, w0, w5, ASR #29 - __ bic(r26, r30, r6, Assembler::ASR, 37); // bic x26, x30, x6, ASR #37 - __ orn(r3, r1, r13, Assembler::LSR, 29); // orn x3, x1, x13, LSR #29 - __ eon(r0, r28, r9, Assembler::LSL, 47); // eon x0, x28, x9, LSL #47 - __ bics(r29, r5, r28, Assembler::LSL, 46); // bics x29, x5, x28, LSL #46 - __ bicw(r9, r18, r7, Assembler::LSR, 20); // bic w9, w18, w7, LSR #20 - __ ornw(r26, r13, r25, Assembler::ASR, 24); // orn w26, w13, w25, ASR #24 - __ eonw(r25, r4, r19, Assembler::LSL, 6); // eon w25, w4, w19, LSL #6 - __ bicsw(r5, r26, r4, Assembler::LSR, 24); // bics w5, w26, w4, LSR #24 + __ add(r19, r22, r7, Assembler::LSL, 28); // add x19, x22, x7, LSL #28 + __ sub(r16, r11, r10, Assembler::LSR, 13); // sub x16, x11, x10, LSR #13 + __ adds(r27, r13, r28, Assembler::ASR, 2); // adds x27, x13, x28, ASR #2 + __ subs(r20, r28, r26, Assembler::ASR, 41); // subs x20, x28, x26, ASR #41 + __ addw(r8, r19, r19, Assembler::ASR, 19); // add w8, w19, w19, ASR #19 + __ subw(r4, r9, r10, Assembler::LSL, 14); // sub w4, w9, w10, LSL #14 + __ addsw(r8, r11, r30, Assembler::LSL, 13); // adds w8, w11, w30, LSL #13 + __ subsw(r0, r25, r19, Assembler::LSL, 9); // subs w0, w25, w19, LSL #9 + __ andr(r20, r0, r21, Assembler::LSL, 19); // and x20, x0, x21, LSL #19 + __ orr(r21, r14, r20, Assembler::LSL, 17); // orr x21, x14, x20, LSL #17 + __ eor(r25, r28, r1, Assembler::LSL, 51); // eor x25, x28, x1, LSL #51 + __ ands(r10, r27, r11, Assembler::ASR, 15); // ands x10, x27, x11, ASR #15 + __ andw(r25, r5, r12, Assembler::ASR, 23); // and w25, w5, w12, ASR #23 + __ orrw(r18, r14, r10, Assembler::LSR, 4); // orr w18, w14, w10, LSR #4 + __ eorw(r4, r21, r5, Assembler::ASR, 22); // eor w4, w21, w5, ASR #22 + __ andsw(r21, r0, r5, Assembler::ASR, 29); // ands w21, w0, w5, ASR #29 + __ bic(r26, r30, r6, Assembler::ASR, 37); // bic x26, x30, x6, ASR #37 + __ orn(r3, r1, r13, Assembler::LSR, 29); // orn x3, x1, x13, LSR #29 + __ eon(r0, r28, r9, Assembler::LSL, 47); // eon x0, x28, x9, LSL #47 + __ bics(r29, r5, r28, Assembler::LSL, 46); // bics x29, x5, x28, LSL #46 + __ bicw(r9, r18, r7, Assembler::LSR, 20); // bic w9, w18, w7, LSR #20 + __ ornw(r26, r13, r25, Assembler::ASR, 24); // orn w26, w13, w25, ASR #24 + __ eonw(r25, r4, r19, Assembler::LSL, 6); // eon w25, w4, w19, LSL #6 + __ bicsw(r5, r26, r4, Assembler::LSR, 24); // bics w5, w26, w4, LSR #24 // AddSubImmOp - __ addw(r7, r19, 340u); // add w7, w19, #340 - __ addsw(r8, r0, 401u); // adds w8, w0, #401 - __ subw(r29, r20, 163u); // sub w29, w20, #163 - __ subsw(r8, r23, 759u); // subs w8, w23, #759 - __ add(r1, r12, 523u); // add x1, x12, #523 - __ adds(r2, r11, 426u); // adds x2, x11, #426 - __ sub(r14, r29, 716u); // sub x14, x29, #716 - __ subs(r11, r5, 582u); // subs x11, x5, #582 + __ addw(r7, r19, 340u); // add w7, w19, #340 + __ addsw(r8, r0, 401u); // adds w8, w0, #401 + __ subw(r29, r20, 163u); // sub w29, w20, #163 + __ subsw(r8, r23, 759u); // subs w8, w23, #759 + __ add(r1, r12, 523u); // add x1, x12, #523 + __ adds(r2, r11, 426u); // adds x2, x11, #426 + __ sub(r14, r29, 716u); // sub x14, x29, #716 + __ subs(r11, r5, 582u); // subs x11, x5, #582 // LogicalImmOp - __ andw(r23, r22, 32768ul); // and w23, w22, #0x8000 - __ orrw(r4, r10, 4042322160ul); // orr w4, w10, #0xf0f0f0f0 - __ eorw(r0, r24, 4042322160ul); // eor w0, w24, #0xf0f0f0f0 - __ andsw(r19, r29, 2139127680ul); // ands w19, w29, #0x7f807f80 - __ andr(r5, r10, 4503599627354112ul); // and x5, x10, #0xfffffffffc000 - __ orr(r12, r30, 18445618178097414144ul); // orr x12, x30, #0xfffc0000fffc0000 - __ eor(r30, r5, 262128ul); // eor x30, x5, #0x3fff0 - __ ands(r26, r23, 4194300ul); // ands x26, x23, #0x3ffffc + __ andw(r23, r22, 32768ul); // and w23, w22, #0x8000 + __ orrw(r4, r10, 4042322160ul); // orr w4, w10, #0xf0f0f0f0 + __ eorw(r0, r24, 4042322160ul); // eor w0, w24, #0xf0f0f0f0 + __ andsw(r19, r29, 2139127680ul); // ands w19, w29, #0x7f807f80 + __ andr(r5, r10, 4503599627354112ul); // and x5, x10, #0xfffffffffc000 + __ orr(r12, r30, 18445618178097414144ul); // orr x12, x30, #0xfffc0000fffc0000 + __ eor(r30, r5, 262128ul); // eor x30, x5, #0x3fff0 + __ ands(r26, r23, 4194300ul); // ands x26, x23, #0x3ffffc // AbsOp - __ b(__ pc()); // b . - __ b(back); // b back - __ b(forth); // b forth - __ bl(__ pc()); // bl . - __ bl(back); // bl back - __ bl(forth); // bl forth + __ b(__ pc()); // b . + __ b(back); // b back + __ b(forth); // b forth + __ bl(__ pc()); // bl . + __ bl(back); // bl back + __ bl(forth); // bl forth // RegAndAbsOp - __ cbzw(r12, __ pc()); // cbz w12, . - __ cbzw(r12, back); // cbz w12, back - __ cbzw(r12, forth); // cbz w12, forth - __ cbnzw(r20, __ pc()); // cbnz w20, . - __ cbnzw(r20, back); // cbnz w20, back - __ cbnzw(r20, forth); // cbnz w20, forth - __ cbz(r12, __ pc()); // cbz x12, . - __ cbz(r12, back); // cbz x12, back - __ cbz(r12, forth); // cbz x12, forth - __ cbnz(r24, __ pc()); // cbnz x24, . - __ cbnz(r24, back); // cbnz x24, back - __ cbnz(r24, forth); // cbnz x24, forth - __ adr(r6, __ pc()); // adr x6, . - __ adr(r6, back); // adr x6, back - __ adr(r6, forth); // adr x6, forth - __ _adrp(r21, __ pc()); // adrp x21, . + __ cbzw(r12, __ pc()); // cbz w12, . + __ cbzw(r12, back); // cbz w12, back + __ cbzw(r12, forth); // cbz w12, forth + __ cbnzw(r20, __ pc()); // cbnz w20, . + __ cbnzw(r20, back); // cbnz w20, back + __ cbnzw(r20, forth); // cbnz w20, forth + __ cbz(r12, __ pc()); // cbz x12, . + __ cbz(r12, back); // cbz x12, back + __ cbz(r12, forth); // cbz x12, forth + __ cbnz(r24, __ pc()); // cbnz x24, . + __ cbnz(r24, back); // cbnz x24, back + __ cbnz(r24, forth); // cbnz x24, forth + __ adr(r6, __ pc()); // adr x6, . + __ adr(r6, back); // adr x6, back + __ adr(r6, forth); // adr x6, forth + __ _adrp(r21, __ pc()); // adrp x21, . // RegImmAbsOp - __ tbz(r1, 1, __ pc()); // tbz x1, #1, . - __ tbz(r1, 1, back); // tbz x1, #1, back - __ tbz(r1, 1, forth); // tbz x1, #1, forth - __ tbnz(r8, 9, __ pc()); // tbnz x8, #9, . - __ tbnz(r8, 9, back); // tbnz x8, #9, back - __ tbnz(r8, 9, forth); // tbnz x8, #9, forth + __ tbz(r1, 1, __ pc()); // tbz x1, #1, . + __ tbz(r1, 1, back); // tbz x1, #1, back + __ tbz(r1, 1, forth); // tbz x1, #1, forth + __ tbnz(r8, 9, __ pc()); // tbnz x8, #9, . + __ tbnz(r8, 9, back); // tbnz x8, #9, back + __ tbnz(r8, 9, forth); // tbnz x8, #9, forth // MoveWideImmOp - __ movnw(r12, 23175, 0); // movn w12, #23175, lsl 0 - __ movzw(r11, 20476, 16); // movz w11, #20476, lsl 16 - __ movkw(r21, 3716, 0); // movk w21, #3716, lsl 0 - __ movn(r29, 28661, 48); // movn x29, #28661, lsl 48 - __ movz(r3, 6927, 0); // movz x3, #6927, lsl 0 - __ movk(r22, 9828, 16); // movk x22, #9828, lsl 16 + __ movnw(r12, 23175, 0); // movn w12, #23175, lsl 0 + __ movzw(r11, 20476, 16); // movz w11, #20476, lsl 16 + __ movkw(r21, 3716, 0); // movk w21, #3716, lsl 0 + __ movn(r29, 28661, 48); // movn x29, #28661, lsl 48 + __ movz(r3, 6927, 0); // movz x3, #6927, lsl 0 + __ movk(r22, 9828, 16); // movk x22, #9828, lsl 16 // BitfieldOp - __ sbfm(r12, r8, 6, 22); // sbfm x12, x8, #6, #22 - __ bfmw(r19, r25, 25, 19); // bfm w19, w25, #25, #19 - __ ubfmw(r9, r12, 29, 15); // ubfm w9, w12, #29, #15 - __ sbfm(r28, r25, 16, 16); // sbfm x28, x25, #16, #16 - __ bfm(r12, r5, 4, 25); // bfm x12, x5, #4, #25 - __ ubfm(r0, r10, 6, 8); // ubfm x0, x10, #6, #8 + __ sbfm(r12, r8, 6, 22); // sbfm x12, x8, #6, #22 + __ bfmw(r19, r25, 25, 19); // bfm w19, w25, #25, #19 + __ ubfmw(r9, r12, 29, 15); // ubfm w9, w12, #29, #15 + __ sbfm(r28, r25, 16, 16); // sbfm x28, x25, #16, #16 + __ bfm(r12, r5, 4, 25); // bfm x12, x5, #4, #25 + __ ubfm(r0, r10, 6, 8); // ubfm x0, x10, #6, #8 // ExtractOp - __ extrw(r4, r13, r26, 24); // extr w4, w13, w26, #24 - __ extr(r23, r30, r24, 31); // extr x23, x30, x24, #31 + __ extrw(r4, r13, r26, 24); // extr w4, w13, w26, #24 + __ extr(r23, r30, r24, 31); // extr x23, x30, x24, #31 // CondBranchOp - __ br(Assembler::EQ, __ pc()); // b.EQ . - __ br(Assembler::EQ, back); // b.EQ back - __ br(Assembler::EQ, forth); // b.EQ forth - __ br(Assembler::NE, __ pc()); // b.NE . - __ br(Assembler::NE, back); // b.NE back - __ br(Assembler::NE, forth); // b.NE forth - __ br(Assembler::HS, __ pc()); // b.HS . - __ br(Assembler::HS, back); // b.HS back - __ br(Assembler::HS, forth); // b.HS forth - __ br(Assembler::CS, __ pc()); // b.CS . - __ br(Assembler::CS, back); // b.CS back - __ br(Assembler::CS, forth); // b.CS forth - __ br(Assembler::LO, __ pc()); // b.LO . - __ br(Assembler::LO, back); // b.LO back - __ br(Assembler::LO, forth); // b.LO forth - __ br(Assembler::CC, __ pc()); // b.CC . - __ br(Assembler::CC, back); // b.CC back - __ br(Assembler::CC, forth); // b.CC forth - __ br(Assembler::MI, __ pc()); // b.MI . - __ br(Assembler::MI, back); // b.MI back - __ br(Assembler::MI, forth); // b.MI forth - __ br(Assembler::PL, __ pc()); // b.PL . - __ br(Assembler::PL, back); // b.PL back - __ br(Assembler::PL, forth); // b.PL forth - __ br(Assembler::VS, __ pc()); // b.VS . - __ br(Assembler::VS, back); // b.VS back - __ br(Assembler::VS, forth); // b.VS forth - __ br(Assembler::VC, __ pc()); // b.VC . - __ br(Assembler::VC, back); // b.VC back - __ br(Assembler::VC, forth); // b.VC forth - __ br(Assembler::HI, __ pc()); // b.HI . - __ br(Assembler::HI, back); // b.HI back - __ br(Assembler::HI, forth); // b.HI forth - __ br(Assembler::LS, __ pc()); // b.LS . - __ br(Assembler::LS, back); // b.LS back - __ br(Assembler::LS, forth); // b.LS forth - __ br(Assembler::GE, __ pc()); // b.GE . - __ br(Assembler::GE, back); // b.GE back - __ br(Assembler::GE, forth); // b.GE forth - __ br(Assembler::LT, __ pc()); // b.LT . - __ br(Assembler::LT, back); // b.LT back - __ br(Assembler::LT, forth); // b.LT forth - __ br(Assembler::GT, __ pc()); // b.GT . - __ br(Assembler::GT, back); // b.GT back - __ br(Assembler::GT, forth); // b.GT forth - __ br(Assembler::LE, __ pc()); // b.LE . - __ br(Assembler::LE, back); // b.LE back - __ br(Assembler::LE, forth); // b.LE forth - __ br(Assembler::AL, __ pc()); // b.AL . - __ br(Assembler::AL, back); // b.AL back - __ br(Assembler::AL, forth); // b.AL forth - __ br(Assembler::NV, __ pc()); // b.NV . - __ br(Assembler::NV, back); // b.NV back - __ br(Assembler::NV, forth); // b.NV forth + __ br(Assembler::EQ, __ pc()); // b.EQ . + __ br(Assembler::EQ, back); // b.EQ back + __ br(Assembler::EQ, forth); // b.EQ forth + __ br(Assembler::NE, __ pc()); // b.NE . + __ br(Assembler::NE, back); // b.NE back + __ br(Assembler::NE, forth); // b.NE forth + __ br(Assembler::HS, __ pc()); // b.HS . + __ br(Assembler::HS, back); // b.HS back + __ br(Assembler::HS, forth); // b.HS forth + __ br(Assembler::CS, __ pc()); // b.CS . + __ br(Assembler::CS, back); // b.CS back + __ br(Assembler::CS, forth); // b.CS forth + __ br(Assembler::LO, __ pc()); // b.LO . + __ br(Assembler::LO, back); // b.LO back + __ br(Assembler::LO, forth); // b.LO forth + __ br(Assembler::CC, __ pc()); // b.CC . + __ br(Assembler::CC, back); // b.CC back + __ br(Assembler::CC, forth); // b.CC forth + __ br(Assembler::MI, __ pc()); // b.MI . + __ br(Assembler::MI, back); // b.MI back + __ br(Assembler::MI, forth); // b.MI forth + __ br(Assembler::PL, __ pc()); // b.PL . + __ br(Assembler::PL, back); // b.PL back + __ br(Assembler::PL, forth); // b.PL forth + __ br(Assembler::VS, __ pc()); // b.VS . + __ br(Assembler::VS, back); // b.VS back + __ br(Assembler::VS, forth); // b.VS forth + __ br(Assembler::VC, __ pc()); // b.VC . + __ br(Assembler::VC, back); // b.VC back + __ br(Assembler::VC, forth); // b.VC forth + __ br(Assembler::HI, __ pc()); // b.HI . + __ br(Assembler::HI, back); // b.HI back + __ br(Assembler::HI, forth); // b.HI forth + __ br(Assembler::LS, __ pc()); // b.LS . + __ br(Assembler::LS, back); // b.LS back + __ br(Assembler::LS, forth); // b.LS forth + __ br(Assembler::GE, __ pc()); // b.GE . + __ br(Assembler::GE, back); // b.GE back + __ br(Assembler::GE, forth); // b.GE forth + __ br(Assembler::LT, __ pc()); // b.LT . + __ br(Assembler::LT, back); // b.LT back + __ br(Assembler::LT, forth); // b.LT forth + __ br(Assembler::GT, __ pc()); // b.GT . + __ br(Assembler::GT, back); // b.GT back + __ br(Assembler::GT, forth); // b.GT forth + __ br(Assembler::LE, __ pc()); // b.LE . + __ br(Assembler::LE, back); // b.LE back + __ br(Assembler::LE, forth); // b.LE forth + __ br(Assembler::AL, __ pc()); // b.AL . + __ br(Assembler::AL, back); // b.AL back + __ br(Assembler::AL, forth); // b.AL forth + __ br(Assembler::NV, __ pc()); // b.NV . + __ br(Assembler::NV, back); // b.NV back + __ br(Assembler::NV, forth); // b.NV forth // ImmOp - __ svc(12729); // svc #12729 - __ hvc(6788); // hvc #6788 - __ smc(1535); // smc #1535 - __ brk(16766); // brk #16766 - __ hlt(9753); // hlt #9753 + __ svc(12729); // svc #12729 + __ hvc(6788); // hvc #6788 + __ smc(1535); // smc #1535 + __ brk(16766); // brk #16766 + __ hlt(9753); // hlt #9753 // Op - __ nop(); // nop - __ eret(); // eret - __ drps(); // drps - __ isb(); // isb + __ nop(); // nop + __ eret(); // eret + __ drps(); // drps + __ isb(); // isb // SystemOp - __ dsb(Assembler::SY); // dsb SY - __ dmb(Assembler::ISHST); // dmb ISHST + __ dsb(Assembler::SY); // dsb SY + __ dmb(Assembler::ISHST); // dmb ISHST // OneRegOp - __ br(r2); // br x2 - __ blr(r5); // blr x5 + __ br(r2); // br x2 + __ blr(r5); // blr x5 // LoadStoreExclusiveOp - __ stxr(r20, r21, r2); // stxr w20, x21, [x2] + __ stxr(r20, r21, r2); // stxr w20, x21, [x2] __ stlxr(r5, r29, r7); // stlxr w5, x29, [x7] - __ ldxr(r5, r16); // ldxr x5, [x16] - __ ldaxr(r27, r29); // ldaxr x27, [x29] - __ stlr(r0, r29); // stlr x0, [x29] - __ ldar(r21, r28); // ldar x21, [x28] + __ ldxr(r5, r16); // ldxr x5, [x16] + __ ldaxr(r27, r29); // ldaxr x27, [x29] + __ stlr(r0, r29); // stlr x0, [x29] + __ ldar(r21, r28); // ldar x21, [x28] // LoadStoreExclusiveOp __ stxrw(r21, r24, r7); // stxr w21, w24, [x7] - __ stlxrw(r21, r26, r28); // stlxr w21, w26, [x28] - __ ldxrw(r21, r6); // ldxr w21, [x6] - __ ldaxrw(r15, r30); // ldaxr w15, [x30] - __ stlrw(r19, r3); // stlr w19, [x3] - __ ldarw(r22, r2); // ldar w22, [x2] + __ stlxrw(r21, r26, r28); // stlxr w21, w26, [x28] + __ ldxrw(r21, r6); // ldxr w21, [x6] + __ ldaxrw(r15, r30); // ldaxr w15, [x30] + __ stlrw(r19, r3); // stlr w19, [x3] + __ ldarw(r22, r2); // ldar w22, [x2] // LoadStoreExclusiveOp - __ stxrh(r18, r15, r0); // stxrh w18, w15, [x0] - __ stlxrh(r11, r5, r28); // stlxrh w11, w5, [x28] - __ ldxrh(r29, r6); // ldxrh w29, [x6] - __ ldaxrh(r18, r7); // ldaxrh w18, [x7] - __ stlrh(r25, r28); // stlrh w25, [x28] - __ ldarh(r2, r19); // ldarh w2, [x19] + __ stxrh(r18, r15, r0); // stxrh w18, w15, [x0] + __ stlxrh(r11, r5, r28); // stlxrh w11, w5, [x28] + __ ldxrh(r29, r6); // ldxrh w29, [x6] + __ ldaxrh(r18, r7); // ldaxrh w18, [x7] + __ stlrh(r25, r28); // stlrh w25, [x28] + __ ldarh(r2, r19); // ldarh w2, [x19] // LoadStoreExclusiveOp - __ stxrb(r10, r30, r1); // stxrb w10, w30, [x1] - __ stlxrb(r20, r21, r22); // stlxrb w20, w21, [x22] - __ ldxrb(r25, r2); // ldxrb w25, [x2] - __ ldaxrb(r24, r5); // ldaxrb w24, [x5] - __ stlrb(r16, r3); // stlrb w16, [x3] - __ ldarb(r22, r29); // ldarb w22, [x29] + __ stxrb(r10, r30, r1); // stxrb w10, w30, [x1] + __ stlxrb(r20, r21, r22); // stlxrb w20, w21, [x22] + __ ldxrb(r25, r2); // ldxrb w25, [x2] + __ ldaxrb(r24, r5); // ldaxrb w24, [x5] + __ stlrb(r16, r3); // stlrb w16, [x3] + __ ldarb(r22, r29); // ldarb w22, [x29] // LoadStoreExclusiveOp - __ ldxp(r8, r2, r19); // ldxp x8, x2, [x19] - __ ldaxp(r7, r19, r14); // ldaxp x7, x19, [x14] - __ stxp(r8, r27, r28, r5); // stxp w8, x27, x28, [x5] + __ ldxp(r8, r2, r19); // ldxp x8, x2, [x19] + __ ldaxp(r7, r19, r14); // ldaxp x7, x19, [x14] + __ stxp(r8, r27, r28, r5); // stxp w8, x27, x28, [x5] __ stlxp(r5, r8, r14, r6); // stlxp w5, x8, x14, [x6] // LoadStoreExclusiveOp - __ ldxpw(r25, r4, r22); // ldxp w25, w4, [x22] + __ ldxpw(r25, r4, r22); // ldxp w25, w4, [x22] __ ldaxpw(r13, r14, r15); // ldaxp w13, w14, [x15] - __ stxpw(r20, r26, r8, r10); // stxp w20, w26, w8, [x10] - __ stlxpw(r23, r18, r18, r18); // stlxp w23, w18, w18, [x18] + __ stxpw(r20, r26, r8, r10); // stxp w20, w26, w8, [x10] + __ stlxpw(r23, r18, r18, r18); // stlxp w23, w18, w18, [x18] -// base_plus_unscaled_offset +// base_plus_unscaled_offset // LoadStoreOp - __ str(r30, Address(r11, 99)); // str x30, [x11, 99] - __ strw(r23, Address(r25, -77)); // str w23, [x25, -77] - __ strb(r2, Address(r14, 3)); // strb w2, [x14, 3] - __ strh(r9, Address(r10, 5)); // strh w9, [x10, 5] - __ ldr(r20, Address(r15, 57)); // ldr x20, [x15, 57] - __ ldrw(r12, Address(r16, -78)); // ldr w12, [x16, -78] - __ ldrb(r22, Address(r26, -3)); // ldrb w22, [x26, -3] - __ ldrh(r30, Address(r19, -47)); // ldrh w30, [x19, -47] - __ ldrsb(r9, Address(r10, -12)); // ldrsb x9, [x10, -12] - __ ldrsh(r28, Address(r17, 14)); // ldrsh x28, [x17, 14] - __ ldrshw(r3, Address(r5, 10)); // ldrsh w3, [x5, 10] - __ ldrsw(r17, Address(r17, -91)); // ldrsw x17, [x17, -91] - __ ldrd(v2, Address(r20, -17)); // ldr d2, [x20, -17] - __ ldrs(v22, Address(r7, -10)); // ldr s22, [x7, -10] - __ strd(v30, Address(r18, -223)); // str d30, [x18, -223] - __ strs(v13, Address(r22, 21)); // str s13, [x22, 21] + __ str(r30, Address(r11, 99)); // str x30, [x11, 99] + __ strw(r23, Address(r25, -77)); // str w23, [x25, -77] + __ strb(r2, Address(r14, 3)); // strb w2, [x14, 3] + __ strh(r9, Address(r10, 5)); // strh w9, [x10, 5] + __ ldr(r20, Address(r15, 57)); // ldr x20, [x15, 57] + __ ldrw(r12, Address(r16, -78)); // ldr w12, [x16, -78] + __ ldrb(r22, Address(r26, -3)); // ldrb w22, [x26, -3] + __ ldrh(r30, Address(r19, -47)); // ldrh w30, [x19, -47] + __ ldrsb(r9, Address(r10, -12)); // ldrsb x9, [x10, -12] + __ ldrsh(r28, Address(r17, 14)); // ldrsh x28, [x17, 14] + __ ldrshw(r3, Address(r5, 10)); // ldrsh w3, [x5, 10] + __ ldrsw(r17, Address(r17, -91)); // ldrsw x17, [x17, -91] + __ ldrd(v2, Address(r20, -17)); // ldr d2, [x20, -17] + __ ldrs(v22, Address(r7, -10)); // ldr s22, [x7, -10] + __ strd(v30, Address(r18, -223)); // str d30, [x18, -223] + __ strs(v13, Address(r22, 21)); // str s13, [x22, 21] -// pre +// pre // LoadStoreOp - __ str(r9, Address(__ pre(r18, -112))); // str x9, [x18, -112]! - __ strw(r29, Address(__ pre(r23, 11))); // str w29, [x23, 11]! - __ strb(r18, Address(__ pre(r12, -1))); // strb w18, [x12, -1]! - __ strh(r16, Address(__ pre(r20, -23))); // strh w16, [x20, -23]! - __ ldr(r3, Address(__ pre(r29, 9))); // ldr x3, [x29, 9]! - __ ldrw(r25, Address(__ pre(r3, 19))); // ldr w25, [x3, 19]! - __ ldrb(r1, Address(__ pre(r29, -1))); // ldrb w1, [x29, -1]! - __ ldrh(r8, Address(__ pre(r29, -57))); // ldrh w8, [x29, -57]! - __ ldrsb(r5, Address(__ pre(r14, -13))); // ldrsb x5, [x14, -13]! - __ ldrsh(r10, Address(__ pre(r27, 1))); // ldrsh x10, [x27, 1]! - __ ldrshw(r11, Address(__ pre(r10, 25))); // ldrsh w11, [x10, 25]! - __ ldrsw(r4, Address(__ pre(r22, -92))); // ldrsw x4, [x22, -92]! - __ ldrd(v11, Address(__ pre(r23, 8))); // ldr d11, [x23, 8]! - __ ldrs(v25, Address(__ pre(r19, 54))); // ldr s25, [x19, 54]! - __ strd(v1, Address(__ pre(r7, -174))); // str d1, [x7, -174]! - __ strs(v8, Address(__ pre(r25, 54))); // str s8, [x25, 54]! + __ str(r9, Address(__ pre(r18, -112))); // str x9, [x18, -112]! + __ strw(r29, Address(__ pre(r23, 11))); // str w29, [x23, 11]! + __ strb(r18, Address(__ pre(r12, -1))); // strb w18, [x12, -1]! + __ strh(r16, Address(__ pre(r20, -23))); // strh w16, [x20, -23]! + __ ldr(r3, Address(__ pre(r29, 9))); // ldr x3, [x29, 9]! + __ ldrw(r25, Address(__ pre(r3, 19))); // ldr w25, [x3, 19]! + __ ldrb(r1, Address(__ pre(r29, -1))); // ldrb w1, [x29, -1]! + __ ldrh(r8, Address(__ pre(r29, -57))); // ldrh w8, [x29, -57]! + __ ldrsb(r5, Address(__ pre(r14, -13))); // ldrsb x5, [x14, -13]! + __ ldrsh(r10, Address(__ pre(r27, 1))); // ldrsh x10, [x27, 1]! + __ ldrshw(r11, Address(__ pre(r10, 25))); // ldrsh w11, [x10, 25]! + __ ldrsw(r4, Address(__ pre(r22, -92))); // ldrsw x4, [x22, -92]! + __ ldrd(v11, Address(__ pre(r23, 8))); // ldr d11, [x23, 8]! + __ ldrs(v25, Address(__ pre(r19, 54))); // ldr s25, [x19, 54]! + __ strd(v1, Address(__ pre(r7, -174))); // str d1, [x7, -174]! + __ strs(v8, Address(__ pre(r25, 54))); // str s8, [x25, 54]! -// post +// post // LoadStoreOp - __ str(r5, Address(__ post(r11, 37))); // str x5, [x11], 37 - __ strw(r24, Address(__ post(r15, 19))); // str w24, [x15], 19 - __ strb(r15, Address(__ post(r26, -1))); // strb w15, [x26], -1 - __ strh(r18, Address(__ post(r18, -6))); // strh w18, [x18], -6 - __ ldr(r7, Address(__ post(r2, -230))); // ldr x7, [x2], -230 - __ ldrw(r27, Address(__ post(r11, -27))); // ldr w27, [x11], -27 - __ ldrb(r18, Address(__ post(r3, -25))); // ldrb w18, [x3], -25 - __ ldrh(r10, Address(__ post(r24, -32))); // ldrh w10, [x24], -32 - __ ldrsb(r22, Address(__ post(r10, 4))); // ldrsb x22, [x10], 4 - __ ldrsh(r17, Address(__ post(r12, 25))); // ldrsh x17, [x12], 25 - __ ldrshw(r8, Address(__ post(r7, -62))); // ldrsh w8, [x7], -62 - __ ldrsw(r23, Address(__ post(r22, -51))); // ldrsw x23, [x22], -51 - __ ldrd(v24, Address(__ post(r25, 48))); // ldr d24, [x25], 48 - __ ldrs(v21, Address(__ post(r12, -10))); // ldr s21, [x12], -10 - __ strd(v18, Address(__ post(r13, -222))); // str d18, [x13], -222 - __ strs(v16, Address(__ post(r1, -41))); // str s16, [x1], -41 + __ str(r5, Address(__ post(r11, 37))); // str x5, [x11], 37 + __ strw(r24, Address(__ post(r15, 19))); // str w24, [x15], 19 + __ strb(r15, Address(__ post(r26, -1))); // strb w15, [x26], -1 + __ strh(r18, Address(__ post(r18, -6))); // strh w18, [x18], -6 + __ ldr(r7, Address(__ post(r2, -230))); // ldr x7, [x2], -230 + __ ldrw(r27, Address(__ post(r11, -27))); // ldr w27, [x11], -27 + __ ldrb(r18, Address(__ post(r3, -25))); // ldrb w18, [x3], -25 + __ ldrh(r10, Address(__ post(r24, -32))); // ldrh w10, [x24], -32 + __ ldrsb(r22, Address(__ post(r10, 4))); // ldrsb x22, [x10], 4 + __ ldrsh(r17, Address(__ post(r12, 25))); // ldrsh x17, [x12], 25 + __ ldrshw(r8, Address(__ post(r7, -62))); // ldrsh w8, [x7], -62 + __ ldrsw(r23, Address(__ post(r22, -51))); // ldrsw x23, [x22], -51 + __ ldrd(v24, Address(__ post(r25, 48))); // ldr d24, [x25], 48 + __ ldrs(v21, Address(__ post(r12, -10))); // ldr s21, [x12], -10 + __ strd(v18, Address(__ post(r13, -222))); // str d18, [x13], -222 + __ strs(v16, Address(__ post(r1, -41))); // str s16, [x1], -41 -// base_plus_reg +// base_plus_reg // LoadStoreOp - __ str(r2, Address(r22, r15, Address::sxtw(0))); // str x2, [x22, w15, sxtw #0] - __ strw(r2, Address(r16, r29, Address::lsl(0))); // str w2, [x16, x29, lsl #0] - __ strb(r20, Address(r18, r14, Address::uxtw(0))); // strb w20, [x18, w14, uxtw #0] - __ strh(r6, Address(r19, r20, Address::sxtx(1))); // strh w6, [x19, x20, sxtx #1] - __ ldr(r14, Address(r29, r14, Address::sxtw(0))); // ldr x14, [x29, w14, sxtw #0] - __ ldrw(r16, Address(r20, r12, Address::sxtw(2))); // ldr w16, [x20, w12, sxtw #2] - __ ldrb(r9, Address(r12, r0, Address::sxtw(0))); // ldrb w9, [x12, w0, sxtw #0] - __ ldrh(r12, Address(r17, r3, Address::lsl(1))); // ldrh w12, [x17, x3, lsl #1] - __ ldrsb(r2, Address(r17, r3, Address::sxtx(0))); // ldrsb x2, [x17, x3, sxtx #0] - __ ldrsh(r7, Address(r1, r17, Address::uxtw(1))); // ldrsh x7, [x1, w17, uxtw #1] - __ ldrshw(r25, Address(r15, r18, Address::sxtw(1))); // ldrsh w25, [x15, w18, sxtw #1] - __ ldrsw(r23, Address(r21, r12, Address::lsl(0))); // ldrsw x23, [x21, x12, lsl #0] - __ ldrd(v5, Address(r13, r8, Address::lsl(3))); // ldr d5, [x13, x8, lsl #3] - __ ldrs(v3, Address(r10, r22, Address::lsl(2))); // ldr s3, [x10, x22, lsl #2] - __ strd(v14, Address(r2, r27, Address::sxtw(0))); // str d14, [x2, w27, sxtw #0] - __ strs(v20, Address(r6, r25, Address::lsl(0))); // str s20, [x6, x25, lsl #0] + __ str(r2, Address(r22, r15, Address::sxtw(0))); // str x2, [x22, w15, sxtw #0] + __ strw(r2, Address(r16, r29, Address::lsl(0))); // str w2, [x16, x29, lsl #0] + __ strb(r20, Address(r18, r14, Address::uxtw(0))); // strb w20, [x18, w14, uxtw #0] + __ strh(r6, Address(r19, r20, Address::sxtx(1))); // strh w6, [x19, x20, sxtx #1] + __ ldr(r14, Address(r29, r14, Address::sxtw(0))); // ldr x14, [x29, w14, sxtw #0] + __ ldrw(r16, Address(r20, r12, Address::sxtw(2))); // ldr w16, [x20, w12, sxtw #2] + __ ldrb(r9, Address(r12, r0, Address::sxtw(0))); // ldrb w9, [x12, w0, sxtw #0] + __ ldrh(r12, Address(r17, r3, Address::lsl(1))); // ldrh w12, [x17, x3, lsl #1] + __ ldrsb(r2, Address(r17, r3, Address::sxtx(0))); // ldrsb x2, [x17, x3, sxtx #0] + __ ldrsh(r7, Address(r1, r17, Address::uxtw(1))); // ldrsh x7, [x1, w17, uxtw #1] + __ ldrshw(r25, Address(r15, r18, Address::sxtw(1))); // ldrsh w25, [x15, w18, sxtw #1] + __ ldrsw(r23, Address(r21, r12, Address::lsl(0))); // ldrsw x23, [x21, x12, lsl #0] + __ ldrd(v5, Address(r13, r8, Address::lsl(3))); // ldr d5, [x13, x8, lsl #3] + __ ldrs(v3, Address(r10, r22, Address::lsl(2))); // ldr s3, [x10, x22, lsl #2] + __ strd(v14, Address(r2, r27, Address::sxtw(0))); // str d14, [x2, w27, sxtw #0] + __ strs(v20, Address(r6, r25, Address::lsl(0))); // str s20, [x6, x25, lsl #0] -// base_plus_scaled_offset +// base_plus_scaled_offset // LoadStoreOp - __ str(r30, Address(r7, 16256)); // str x30, [x7, 16256] - __ strw(r15, Address(r8, 7588)); // str w15, [x8, 7588] - __ strb(r11, Address(r0, 1866)); // strb w11, [x0, 1866] - __ strh(r3, Address(r17, 3734)); // strh w3, [x17, 3734] - __ ldr(r2, Address(r7, 14224)); // ldr x2, [x7, 14224] - __ ldrw(r5, Address(r9, 7396)); // ldr w5, [x9, 7396] - __ ldrb(r28, Address(r9, 1721)); // ldrb w28, [x9, 1721] - __ ldrh(r2, Address(r20, 3656)); // ldrh w2, [x20, 3656] - __ ldrsb(r22, Address(r14, 1887)); // ldrsb x22, [x14, 1887] - __ ldrsh(r8, Address(r0, 4080)); // ldrsh x8, [x0, 4080] - __ ldrshw(r0, Address(r30, 3916)); // ldrsh w0, [x30, 3916] - __ ldrsw(r24, Address(r19, 6828)); // ldrsw x24, [x19, 6828] - __ ldrd(v24, Address(r12, 13032)); // ldr d24, [x12, 13032] - __ ldrs(v8, Address(r8, 7452)); // ldr s8, [x8, 7452] - __ strd(v10, Address(r15, 15992)); // str d10, [x15, 15992] - __ strs(v26, Address(r19, 6688)); // str s26, [x19, 6688] + __ str(r30, Address(r7, 16256)); // str x30, [x7, 16256] + __ strw(r15, Address(r8, 7588)); // str w15, [x8, 7588] + __ strb(r11, Address(r0, 1866)); // strb w11, [x0, 1866] + __ strh(r3, Address(r17, 3734)); // strh w3, [x17, 3734] + __ ldr(r2, Address(r7, 14224)); // ldr x2, [x7, 14224] + __ ldrw(r5, Address(r9, 7396)); // ldr w5, [x9, 7396] + __ ldrb(r28, Address(r9, 1721)); // ldrb w28, [x9, 1721] + __ ldrh(r2, Address(r20, 3656)); // ldrh w2, [x20, 3656] + __ ldrsb(r22, Address(r14, 1887)); // ldrsb x22, [x14, 1887] + __ ldrsh(r8, Address(r0, 4080)); // ldrsh x8, [x0, 4080] + __ ldrshw(r0, Address(r30, 3916)); // ldrsh w0, [x30, 3916] + __ ldrsw(r24, Address(r19, 6828)); // ldrsw x24, [x19, 6828] + __ ldrd(v24, Address(r12, 13032)); // ldr d24, [x12, 13032] + __ ldrs(v8, Address(r8, 7452)); // ldr s8, [x8, 7452] + __ strd(v10, Address(r15, 15992)); // str d10, [x15, 15992] + __ strs(v26, Address(r19, 6688)); // str s26, [x19, 6688] -// pcrel +// pcrel // LoadStoreOp - __ ldr(r10, forth); // ldr x10, forth - __ ldrw(r3, __ pc()); // ldr w3, . + __ ldr(r10, forth); // ldr x10, forth + __ ldrw(r3, __ pc()); // ldr w3, . // LoadStoreOp - __ prfm(Address(r23, 9)); // prfm PLDL1KEEP, [x23, 9] + __ prfm(Address(r23, 9)); // prfm PLDL1KEEP, [x23, 9] // LoadStoreOp - __ prfm(back); // prfm PLDL1KEEP, back + __ prfm(back); // prfm PLDL1KEEP, back // LoadStoreOp - __ prfm(Address(r3, r8, Address::uxtw(0))); // prfm PLDL1KEEP, [x3, w8, uxtw #0] + __ prfm(Address(r3, r8, Address::uxtw(0))); // prfm PLDL1KEEP, [x3, w8, uxtw #0] // LoadStoreOp - __ prfm(Address(r11, 15080)); // prfm PLDL1KEEP, [x11, 15080] + __ prfm(Address(r11, 15080)); // prfm PLDL1KEEP, [x11, 15080] // AddSubCarryOp - __ adcw(r13, r9, r28); // adc w13, w9, w28 - __ adcsw(r27, r19, r28); // adcs w27, w19, w28 - __ sbcw(r19, r18, r6); // sbc w19, w18, w6 - __ sbcsw(r14, r20, r3); // sbcs w14, w20, w3 - __ adc(r16, r14, r8); // adc x16, x14, x8 - __ adcs(r0, r29, r8); // adcs x0, x29, x8 - __ sbc(r8, r24, r20); // sbc x8, x24, x20 - __ sbcs(r12, r28, r0); // sbcs x12, x28, x0 + __ adcw(r13, r9, r28); // adc w13, w9, w28 + __ adcsw(r27, r19, r28); // adcs w27, w19, w28 + __ sbcw(r19, r18, r6); // sbc w19, w18, w6 + __ sbcsw(r14, r20, r3); // sbcs w14, w20, w3 + __ adc(r16, r14, r8); // adc x16, x14, x8 + __ adcs(r0, r29, r8); // adcs x0, x29, x8 + __ sbc(r8, r24, r20); // sbc x8, x24, x20 + __ sbcs(r12, r28, r0); // sbcs x12, x28, x0 // AddSubExtendedOp - __ addw(r23, r6, r16, ext::uxtb, 4); // add w23, w6, w16, uxtb #4 - __ addsw(r25, r25, r23, ext::sxth, 2); // adds w25, w25, w23, sxth #2 - __ sub(r26, r22, r4, ext::uxtx, 1); // sub x26, x22, x4, uxtx #1 - __ subsw(r17, r29, r19, ext::sxtx, 3); // subs w17, w29, w19, sxtx #3 - __ add(r11, r30, r21, ext::uxtb, 3); // add x11, x30, x21, uxtb #3 - __ adds(r16, r19, r0, ext::sxtb, 2); // adds x16, x19, x0, sxtb #2 - __ sub(r11, r9, r25, ext::sxtx, 1); // sub x11, x9, x25, sxtx #1 - __ subs(r17, r20, r12, ext::sxtb, 4); // subs x17, x20, x12, sxtb #4 + __ addw(r23, r6, r16, ext::uxtb, 4); // add w23, w6, w16, uxtb #4 + __ addsw(r25, r25, r23, ext::sxth, 2); // adds w25, w25, w23, sxth #2 + __ sub(r26, r22, r4, ext::uxtx, 1); // sub x26, x22, x4, uxtx #1 + __ subsw(r17, r29, r19, ext::sxtx, 3); // subs w17, w29, w19, sxtx #3 + __ add(r11, r30, r21, ext::uxtb, 3); // add x11, x30, x21, uxtb #3 + __ adds(r16, r19, r0, ext::sxtb, 2); // adds x16, x19, x0, sxtb #2 + __ sub(r11, r9, r25, ext::sxtx, 1); // sub x11, x9, x25, sxtx #1 + __ subs(r17, r20, r12, ext::sxtb, 4); // subs x17, x20, x12, sxtb #4 // ConditionalCompareOp - __ ccmnw(r13, r11, 3u, Assembler::LE); // ccmn w13, w11, #3, LE - __ ccmpw(r13, r12, 2u, Assembler::HI); // ccmp w13, w12, #2, HI - __ ccmn(r3, r2, 12u, Assembler::NE); // ccmn x3, x2, #12, NE - __ ccmp(r7, r21, 3u, Assembler::VS); // ccmp x7, x21, #3, VS + __ ccmnw(r13, r11, 3u, Assembler::LE); // ccmn w13, w11, #3, LE + __ ccmpw(r13, r12, 2u, Assembler::HI); // ccmp w13, w12, #2, HI + __ ccmn(r3, r2, 12u, Assembler::NE); // ccmn x3, x2, #12, NE + __ ccmp(r7, r21, 3u, Assembler::VS); // ccmp x7, x21, #3, VS // ConditionalCompareImmedOp - __ ccmnw(r2, 14, 4, Assembler::CC); // ccmn w2, #14, #4, CC - __ ccmpw(r17, 17, 6, Assembler::PL); // ccmp w17, #17, #6, PL - __ ccmn(r10, 12, 0, Assembler::CS); // ccmn x10, #12, #0, CS - __ ccmp(r21, 18, 14, Assembler::GE); // ccmp x21, #18, #14, GE + __ ccmnw(r2, 14, 4, Assembler::CC); // ccmn w2, #14, #4, CC + __ ccmpw(r17, 17, 6, Assembler::PL); // ccmp w17, #17, #6, PL + __ ccmn(r10, 12, 0, Assembler::CS); // ccmn x10, #12, #0, CS + __ ccmp(r21, 18, 14, Assembler::GE); // ccmp x21, #18, #14, GE // ConditionalSelectOp - __ cselw(r21, r13, r12, Assembler::GT); // csel w21, w13, w12, GT - __ csincw(r10, r27, r15, Assembler::LS); // csinc w10, w27, w15, LS - __ csinvw(r0, r13, r9, Assembler::HI); // csinv w0, w13, w9, HI - __ csnegw(r18, r4, r26, Assembler::VS); // csneg w18, w4, w26, VS - __ csel(r12, r29, r7, Assembler::LS); // csel x12, x29, x7, LS - __ csinc(r6, r7, r20, Assembler::VC); // csinc x6, x7, x20, VC - __ csinv(r22, r21, r3, Assembler::LE); // csinv x22, x21, x3, LE - __ csneg(r19, r12, r27, Assembler::LS); // csneg x19, x12, x27, LS + __ cselw(r21, r13, r12, Assembler::GT); // csel w21, w13, w12, GT + __ csincw(r10, r27, r15, Assembler::LS); // csinc w10, w27, w15, LS + __ csinvw(r0, r13, r9, Assembler::HI); // csinv w0, w13, w9, HI + __ csnegw(r18, r4, r26, Assembler::VS); // csneg w18, w4, w26, VS + __ csel(r12, r29, r7, Assembler::LS); // csel x12, x29, x7, LS + __ csinc(r6, r7, r20, Assembler::VC); // csinc x6, x7, x20, VC + __ csinv(r22, r21, r3, Assembler::LE); // csinv x22, x21, x3, LE + __ csneg(r19, r12, r27, Assembler::LS); // csneg x19, x12, x27, LS // TwoRegOp - __ rbitw(r0, r16); // rbit w0, w16 - __ rev16w(r17, r23); // rev16 w17, w23 - __ revw(r17, r14); // rev w17, w14 - __ clzw(r24, r30); // clz w24, w30 - __ clsw(r24, r22); // cls w24, w22 - __ rbit(r3, r17); // rbit x3, x17 - __ rev16(r12, r13); // rev16 x12, x13 - __ rev32(r9, r22); // rev32 x9, x22 - __ rev(r0, r0); // rev x0, x0 - __ clz(r5, r16); // clz x5, x16 - __ cls(r25, r22); // cls x25, x22 + __ rbitw(r0, r16); // rbit w0, w16 + __ rev16w(r17, r23); // rev16 w17, w23 + __ revw(r17, r14); // rev w17, w14 + __ clzw(r24, r30); // clz w24, w30 + __ clsw(r24, r22); // cls w24, w22 + __ rbit(r3, r17); // rbit x3, x17 + __ rev16(r12, r13); // rev16 x12, x13 + __ rev32(r9, r22); // rev32 x9, x22 + __ rev(r0, r0); // rev x0, x0 + __ clz(r5, r16); // clz x5, x16 + __ cls(r25, r22); // cls x25, x22 // ThreeRegOp - __ udivw(r29, r4, r0); // udiv w29, w4, w0 - __ sdivw(r0, r29, r29); // sdiv w0, w29, w29 - __ lslvw(r5, r17, r21); // lslv w5, w17, w21 - __ lsrvw(r9, r9, r18); // lsrv w9, w9, w18 - __ asrvw(r1, r27, r8); // asrv w1, w27, w8 - __ rorvw(r18, r20, r13); // rorv w18, w20, w13 - __ udiv(r8, r25, r12); // udiv x8, x25, x12 - __ sdiv(r7, r5, r28); // sdiv x7, x5, x28 - __ lslv(r5, r17, r27); // lslv x5, x17, x27 - __ lsrv(r23, r26, r20); // lsrv x23, x26, x20 - __ asrv(r28, r8, r28); // asrv x28, x8, x28 - __ rorv(r3, r29, r4); // rorv x3, x29, x4 + __ udivw(r29, r4, r0); // udiv w29, w4, w0 + __ sdivw(r0, r29, r29); // sdiv w0, w29, w29 + __ lslvw(r5, r17, r21); // lslv w5, w17, w21 + __ lsrvw(r9, r9, r18); // lsrv w9, w9, w18 + __ asrvw(r1, r27, r8); // asrv w1, w27, w8 + __ rorvw(r18, r20, r13); // rorv w18, w20, w13 + __ udiv(r8, r25, r12); // udiv x8, x25, x12 + __ sdiv(r7, r5, r28); // sdiv x7, x5, x28 + __ lslv(r5, r17, r27); // lslv x5, x17, x27 + __ lsrv(r23, r26, r20); // lsrv x23, x26, x20 + __ asrv(r28, r8, r28); // asrv x28, x8, x28 + __ rorv(r3, r29, r4); // rorv x3, x29, x4 // FourRegMulOp - __ maddw(r17, r14, r26, r21); // madd w17, w14, w26, w21 - __ msubw(r1, r30, r11, r11); // msub w1, w30, w11, w11 - __ madd(r1, r17, r6, r28); // madd x1, x17, x6, x28 - __ msub(r30, r6, r30, r8); // msub x30, x6, x30, x8 - __ smaddl(r21, r6, r14, r8); // smaddl x21, w6, w14, x8 - __ smsubl(r10, r10, r24, r19); // smsubl x10, w10, w24, x19 - __ umaddl(r20, r18, r14, r24); // umaddl x20, w18, w14, x24 - __ umsubl(r18, r2, r5, r5); // umsubl x18, w2, w5, x5 + __ maddw(r17, r14, r26, r21); // madd w17, w14, w26, w21 + __ msubw(r1, r30, r11, r11); // msub w1, w30, w11, w11 + __ madd(r1, r17, r6, r28); // madd x1, x17, x6, x28 + __ msub(r30, r6, r30, r8); // msub x30, x6, x30, x8 + __ smaddl(r21, r6, r14, r8); // smaddl x21, w6, w14, x8 + __ smsubl(r10, r10, r24, r19); // smsubl x10, w10, w24, x19 + __ umaddl(r20, r18, r14, r24); // umaddl x20, w18, w14, x24 + __ umsubl(r18, r2, r5, r5); // umsubl x18, w2, w5, x5 // ThreeRegFloatOp - __ fmuls(v8, v18, v13); // fmul s8, s18, s13 - __ fdivs(v2, v14, v28); // fdiv s2, s14, s28 - __ fadds(v15, v12, v28); // fadd s15, s12, s28 - __ fsubs(v0, v12, v1); // fsub s0, s12, s1 - __ fmuls(v15, v29, v4); // fmul s15, s29, s4 - __ fmuld(v12, v1, v23); // fmul d12, d1, d23 - __ fdivd(v27, v8, v18); // fdiv d27, d8, d18 - __ faddd(v23, v20, v11); // fadd d23, d20, d11 - __ fsubd(v8, v12, v18); // fsub d8, d12, d18 - __ fmuld(v26, v24, v23); // fmul d26, d24, d23 + __ fmuls(v8, v18, v13); // fmul s8, s18, s13 + __ fdivs(v2, v14, v28); // fdiv s2, s14, s28 + __ fadds(v15, v12, v28); // fadd s15, s12, s28 + __ fsubs(v0, v12, v1); // fsub s0, s12, s1 + __ fmuls(v15, v29, v4); // fmul s15, s29, s4 + __ fmuld(v12, v1, v23); // fmul d12, d1, d23 + __ fdivd(v27, v8, v18); // fdiv d27, d8, d18 + __ faddd(v23, v20, v11); // fadd d23, d20, d11 + __ fsubd(v8, v12, v18); // fsub d8, d12, d18 + __ fmuld(v26, v24, v23); // fmul d26, d24, d23 // FourRegFloatOp - __ fmadds(v21, v23, v13, v25); // fmadd s21, s23, s13, s25 - __ fmsubs(v22, v10, v1, v14); // fmsub s22, s10, s1, s14 - __ fnmadds(v14, v20, v2, v30); // fnmadd s14, s20, s2, s30 - __ fnmadds(v7, v29, v22, v22); // fnmadd s7, s29, s22, s22 - __ fmaddd(v13, v5, v15, v5); // fmadd d13, d5, d15, d5 - __ fmsubd(v14, v12, v5, v10); // fmsub d14, d12, d5, d10 - __ fnmaddd(v10, v19, v0, v1); // fnmadd d10, d19, d0, d1 - __ fnmaddd(v20, v2, v2, v0); // fnmadd d20, d2, d2, d0 + __ fmadds(v21, v23, v13, v25); // fmadd s21, s23, s13, s25 + __ fmsubs(v22, v10, v1, v14); // fmsub s22, s10, s1, s14 + __ fnmadds(v14, v20, v2, v30); // fnmadd s14, s20, s2, s30 + __ fnmadds(v7, v29, v22, v22); // fnmadd s7, s29, s22, s22 + __ fmaddd(v13, v5, v15, v5); // fmadd d13, d5, d15, d5 + __ fmsubd(v14, v12, v5, v10); // fmsub d14, d12, d5, d10 + __ fnmaddd(v10, v19, v0, v1); // fnmadd d10, d19, d0, d1 + __ fnmaddd(v20, v2, v2, v0); // fnmadd d20, d2, d2, d0 // TwoRegFloatOp - __ fmovs(v25, v9); // fmov s25, s9 - __ fabss(v20, v4); // fabs s20, s4 - __ fnegs(v3, v27); // fneg s3, s27 - __ fsqrts(v1, v2); // fsqrt s1, s2 - __ fcvts(v30, v0); // fcvt d30, s0 - __ fmovd(v12, v4); // fmov d12, d4 - __ fabsd(v1, v27); // fabs d1, d27 - __ fnegd(v8, v22); // fneg d8, d22 - __ fsqrtd(v11, v11); // fsqrt d11, d11 - __ fcvtd(v22, v28); // fcvt s22, d28 + __ fmovs(v25, v9); // fmov s25, s9 + __ fabss(v20, v4); // fabs s20, s4 + __ fnegs(v3, v27); // fneg s3, s27 + __ fsqrts(v1, v2); // fsqrt s1, s2 + __ fcvts(v30, v0); // fcvt d30, s0 + __ fmovd(v12, v4); // fmov d12, d4 + __ fabsd(v1, v27); // fabs d1, d27 + __ fnegd(v8, v22); // fneg d8, d22 + __ fsqrtd(v11, v11); // fsqrt d11, d11 + __ fcvtd(v22, v28); // fcvt s22, d28 // FloatConvertOp - __ fcvtzsw(r28, v22); // fcvtzs w28, s22 - __ fcvtzs(r20, v27); // fcvtzs x20, s27 - __ fcvtzdw(r14, v0); // fcvtzs w14, d0 - __ fcvtzd(r26, v11); // fcvtzs x26, d11 - __ scvtfws(v28, r22); // scvtf s28, w22 - __ scvtfs(v16, r10); // scvtf s16, x10 - __ scvtfwd(v8, r21); // scvtf d8, w21 - __ scvtfd(v21, r28); // scvtf d21, x28 - __ fmovs(r24, v24); // fmov w24, s24 - __ fmovd(r8, v19); // fmov x8, d19 - __ fmovs(v8, r12); // fmov s8, w12 - __ fmovd(v6, r7); // fmov d6, x7 + __ fcvtzsw(r28, v22); // fcvtzs w28, s22 + __ fcvtzs(r20, v27); // fcvtzs x20, s27 + __ fcvtzdw(r14, v0); // fcvtzs w14, d0 + __ fcvtzd(r26, v11); // fcvtzs x26, d11 + __ scvtfws(v28, r22); // scvtf s28, w22 + __ scvtfs(v16, r10); // scvtf s16, x10 + __ scvtfwd(v8, r21); // scvtf d8, w21 + __ scvtfd(v21, r28); // scvtf d21, x28 + __ fmovs(r24, v24); // fmov w24, s24 + __ fmovd(r8, v19); // fmov x8, d19 + __ fmovs(v8, r12); // fmov s8, w12 + __ fmovd(v6, r7); // fmov d6, x7 // TwoRegFloatOp - __ fcmps(v30, v16); // fcmp s30, s16 - __ fcmpd(v25, v11); // fcmp d25, d11 - __ fcmps(v11, 0.0); // fcmp s11, #0.0 - __ fcmpd(v11, 0.0); // fcmp d11, #0.0 + __ fcmps(v30, v16); // fcmp s30, s16 + __ fcmpd(v25, v11); // fcmp d25, d11 + __ fcmps(v11, 0.0); // fcmp s11, #0.0 + __ fcmpd(v11, 0.0); // fcmp d11, #0.0 // LoadStorePairOp - __ stpw(r29, r12, Address(r17, 128)); // stp w29, w12, [x17, #128] - __ ldpw(r22, r18, Address(r14, -96)); // ldp w22, w18, [x14, #-96] - __ ldpsw(r11, r16, Address(r1, 64)); // ldpsw x11, x16, [x1, #64] - __ stp(r0, r11, Address(r26, 112)); // stp x0, x11, [x26, #112] - __ ldp(r7, r1, Address(r26, 16)); // ldp x7, x1, [x26, #16] + __ stpw(r29, r12, Address(r17, 128)); // stp w29, w12, [x17, #128] + __ ldpw(r22, r18, Address(r14, -96)); // ldp w22, w18, [x14, #-96] + __ ldpsw(r11, r16, Address(r1, 64)); // ldpsw x11, x16, [x1, #64] + __ stp(r0, r11, Address(r26, 112)); // stp x0, x11, [x26, #112] + __ ldp(r7, r1, Address(r26, 16)); // ldp x7, x1, [x26, #16] // LoadStorePairOp - __ stpw(r10, r7, Address(__ pre(r24, 0))); // stp w10, w7, [x24, #0]! - __ ldpw(r7, r28, Address(__ pre(r24, -256))); // ldp w7, w28, [x24, #-256]! - __ ldpsw(r25, r28, Address(__ pre(r21, -240))); // ldpsw x25, x28, [x21, #-240]! - __ stp(r20, r18, Address(__ pre(r14, -16))); // stp x20, x18, [x14, #-16]! - __ ldp(r8, r10, Address(__ pre(r13, 80))); // ldp x8, x10, [x13, #80]! + __ stpw(r10, r7, Address(__ pre(r24, 0))); // stp w10, w7, [x24, #0]! + __ ldpw(r7, r28, Address(__ pre(r24, -256))); // ldp w7, w28, [x24, #-256]! + __ ldpsw(r25, r28, Address(__ pre(r21, -240))); // ldpsw x25, x28, [x21, #-240]! + __ stp(r20, r18, Address(__ pre(r14, -16))); // stp x20, x18, [x14, #-16]! + __ ldp(r8, r10, Address(__ pre(r13, 80))); // ldp x8, x10, [x13, #80]! // LoadStorePairOp - __ stpw(r26, r24, Address(__ post(r2, -128))); // stp w26, w24, [x2], #-128 - __ ldpw(r2, r25, Address(__ post(r21, -192))); // ldp w2, w25, [x21], #-192 - __ ldpsw(r17, r2, Address(__ post(r21, -144))); // ldpsw x17, x2, [x21], #-144 - __ stp(r12, r10, Address(__ post(r11, 96))); // stp x12, x10, [x11], #96 - __ ldp(r24, r6, Address(__ post(r17, -32))); // ldp x24, x6, [x17], #-32 + __ stpw(r26, r24, Address(__ post(r2, -128))); // stp w26, w24, [x2], #-128 + __ ldpw(r2, r25, Address(__ post(r21, -192))); // ldp w2, w25, [x21], #-192 + __ ldpsw(r17, r2, Address(__ post(r21, -144))); // ldpsw x17, x2, [x21], #-144 + __ stp(r12, r10, Address(__ post(r11, 96))); // stp x12, x10, [x11], #96 + __ ldp(r24, r6, Address(__ post(r17, -32))); // ldp x24, x6, [x17], #-32 // LoadStorePairOp - __ stnpw(r3, r30, Address(r14, -224)); // stnp w3, w30, [x14, #-224] - __ ldnpw(r15, r20, Address(r26, -144)); // ldnp w15, w20, [x26, #-144] - __ stnp(r22, r25, Address(r12, -128)); // stnp x22, x25, [x12, #-128] - __ ldnp(r27, r22, Address(r17, -176)); // ldnp x27, x22, [x17, #-176] + __ stnpw(r3, r30, Address(r14, -224)); // stnp w3, w30, [x14, #-224] + __ ldnpw(r15, r20, Address(r26, -144)); // ldnp w15, w20, [x26, #-144] + __ stnp(r22, r25, Address(r12, -128)); // stnp x22, x25, [x12, #-128] + __ ldnp(r27, r22, Address(r17, -176)); // ldnp x27, x22, [x17, #-176] // FloatImmediateOp - __ fmovd(v0, 2.0); // fmov d0, #2.0 - __ fmovd(v0, 2.125); // fmov d0, #2.125 - __ fmovd(v0, 4.0); // fmov d0, #4.0 - __ fmovd(v0, 4.25); // fmov d0, #4.25 - __ fmovd(v0, 8.0); // fmov d0, #8.0 - __ fmovd(v0, 8.5); // fmov d0, #8.5 - __ fmovd(v0, 16.0); // fmov d0, #16.0 - __ fmovd(v0, 17.0); // fmov d0, #17.0 - __ fmovd(v0, 0.125); // fmov d0, #0.125 - __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125 - __ fmovd(v0, 0.25); // fmov d0, #0.25 - __ fmovd(v0, 0.265625); // fmov d0, #0.265625 - __ fmovd(v0, 0.5); // fmov d0, #0.5 - __ fmovd(v0, 0.53125); // fmov d0, #0.53125 - __ fmovd(v0, 1.0); // fmov d0, #1.0 - __ fmovd(v0, 1.0625); // fmov d0, #1.0625 - __ fmovd(v0, -2.0); // fmov d0, #-2.0 - __ fmovd(v0, -2.125); // fmov d0, #-2.125 - __ fmovd(v0, -4.0); // fmov d0, #-4.0 - __ fmovd(v0, -4.25); // fmov d0, #-4.25 - __ fmovd(v0, -8.0); // fmov d0, #-8.0 - __ fmovd(v0, -8.5); // fmov d0, #-8.5 - __ fmovd(v0, -16.0); // fmov d0, #-16.0 - __ fmovd(v0, -17.0); // fmov d0, #-17.0 - __ fmovd(v0, -0.125); // fmov d0, #-0.125 - __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125 - __ fmovd(v0, -0.25); // fmov d0, #-0.25 - __ fmovd(v0, -0.265625); // fmov d0, #-0.265625 - __ fmovd(v0, -0.5); // fmov d0, #-0.5 - __ fmovd(v0, -0.53125); // fmov d0, #-0.53125 - __ fmovd(v0, -1.0); // fmov d0, #-1.0 - __ fmovd(v0, -1.0625); // fmov d0, #-1.0625 + __ fmovd(v0, 2.0); // fmov d0, #2.0 + __ fmovd(v0, 2.125); // fmov d0, #2.125 + __ fmovd(v0, 4.0); // fmov d0, #4.0 + __ fmovd(v0, 4.25); // fmov d0, #4.25 + __ fmovd(v0, 8.0); // fmov d0, #8.0 + __ fmovd(v0, 8.5); // fmov d0, #8.5 + __ fmovd(v0, 16.0); // fmov d0, #16.0 + __ fmovd(v0, 17.0); // fmov d0, #17.0 + __ fmovd(v0, 0.125); // fmov d0, #0.125 + __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125 + __ fmovd(v0, 0.25); // fmov d0, #0.25 + __ fmovd(v0, 0.265625); // fmov d0, #0.265625 + __ fmovd(v0, 0.5); // fmov d0, #0.5 + __ fmovd(v0, 0.53125); // fmov d0, #0.53125 + __ fmovd(v0, 1.0); // fmov d0, #1.0 + __ fmovd(v0, 1.0625); // fmov d0, #1.0625 + __ fmovd(v0, -2.0); // fmov d0, #-2.0 + __ fmovd(v0, -2.125); // fmov d0, #-2.125 + __ fmovd(v0, -4.0); // fmov d0, #-4.0 + __ fmovd(v0, -4.25); // fmov d0, #-4.25 + __ fmovd(v0, -8.0); // fmov d0, #-8.0 + __ fmovd(v0, -8.5); // fmov d0, #-8.5 + __ fmovd(v0, -16.0); // fmov d0, #-16.0 + __ fmovd(v0, -17.0); // fmov d0, #-17.0 + __ fmovd(v0, -0.125); // fmov d0, #-0.125 + __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125 + __ fmovd(v0, -0.25); // fmov d0, #-0.25 + __ fmovd(v0, -0.265625); // fmov d0, #-0.265625 + __ fmovd(v0, -0.5); // fmov d0, #-0.5 + __ fmovd(v0, -0.53125); // fmov d0, #-0.53125 + __ fmovd(v0, -1.0); // fmov d0, #-1.0 + __ fmovd(v0, -1.0625); // fmov d0, #-1.0625 __ bind(forth); @@ -631,431 +631,431 @@ Disassembly of section .text: 0000000000000000 <back>: - 0: 8b0772d3 add x19, x22, x7, lsl #28 - 4: cb4a3570 sub x16, x11, x10, lsr #13 - 8: ab9c09bb adds x27, x13, x28, asr #2 - c: eb9aa794 subs x20, x28, x26, asr #41 - 10: 0b934e68 add w8, w19, w19, asr #19 - 14: 4b0a3924 sub w4, w9, w10, lsl #14 - 18: 2b1e3568 adds w8, w11, w30, lsl #13 - 1c: 6b132720 subs w0, w25, w19, lsl #9 - 20: 8a154c14 and x20, x0, x21, lsl #19 - 24: aa1445d5 orr x21, x14, x20, lsl #17 - 28: ca01cf99 eor x25, x28, x1, lsl #51 - 2c: ea8b3f6a ands x10, x27, x11, asr #15 - 30: 0a8c5cb9 and w25, w5, w12, asr #23 - 34: 2a4a11d2 orr w18, w14, w10, lsr #4 - 38: 4a855aa4 eor w4, w21, w5, asr #22 - 3c: 6a857415 ands w21, w0, w5, asr #29 - 40: 8aa697da bic x26, x30, x6, asr #37 - 44: aa6d7423 orn x3, x1, x13, lsr #29 - 48: ca29bf80 eon x0, x28, x9, lsl #47 - 4c: ea3cb8bd bics x29, x5, x28, lsl #46 - 50: 0a675249 bic w9, w18, w7, lsr #20 - 54: 2ab961ba orn w26, w13, w25, asr #24 - 58: 4a331899 eon w25, w4, w19, lsl #6 - 5c: 6a646345 bics w5, w26, w4, lsr #24 - 60: 11055267 add w7, w19, #0x154 - 64: 31064408 adds w8, w0, #0x191 - 68: 51028e9d sub w29, w20, #0xa3 - 6c: 710bdee8 subs w8, w23, #0x2f7 - 70: 91082d81 add x1, x12, #0x20b - 74: b106a962 adds x2, x11, #0x1aa - 78: d10b33ae sub x14, x29, #0x2cc - 7c: f10918ab subs x11, x5, #0x246 - 80: 121102d7 and w23, w22, #0x8000 - 84: 3204cd44 orr w4, w10, #0xf0f0f0f0 - 88: 5204cf00 eor w0, w24, #0xf0f0f0f0 - 8c: 72099fb3 ands w19, w29, #0x7f807f80 - 90: 92729545 and x5, x10, #0xfffffffffc000 - 94: b20e37cc orr x12, x30, #0xfffc0000fffc0000 - 98: d27c34be eor x30, x5, #0x3fff0 - 9c: f27e4efa ands x26, x23, #0x3ffffc - a0: 14000000 b a0 <back+0xa0> - a4: 17ffffd7 b 0 <back> - a8: 1400017f b 6a4 <forth> - ac: 94000000 bl ac <back+0xac> - b0: 97ffffd4 bl 0 <back> - b4: 9400017c bl 6a4 <forth> - b8: 3400000c cbz w12, b8 <back+0xb8> - bc: 34fffa2c cbz w12, 0 <back> - c0: 34002f2c cbz w12, 6a4 <forth> - c4: 35000014 cbnz w20, c4 <back+0xc4> - c8: 35fff9d4 cbnz w20, 0 <back> - cc: 35002ed4 cbnz w20, 6a4 <forth> - d0: b400000c cbz x12, d0 <back+0xd0> - d4: b4fff96c cbz x12, 0 <back> - d8: b4002e6c cbz x12, 6a4 <forth> - dc: b5000018 cbnz x24, dc <back+0xdc> - e0: b5fff918 cbnz x24, 0 <back> - e4: b5002e18 cbnz x24, 6a4 <forth> - e8: 10000006 adr x6, e8 <back+0xe8> - ec: 10fff8a6 adr x6, 0 <back> - f0: 10002da6 adr x6, 6a4 <forth> - f4: 90000015 adrp x21, 0 <back> - f8: 36080001 tbz w1, #1, f8 <back+0xf8> - fc: 360ff821 tbz w1, #1, 0 <back> - 100: 36082d21 tbz w1, #1, 6a4 <forth> - 104: 37480008 tbnz w8, #9, 104 <back+0x104> - 108: 374ff7c8 tbnz w8, #9, 0 <back> - 10c: 37482cc8 tbnz w8, #9, 6a4 <forth> - 110: 128b50ec movn w12, #0x5a87 - 114: 52a9ff8b movz w11, #0x4ffc, lsl #16 - 118: 7281d095 movk w21, #0xe84 - 11c: 92edfebd movn x29, #0x6ff5, lsl #48 - 120: d28361e3 movz x3, #0x1b0f - 124: f2a4cc96 movk x22, #0x2664, lsl #16 - 128: 9346590c sbfx x12, x8, #6, #17 - 12c: 33194f33 bfi w19, w25, #7, #20 - 130: 531d3d89 ubfiz w9, w12, #3, #16 - 134: 9350433c sbfx x28, x25, #16, #1 - 138: b34464ac bfxil x12, x5, #4, #22 - 13c: d3462140 ubfx x0, x10, #6, #3 - 140: 139a61a4 extr w4, w13, w26, #24 - 144: 93d87fd7 extr x23, x30, x24, #31 - 148: 54000000 b.eq 148 <back+0x148> - 14c: 54fff5a0 b.eq 0 <back> - 150: 54002aa0 b.eq 6a4 <forth> - 154: 54000001 b.ne 154 <back+0x154> - 158: 54fff541 b.ne 0 <back> - 15c: 54002a41 b.ne 6a4 <forth> - 160: 54000002 b.cs 160 <back+0x160> - 164: 54fff4e2 b.cs 0 <back> - 168: 540029e2 b.cs 6a4 <forth> - 16c: 54000002 b.cs 16c <back+0x16c> - 170: 54fff482 b.cs 0 <back> - 174: 54002982 b.cs 6a4 <forth> - 178: 54000003 b.cc 178 <back+0x178> - 17c: 54fff423 b.cc 0 <back> - 180: 54002923 b.cc 6a4 <forth> - 184: 54000003 b.cc 184 <back+0x184> - 188: 54fff3c3 b.cc 0 <back> - 18c: 540028c3 b.cc 6a4 <forth> - 190: 54000004 b.mi 190 <back+0x190> - 194: 54fff364 b.mi 0 <back> - 198: 54002864 b.mi 6a4 <forth> - 19c: 54000005 b.pl 19c <back+0x19c> - 1a0: 54fff305 b.pl 0 <back> - 1a4: 54002805 b.pl 6a4 <forth> - 1a8: 54000006 b.vs 1a8 <back+0x1a8> - 1ac: 54fff2a6 b.vs 0 <back> - 1b0: 540027a6 b.vs 6a4 <forth> - 1b4: 54000007 b.vc 1b4 <back+0x1b4> - 1b8: 54fff247 b.vc 0 <back> - 1bc: 54002747 b.vc 6a4 <forth> - 1c0: 54000008 b.hi 1c0 <back+0x1c0> - 1c4: 54fff1e8 b.hi 0 <back> - 1c8: 540026e8 b.hi 6a4 <forth> - 1cc: 54000009 b.ls 1cc <back+0x1cc> - 1d0: 54fff189 b.ls 0 <back> - 1d4: 54002689 b.ls 6a4 <forth> - 1d8: 5400000a b.ge 1d8 <back+0x1d8> - 1dc: 54fff12a b.ge 0 <back> - 1e0: 5400262a b.ge 6a4 <forth> - 1e4: 5400000b b.lt 1e4 <back+0x1e4> - 1e8: 54fff0cb b.lt 0 <back> - 1ec: 540025cb b.lt 6a4 <forth> - 1f0: 5400000c b.gt 1f0 <back+0x1f0> - 1f4: 54fff06c b.gt 0 <back> - 1f8: 5400256c b.gt 6a4 <forth> - 1fc: 5400000d b.le 1fc <back+0x1fc> - 200: 54fff00d b.le 0 <back> - 204: 5400250d b.le 6a4 <forth> - 208: 5400000e b.al 208 <back+0x208> - 20c: 54ffefae b.al 0 <back> - 210: 540024ae b.al 6a4 <forth> - 214: 5400000f b.nv 214 <back+0x214> - 218: 54ffef4f b.nv 0 <back> - 21c: 5400244f b.nv 6a4 <forth> - 220: d4063721 svc #0x31b9 - 224: d4035082 hvc #0x1a84 - 228: d400bfe3 smc #0x5ff - 22c: d4282fc0 brk #0x417e - 230: d444c320 hlt #0x2619 - 234: d503201f nop - 238: d69f03e0 eret - 23c: d6bf03e0 drps - 240: d5033fdf isb - 244: d5033f9f dsb sy - 248: d5033abf dmb ishst - 24c: d61f0040 br x2 - 250: d63f00a0 blr x5 - 254: c8147c55 stxr w20, x21, [x2] + 0: 8b0772d3 add x19, x22, x7, lsl #28 + 4: cb4a3570 sub x16, x11, x10, lsr #13 + 8: ab9c09bb adds x27, x13, x28, asr #2 + c: eb9aa794 subs x20, x28, x26, asr #41 + 10: 0b934e68 add w8, w19, w19, asr #19 + 14: 4b0a3924 sub w4, w9, w10, lsl #14 + 18: 2b1e3568 adds w8, w11, w30, lsl #13 + 1c: 6b132720 subs w0, w25, w19, lsl #9 + 20: 8a154c14 and x20, x0, x21, lsl #19 + 24: aa1445d5 orr x21, x14, x20, lsl #17 + 28: ca01cf99 eor x25, x28, x1, lsl #51 + 2c: ea8b3f6a ands x10, x27, x11, asr #15 + 30: 0a8c5cb9 and w25, w5, w12, asr #23 + 34: 2a4a11d2 orr w18, w14, w10, lsr #4 + 38: 4a855aa4 eor w4, w21, w5, asr #22 + 3c: 6a857415 ands w21, w0, w5, asr #29 + 40: 8aa697da bic x26, x30, x6, asr #37 + 44: aa6d7423 orn x3, x1, x13, lsr #29 + 48: ca29bf80 eon x0, x28, x9, lsl #47 + 4c: ea3cb8bd bics x29, x5, x28, lsl #46 + 50: 0a675249 bic w9, w18, w7, lsr #20 + 54: 2ab961ba orn w26, w13, w25, asr #24 + 58: 4a331899 eon w25, w4, w19, lsl #6 + 5c: 6a646345 bics w5, w26, w4, lsr #24 + 60: 11055267 add w7, w19, #0x154 + 64: 31064408 adds w8, w0, #0x191 + 68: 51028e9d sub w29, w20, #0xa3 + 6c: 710bdee8 subs w8, w23, #0x2f7 + 70: 91082d81 add x1, x12, #0x20b + 74: b106a962 adds x2, x11, #0x1aa + 78: d10b33ae sub x14, x29, #0x2cc + 7c: f10918ab subs x11, x5, #0x246 + 80: 121102d7 and w23, w22, #0x8000 + 84: 3204cd44 orr w4, w10, #0xf0f0f0f0 + 88: 5204cf00 eor w0, w24, #0xf0f0f0f0 + 8c: 72099fb3 ands w19, w29, #0x7f807f80 + 90: 92729545 and x5, x10, #0xfffffffffc000 + 94: b20e37cc orr x12, x30, #0xfffc0000fffc0000 + 98: d27c34be eor x30, x5, #0x3fff0 + 9c: f27e4efa ands x26, x23, #0x3ffffc + a0: 14000000 b a0 <back+0xa0> + a4: 17ffffd7 b 0 <back> + a8: 1400017f b 6a4 <forth> + ac: 94000000 bl ac <back+0xac> + b0: 97ffffd4 bl 0 <back> + b4: 9400017c bl 6a4 <forth> + b8: 3400000c cbz w12, b8 <back+0xb8> + bc: 34fffa2c cbz w12, 0 <back> + c0: 34002f2c cbz w12, 6a4 <forth> + c4: 35000014 cbnz w20, c4 <back+0xc4> + c8: 35fff9d4 cbnz w20, 0 <back> + cc: 35002ed4 cbnz w20, 6a4 <forth> + d0: b400000c cbz x12, d0 <back+0xd0> + d4: b4fff96c cbz x12, 0 <back> + d8: b4002e6c cbz x12, 6a4 <forth> + dc: b5000018 cbnz x24, dc <back+0xdc> + e0: b5fff918 cbnz x24, 0 <back> + e4: b5002e18 cbnz x24, 6a4 <forth> + e8: 10000006 adr x6, e8 <back+0xe8> + ec: 10fff8a6 adr x6, 0 <back> + f0: 10002da6 adr x6, 6a4 <forth> + f4: 90000015 adrp x21, 0 <back> + f8: 36080001 tbz w1, #1, f8 <back+0xf8> + fc: 360ff821 tbz w1, #1, 0 <back> + 100: 36082d21 tbz w1, #1, 6a4 <forth> + 104: 37480008 tbnz w8, #9, 104 <back+0x104> + 108: 374ff7c8 tbnz w8, #9, 0 <back> + 10c: 37482cc8 tbnz w8, #9, 6a4 <forth> + 110: 128b50ec movn w12, #0x5a87 + 114: 52a9ff8b movz w11, #0x4ffc, lsl #16 + 118: 7281d095 movk w21, #0xe84 + 11c: 92edfebd movn x29, #0x6ff5, lsl #48 + 120: d28361e3 movz x3, #0x1b0f + 124: f2a4cc96 movk x22, #0x2664, lsl #16 + 128: 9346590c sbfx x12, x8, #6, #17 + 12c: 33194f33 bfi w19, w25, #7, #20 + 130: 531d3d89 ubfiz w9, w12, #3, #16 + 134: 9350433c sbfx x28, x25, #16, #1 + 138: b34464ac bfxil x12, x5, #4, #22 + 13c: d3462140 ubfx x0, x10, #6, #3 + 140: 139a61a4 extr w4, w13, w26, #24 + 144: 93d87fd7 extr x23, x30, x24, #31 + 148: 54000000 b.eq 148 <back+0x148> + 14c: 54fff5a0 b.eq 0 <back> + 150: 54002aa0 b.eq 6a4 <forth> + 154: 54000001 b.ne 154 <back+0x154> + 158: 54fff541 b.ne 0 <back> + 15c: 54002a41 b.ne 6a4 <forth> + 160: 54000002 b.cs 160 <back+0x160> + 164: 54fff4e2 b.cs 0 <back> + 168: 540029e2 b.cs 6a4 <forth> + 16c: 54000002 b.cs 16c <back+0x16c> + 170: 54fff482 b.cs 0 <back> + 174: 54002982 b.cs 6a4 <forth> + 178: 54000003 b.cc 178 <back+0x178> + 17c: 54fff423 b.cc 0 <back> + 180: 54002923 b.cc 6a4 <forth> + 184: 54000003 b.cc 184 <back+0x184> + 188: 54fff3c3 b.cc 0 <back> + 18c: 540028c3 b.cc 6a4 <forth> + 190: 54000004 b.mi 190 <back+0x190> + 194: 54fff364 b.mi 0 <back> + 198: 54002864 b.mi 6a4 <forth> + 19c: 54000005 b.pl 19c <back+0x19c> + 1a0: 54fff305 b.pl 0 <back> + 1a4: 54002805 b.pl 6a4 <forth> + 1a8: 54000006 b.vs 1a8 <back+0x1a8> + 1ac: 54fff2a6 b.vs 0 <back> + 1b0: 540027a6 b.vs 6a4 <forth> + 1b4: 54000007 b.vc 1b4 <back+0x1b4> + 1b8: 54fff247 b.vc 0 <back> + 1bc: 54002747 b.vc 6a4 <forth> + 1c0: 54000008 b.hi 1c0 <back+0x1c0> + 1c4: 54fff1e8 b.hi 0 <back> + 1c8: 540026e8 b.hi 6a4 <forth> + 1cc: 54000009 b.ls 1cc <back+0x1cc> + 1d0: 54fff189 b.ls 0 <back> + 1d4: 54002689 b.ls 6a4 <forth> + 1d8: 5400000a b.ge 1d8 <back+0x1d8> + 1dc: 54fff12a b.ge 0 <back> + 1e0: 5400262a b.ge 6a4 <forth> + 1e4: 5400000b b.lt 1e4 <back+0x1e4> + 1e8: 54fff0cb b.lt 0 <back> + 1ec: 540025cb b.lt 6a4 <forth> + 1f0: 5400000c b.gt 1f0 <back+0x1f0> + 1f4: 54fff06c b.gt 0 <back> + 1f8: 5400256c b.gt 6a4 <forth> + 1fc: 5400000d b.le 1fc <back+0x1fc> + 200: 54fff00d b.le 0 <back> + 204: 5400250d b.le 6a4 <forth> + 208: 5400000e b.al 208 <back+0x208> + 20c: 54ffefae b.al 0 <back> + 210: 540024ae b.al 6a4 <forth> + 214: 5400000f b.nv 214 <back+0x214> + 218: 54ffef4f b.nv 0 <back> + 21c: 5400244f b.nv 6a4 <forth> + 220: d4063721 svc #0x31b9 + 224: d4035082 hvc #0x1a84 + 228: d400bfe3 smc #0x5ff + 22c: d4282fc0 brk #0x417e + 230: d444c320 hlt #0x2619 + 234: d503201f nop + 238: d69f03e0 eret + 23c: d6bf03e0 drps + 240: d5033fdf isb + 244: d5033f9f dsb sy + 248: d5033abf dmb ishst + 24c: d61f0040 br x2 + 250: d63f00a0 blr x5 + 254: c8147c55 stxr w20, x21, [x2] 258: c805fcfd stlxr w5, x29, [x7] - 25c: c85f7e05 ldxr x5, [x16] - 260: c85fffbb ldaxr x27, [x29] - 264: c89fffa0 stlr x0, [x29] - 268: c8dfff95 ldar x21, [x28] + 25c: c85f7e05 ldxr x5, [x16] + 260: c85fffbb ldaxr x27, [x29] + 264: c89fffa0 stlr x0, [x29] + 268: c8dfff95 ldar x21, [x28] 26c: 88157cf8 stxr w21, w24, [x7] - 270: 8815ff9a stlxr w21, w26, [x28] - 274: 885f7cd5 ldxr w21, [x6] - 278: 885fffcf ldaxr w15, [x30] - 27c: 889ffc73 stlr w19, [x3] - 280: 88dffc56 ldar w22, [x2] - 284: 48127c0f stxrh w18, w15, [x0] - 288: 480bff85 stlxrh w11, w5, [x28] - 28c: 485f7cdd ldxrh w29, [x6] - 290: 485ffcf2 ldaxrh w18, [x7] - 294: 489fff99 stlrh w25, [x28] - 298: 48dffe62 ldarh w2, [x19] - 29c: 080a7c3e stxrb w10, w30, [x1] - 2a0: 0814fed5 stlxrb w20, w21, [x22] - 2a4: 085f7c59 ldxrb w25, [x2] - 2a8: 085ffcb8 ldaxrb w24, [x5] - 2ac: 089ffc70 stlrb w16, [x3] - 2b0: 08dfffb6 ldarb w22, [x29] - 2b4: c87f0a68 ldxp x8, x2, [x19] - 2b8: c87fcdc7 ldaxp x7, x19, [x14] - 2bc: c82870bb stxp w8, x27, x28, [x5] + 270: 8815ff9a stlxr w21, w26, [x28] + 274: 885f7cd5 ldxr w21, [x6] + 278: 885fffcf ldaxr w15, [x30] + 27c: 889ffc73 stlr w19, [x3] + 280: 88dffc56 ldar w22, [x2] + 284: 48127c0f stxrh w18, w15, [x0] + 288: 480bff85 stlxrh w11, w5, [x28] + 28c: 485f7cdd ldxrh w29, [x6] + 290: 485ffcf2 ldaxrh w18, [x7] + 294: 489fff99 stlrh w25, [x28] + 298: 48dffe62 ldarh w2, [x19] + 29c: 080a7c3e stxrb w10, w30, [x1] + 2a0: 0814fed5 stlxrb w20, w21, [x22] + 2a4: 085f7c59 ldxrb w25, [x2] + 2a8: 085ffcb8 ldaxrb w24, [x5] + 2ac: 089ffc70 stlrb w16, [x3] + 2b0: 08dfffb6 ldarb w22, [x29] + 2b4: c87f0a68 ldxp x8, x2, [x19] + 2b8: c87fcdc7 ldaxp x7, x19, [x14] + 2bc: c82870bb stxp w8, x27, x28, [x5] 2c0: c825b8c8 stlxp w5, x8, x14, [x6] - 2c4: 887f12d9 ldxp w25, w4, [x22] + 2c4: 887f12d9 ldxp w25, w4, [x22] 2c8: 887fb9ed ldaxp w13, w14, [x15] - 2cc: 8834215a stxp w20, w26, w8, [x10] - 2d0: 8837ca52 stlxp w23, w18, w18, [x18] - 2d4: f806317e str x30, [x11,#99] - 2d8: b81b3337 str w23, [x25,#-77] - 2dc: 39000dc2 strb w2, [x14,#3] - 2e0: 78005149 strh w9, [x10,#5] - 2e4: f84391f4 ldr x20, [x15,#57] - 2e8: b85b220c ldr w12, [x16,#-78] - 2ec: 385fd356 ldrb w22, [x26,#-3] - 2f0: 785d127e ldrh w30, [x19,#-47] - 2f4: 389f4149 ldrsb x9, [x10,#-12] - 2f8: 79801e3c ldrsh x28, [x17,#14] - 2fc: 79c014a3 ldrsh w3, [x5,#10] - 300: b89a5231 ldrsw x17, [x17,#-91] - 304: fc5ef282 ldr d2, [x20,#-17] - 308: bc5f60f6 ldr s22, [x7,#-10] - 30c: fc12125e str d30, [x18,#-223] - 310: bc0152cd str s13, [x22,#21] - 314: f8190e49 str x9, [x18,#-112]! - 318: b800befd str w29, [x23,#11]! - 31c: 381ffd92 strb w18, [x12,#-1]! - 320: 781e9e90 strh w16, [x20,#-23]! - 324: f8409fa3 ldr x3, [x29,#9]! - 328: b8413c79 ldr w25, [x3,#19]! - 32c: 385fffa1 ldrb w1, [x29,#-1]! - 330: 785c7fa8 ldrh w8, [x29,#-57]! - 334: 389f3dc5 ldrsb x5, [x14,#-13]! - 338: 78801f6a ldrsh x10, [x27,#1]! - 33c: 78c19d4b ldrsh w11, [x10,#25]! - 340: b89a4ec4 ldrsw x4, [x22,#-92]! - 344: fc408eeb ldr d11, [x23,#8]! - 348: bc436e79 ldr s25, [x19,#54]! - 34c: fc152ce1 str d1, [x7,#-174]! - 350: bc036f28 str s8, [x25,#54]! - 354: f8025565 str x5, [x11],#37 - 358: b80135f8 str w24, [x15],#19 - 35c: 381ff74f strb w15, [x26],#-1 - 360: 781fa652 strh w18, [x18],#-6 - 364: f851a447 ldr x7, [x2],#-230 - 368: b85e557b ldr w27, [x11],#-27 - 36c: 385e7472 ldrb w18, [x3],#-25 - 370: 785e070a ldrh w10, [x24],#-32 - 374: 38804556 ldrsb x22, [x10],#4 - 378: 78819591 ldrsh x17, [x12],#25 - 37c: 78dc24e8 ldrsh w8, [x7],#-62 - 380: b89cd6d7 ldrsw x23, [x22],#-51 - 384: fc430738 ldr d24, [x25],#48 - 388: bc5f6595 ldr s21, [x12],#-10 - 38c: fc1225b2 str d18, [x13],#-222 - 390: bc1d7430 str s16, [x1],#-41 - 394: f82fcac2 str x2, [x22,w15,sxtw] - 398: b83d6a02 str w2, [x16,x29] - 39c: 382e5a54 strb w20, [x18,w14,uxtw #0] - 3a0: 7834fa66 strh w6, [x19,x20,sxtx #1] - 3a4: f86ecbae ldr x14, [x29,w14,sxtw] - 3a8: b86cda90 ldr w16, [x20,w12,sxtw #2] - 3ac: 3860d989 ldrb w9, [x12,w0,sxtw #0] - 3b0: 78637a2c ldrh w12, [x17,x3,lsl #1] - 3b4: 38a3fa22 ldrsb x2, [x17,x3,sxtx #0] - 3b8: 78b15827 ldrsh x7, [x1,w17,uxtw #1] - 3bc: 78f2d9f9 ldrsh w25, [x15,w18,sxtw #1] - 3c0: b8ac6ab7 ldrsw x23, [x21,x12] - 3c4: fc6879a5 ldr d5, [x13,x8,lsl #3] - 3c8: bc767943 ldr s3, [x10,x22,lsl #2] - 3cc: fc3bc84e str d14, [x2,w27,sxtw] - 3d0: bc3968d4 str s20, [x6,x25] - 3d4: f91fc0fe str x30, [x7,#16256] - 3d8: b91da50f str w15, [x8,#7588] - 3dc: 391d280b strb w11, [x0,#1866] - 3e0: 791d2e23 strh w3, [x17,#3734] - 3e4: f95bc8e2 ldr x2, [x7,#14224] - 3e8: b95ce525 ldr w5, [x9,#7396] - 3ec: 395ae53c ldrb w28, [x9,#1721] - 3f0: 795c9282 ldrh w2, [x20,#3656] - 3f4: 399d7dd6 ldrsb x22, [x14,#1887] - 3f8: 799fe008 ldrsh x8, [x0,#4080] - 3fc: 79de9bc0 ldrsh w0, [x30,#3916] - 400: b99aae78 ldrsw x24, [x19,#6828] - 404: fd597598 ldr d24, [x12,#13032] - 408: bd5d1d08 ldr s8, [x8,#7452] - 40c: fd1f3dea str d10, [x15,#15992] - 410: bd1a227a str s26, [x19,#6688] - 414: 5800148a ldr x10, 6a4 <forth> - 418: 18000003 ldr w3, 418 <back+0x418> - 41c: f88092e0 prfm pldl1keep, [x23,#9] - 420: d8ffdf00 prfm pldl1keep, 0 <back> - 424: f8a84860 prfm pldl1keep, [x3,w8,uxtw] - 428: f99d7560 prfm pldl1keep, [x11,#15080] - 42c: 1a1c012d adc w13, w9, w28 - 430: 3a1c027b adcs w27, w19, w28 - 434: 5a060253 sbc w19, w18, w6 - 438: 7a03028e sbcs w14, w20, w3 - 43c: 9a0801d0 adc x16, x14, x8 - 440: ba0803a0 adcs x0, x29, x8 - 444: da140308 sbc x8, x24, x20 - 448: fa00038c sbcs x12, x28, x0 - 44c: 0b3010d7 add w23, w6, w16, uxtb #4 - 450: 2b37ab39 adds w25, w25, w23, sxth #2 - 454: cb2466da sub x26, x22, x4, uxtx #1 - 458: 6b33efb1 subs w17, w29, w19, sxtx #3 - 45c: 8b350fcb add x11, x30, w21, uxtb #3 - 460: ab208a70 adds x16, x19, w0, sxtb #2 - 464: cb39e52b sub x11, x9, x25, sxtx #1 - 468: eb2c9291 subs x17, x20, w12, sxtb #4 - 46c: 3a4bd1a3 ccmn w13, w11, #0x3, le - 470: 7a4c81a2 ccmp w13, w12, #0x2, hi - 474: ba42106c ccmn x3, x2, #0xc, ne - 478: fa5560e3 ccmp x7, x21, #0x3, vs - 47c: 3a4e3844 ccmn w2, #0xe, #0x4, cc - 480: 7a515a26 ccmp w17, #0x11, #0x6, pl - 484: ba4c2940 ccmn x10, #0xc, #0x0, cs - 488: fa52aaae ccmp x21, #0x12, #0xe, ge - 48c: 1a8cc1b5 csel w21, w13, w12, gt - 490: 1a8f976a csinc w10, w27, w15, ls - 494: 5a8981a0 csinv w0, w13, w9, hi - 498: 5a9a6492 csneg w18, w4, w26, vs - 49c: 9a8793ac csel x12, x29, x7, ls - 4a0: 9a9474e6 csinc x6, x7, x20, vc - 4a4: da83d2b6 csinv x22, x21, x3, le - 4a8: da9b9593 csneg x19, x12, x27, ls - 4ac: 5ac00200 rbit w0, w16 - 4b0: 5ac006f1 rev16 w17, w23 - 4b4: 5ac009d1 rev w17, w14 - 4b8: 5ac013d8 clz w24, w30 - 4bc: 5ac016d8 cls w24, w22 - 4c0: dac00223 rbit x3, x17 - 4c4: dac005ac rev16 x12, x13 - 4c8: dac00ac9 rev32 x9, x22 - 4cc: dac00c00 rev x0, x0 - 4d0: dac01205 clz x5, x16 - 4d4: dac016d9 cls x25, x22 - 4d8: 1ac0089d udiv w29, w4, w0 - 4dc: 1add0fa0 sdiv w0, w29, w29 - 4e0: 1ad52225 lsl w5, w17, w21 - 4e4: 1ad22529 lsr w9, w9, w18 - 4e8: 1ac82b61 asr w1, w27, w8 - 4ec: 1acd2e92 ror w18, w20, w13 - 4f0: 9acc0b28 udiv x8, x25, x12 - 4f4: 9adc0ca7 sdiv x7, x5, x28 - 4f8: 9adb2225 lsl x5, x17, x27 - 4fc: 9ad42757 lsr x23, x26, x20 - 500: 9adc291c asr x28, x8, x28 - 504: 9ac42fa3 ror x3, x29, x4 - 508: 1b1a55d1 madd w17, w14, w26, w21 - 50c: 1b0bafc1 msub w1, w30, w11, w11 - 510: 9b067221 madd x1, x17, x6, x28 - 514: 9b1ea0de msub x30, x6, x30, x8 - 518: 9b2e20d5 smaddl x21, w6, w14, x8 - 51c: 9b38cd4a smsubl x10, w10, w24, x19 - 520: 9bae6254 umaddl x20, w18, w14, x24 - 524: 9ba59452 umsubl x18, w2, w5, x5 - 528: 1e2d0a48 fmul s8, s18, s13 - 52c: 1e3c19c2 fdiv s2, s14, s28 - 530: 1e3c298f fadd s15, s12, s28 - 534: 1e213980 fsub s0, s12, s1 - 538: 1e240baf fmul s15, s29, s4 - 53c: 1e77082c fmul d12, d1, d23 - 540: 1e72191b fdiv d27, d8, d18 - 544: 1e6b2a97 fadd d23, d20, d11 - 548: 1e723988 fsub d8, d12, d18 - 54c: 1e770b1a fmul d26, d24, d23 - 550: 1f0d66f5 fmadd s21, s23, s13, s25 - 554: 1f01b956 fmsub s22, s10, s1, s14 - 558: 1f227a8e fnmadd s14, s20, s2, s30 - 55c: 1f365ba7 fnmadd s7, s29, s22, s22 - 560: 1f4f14ad fmadd d13, d5, d15, d5 - 564: 1f45a98e fmsub d14, d12, d5, d10 - 568: 1f60066a fnmadd d10, d19, d0, d1 - 56c: 1f620054 fnmadd d20, d2, d2, d0 - 570: 1e204139 fmov s25, s9 - 574: 1e20c094 fabs s20, s4 - 578: 1e214363 fneg s3, s27 - 57c: 1e21c041 fsqrt s1, s2 - 580: 1e22c01e fcvt d30, s0 - 584: 1e60408c fmov d12, d4 - 588: 1e60c361 fabs d1, d27 - 58c: 1e6142c8 fneg d8, d22 - 590: 1e61c16b fsqrt d11, d11 - 594: 1e624396 fcvt s22, d28 - 598: 1e3802dc fcvtzs w28, s22 - 59c: 9e380374 fcvtzs x20, s27 - 5a0: 1e78000e fcvtzs w14, d0 - 5a4: 9e78017a fcvtzs x26, d11 - 5a8: 1e2202dc scvtf s28, w22 - 5ac: 9e220150 scvtf s16, x10 - 5b0: 1e6202a8 scvtf d8, w21 - 5b4: 9e620395 scvtf d21, x28 - 5b8: 1e260318 fmov w24, s24 - 5bc: 9e660268 fmov x8, d19 - 5c0: 1e270188 fmov s8, w12 - 5c4: 9e6700e6 fmov d6, x7 - 5c8: 1e3023c0 fcmp s30, s16 - 5cc: 1e6b2320 fcmp d25, d11 - 5d0: 1e202168 fcmp s11, #0.0 - 5d4: 1e602168 fcmp d11, #0.0 - 5d8: 2910323d stp w29, w12, [x17,#128] - 5dc: 297449d6 ldp w22, w18, [x14,#-96] - 5e0: 6948402b ldpsw x11, x16, [x1,#64] - 5e4: a9072f40 stp x0, x11, [x26,#112] - 5e8: a9410747 ldp x7, x1, [x26,#16] - 5ec: 29801f0a stp w10, w7, [x24,#0]! - 5f0: 29e07307 ldp w7, w28, [x24,#-256]! - 5f4: 69e272b9 ldpsw x25, x28, [x21,#-240]! - 5f8: a9bf49d4 stp x20, x18, [x14,#-16]! - 5fc: a9c529a8 ldp x8, x10, [x13,#80]! - 600: 28b0605a stp w26, w24, [x2],#-128 - 604: 28e866a2 ldp w2, w25, [x21],#-192 - 608: 68ee0ab1 ldpsw x17, x2, [x21],#-144 - 60c: a886296c stp x12, x10, [x11],#96 - 610: a8fe1a38 ldp x24, x6, [x17],#-32 - 614: 282479c3 stnp w3, w30, [x14,#-224] - 618: 286e534f ldnp w15, w20, [x26,#-144] - 61c: a8386596 stnp x22, x25, [x12,#-128] - 620: a8755a3b ldnp x27, x22, [x17,#-176] - 624: 1e601000 fmov d0, #2.000000000000000000e+00 - 628: 1e603000 fmov d0, #2.125000000000000000e+00 - 62c: 1e621000 fmov d0, #4.000000000000000000e+00 - 630: 1e623000 fmov d0, #4.250000000000000000e+00 - 634: 1e641000 fmov d0, #8.000000000000000000e+00 - 638: 1e643000 fmov d0, #8.500000000000000000e+00 - 63c: 1e661000 fmov d0, #1.600000000000000000e+01 - 640: 1e663000 fmov d0, #1.700000000000000000e+01 - 644: 1e681000 fmov d0, #1.250000000000000000e-01 - 648: 1e683000 fmov d0, #1.328125000000000000e-01 - 64c: 1e6a1000 fmov d0, #2.500000000000000000e-01 - 650: 1e6a3000 fmov d0, #2.656250000000000000e-01 - 654: 1e6c1000 fmov d0, #5.000000000000000000e-01 - 658: 1e6c3000 fmov d0, #5.312500000000000000e-01 - 65c: 1e6e1000 fmov d0, #1.000000000000000000e+00 - 660: 1e6e3000 fmov d0, #1.062500000000000000e+00 - 664: 1e701000 fmov d0, #-2.000000000000000000e+00 - 668: 1e703000 fmov d0, #-2.125000000000000000e+00 - 66c: 1e721000 fmov d0, #-4.000000000000000000e+00 - 670: 1e723000 fmov d0, #-4.250000000000000000e+00 - 674: 1e741000 fmov d0, #-8.000000000000000000e+00 - 678: 1e743000 fmov d0, #-8.500000000000000000e+00 - 67c: 1e761000 fmov d0, #-1.600000000000000000e+01 - 680: 1e763000 fmov d0, #-1.700000000000000000e+01 - 684: 1e781000 fmov d0, #-1.250000000000000000e-01 - 688: 1e783000 fmov d0, #-1.328125000000000000e-01 - 68c: 1e7a1000 fmov d0, #-2.500000000000000000e-01 - 690: 1e7a3000 fmov d0, #-2.656250000000000000e-01 - 694: 1e7c1000 fmov d0, #-5.000000000000000000e-01 - 698: 1e7c3000 fmov d0, #-5.312500000000000000e-01 - 69c: 1e7e1000 fmov d0, #-1.000000000000000000e+00 - 6a0: 1e7e3000 fmov d0, #-1.062500000000000000e+00 + 2cc: 8834215a stxp w20, w26, w8, [x10] + 2d0: 8837ca52 stlxp w23, w18, w18, [x18] + 2d4: f806317e str x30, [x11,#99] + 2d8: b81b3337 str w23, [x25,#-77] + 2dc: 39000dc2 strb w2, [x14,#3] + 2e0: 78005149 strh w9, [x10,#5] + 2e4: f84391f4 ldr x20, [x15,#57] + 2e8: b85b220c ldr w12, [x16,#-78] + 2ec: 385fd356 ldrb w22, [x26,#-3] + 2f0: 785d127e ldrh w30, [x19,#-47] + 2f4: 389f4149 ldrsb x9, [x10,#-12] + 2f8: 79801e3c ldrsh x28, [x17,#14] + 2fc: 79c014a3 ldrsh w3, [x5,#10] + 300: b89a5231 ldrsw x17, [x17,#-91] + 304: fc5ef282 ldr d2, [x20,#-17] + 308: bc5f60f6 ldr s22, [x7,#-10] + 30c: fc12125e str d30, [x18,#-223] + 310: bc0152cd str s13, [x22,#21] + 314: f8190e49 str x9, [x18,#-112]! + 318: b800befd str w29, [x23,#11]! + 31c: 381ffd92 strb w18, [x12,#-1]! + 320: 781e9e90 strh w16, [x20,#-23]! + 324: f8409fa3 ldr x3, [x29,#9]! + 328: b8413c79 ldr w25, [x3,#19]! + 32c: 385fffa1 ldrb w1, [x29,#-1]! + 330: 785c7fa8 ldrh w8, [x29,#-57]! + 334: 389f3dc5 ldrsb x5, [x14,#-13]! + 338: 78801f6a ldrsh x10, [x27,#1]! + 33c: 78c19d4b ldrsh w11, [x10,#25]! + 340: b89a4ec4 ldrsw x4, [x22,#-92]! + 344: fc408eeb ldr d11, [x23,#8]! + 348: bc436e79 ldr s25, [x19,#54]! + 34c: fc152ce1 str d1, [x7,#-174]! + 350: bc036f28 str s8, [x25,#54]! + 354: f8025565 str x5, [x11],#37 + 358: b80135f8 str w24, [x15],#19 + 35c: 381ff74f strb w15, [x26],#-1 + 360: 781fa652 strh w18, [x18],#-6 + 364: f851a447 ldr x7, [x2],#-230 + 368: b85e557b ldr w27, [x11],#-27 + 36c: 385e7472 ldrb w18, [x3],#-25 + 370: 785e070a ldrh w10, [x24],#-32 + 374: 38804556 ldrsb x22, [x10],#4 + 378: 78819591 ldrsh x17, [x12],#25 + 37c: 78dc24e8 ldrsh w8, [x7],#-62 + 380: b89cd6d7 ldrsw x23, [x22],#-51 + 384: fc430738 ldr d24, [x25],#48 + 388: bc5f6595 ldr s21, [x12],#-10 + 38c: fc1225b2 str d18, [x13],#-222 + 390: bc1d7430 str s16, [x1],#-41 + 394: f82fcac2 str x2, [x22,w15,sxtw] + 398: b83d6a02 str w2, [x16,x29] + 39c: 382e5a54 strb w20, [x18,w14,uxtw #0] + 3a0: 7834fa66 strh w6, [x19,x20,sxtx #1] + 3a4: f86ecbae ldr x14, [x29,w14,sxtw] + 3a8: b86cda90 ldr w16, [x20,w12,sxtw #2] + 3ac: 3860d989 ldrb w9, [x12,w0,sxtw #0] + 3b0: 78637a2c ldrh w12, [x17,x3,lsl #1] + 3b4: 38a3fa22 ldrsb x2, [x17,x3,sxtx #0] + 3b8: 78b15827 ldrsh x7, [x1,w17,uxtw #1] + 3bc: 78f2d9f9 ldrsh w25, [x15,w18,sxtw #1] + 3c0: b8ac6ab7 ldrsw x23, [x21,x12] + 3c4: fc6879a5 ldr d5, [x13,x8,lsl #3] + 3c8: bc767943 ldr s3, [x10,x22,lsl #2] + 3cc: fc3bc84e str d14, [x2,w27,sxtw] + 3d0: bc3968d4 str s20, [x6,x25] + 3d4: f91fc0fe str x30, [x7,#16256] + 3d8: b91da50f str w15, [x8,#7588] + 3dc: 391d280b strb w11, [x0,#1866] + 3e0: 791d2e23 strh w3, [x17,#3734] + 3e4: f95bc8e2 ldr x2, [x7,#14224] + 3e8: b95ce525 ldr w5, [x9,#7396] + 3ec: 395ae53c ldrb w28, [x9,#1721] + 3f0: 795c9282 ldrh w2, [x20,#3656] + 3f4: 399d7dd6 ldrsb x22, [x14,#1887] + 3f8: 799fe008 ldrsh x8, [x0,#4080] + 3fc: 79de9bc0 ldrsh w0, [x30,#3916] + 400: b99aae78 ldrsw x24, [x19,#6828] + 404: fd597598 ldr d24, [x12,#13032] + 408: bd5d1d08 ldr s8, [x8,#7452] + 40c: fd1f3dea str d10, [x15,#15992] + 410: bd1a227a str s26, [x19,#6688] + 414: 5800148a ldr x10, 6a4 <forth> + 418: 18000003 ldr w3, 418 <back+0x418> + 41c: f88092e0 prfm pldl1keep, [x23,#9] + 420: d8ffdf00 prfm pldl1keep, 0 <back> + 424: f8a84860 prfm pldl1keep, [x3,w8,uxtw] + 428: f99d7560 prfm pldl1keep, [x11,#15080] + 42c: 1a1c012d adc w13, w9, w28 + 430: 3a1c027b adcs w27, w19, w28 + 434: 5a060253 sbc w19, w18, w6 + 438: 7a03028e sbcs w14, w20, w3 + 43c: 9a0801d0 adc x16, x14, x8 + 440: ba0803a0 adcs x0, x29, x8 + 444: da140308 sbc x8, x24, x20 + 448: fa00038c sbcs x12, x28, x0 + 44c: 0b3010d7 add w23, w6, w16, uxtb #4 + 450: 2b37ab39 adds w25, w25, w23, sxth #2 + 454: cb2466da sub x26, x22, x4, uxtx #1 + 458: 6b33efb1 subs w17, w29, w19, sxtx #3 + 45c: 8b350fcb add x11, x30, w21, uxtb #3 + 460: ab208a70 adds x16, x19, w0, sxtb #2 + 464: cb39e52b sub x11, x9, x25, sxtx #1 + 468: eb2c9291 subs x17, x20, w12, sxtb #4 + 46c: 3a4bd1a3 ccmn w13, w11, #0x3, le + 470: 7a4c81a2 ccmp w13, w12, #0x2, hi + 474: ba42106c ccmn x3, x2, #0xc, ne + 478: fa5560e3 ccmp x7, x21, #0x3, vs + 47c: 3a4e3844 ccmn w2, #0xe, #0x4, cc + 480: 7a515a26 ccmp w17, #0x11, #0x6, pl + 484: ba4c2940 ccmn x10, #0xc, #0x0, cs + 488: fa52aaae ccmp x21, #0x12, #0xe, ge + 48c: 1a8cc1b5 csel w21, w13, w12, gt + 490: 1a8f976a csinc w10, w27, w15, ls + 494: 5a8981a0 csinv w0, w13, w9, hi + 498: 5a9a6492 csneg w18, w4, w26, vs + 49c: 9a8793ac csel x12, x29, x7, ls + 4a0: 9a9474e6 csinc x6, x7, x20, vc + 4a4: da83d2b6 csinv x22, x21, x3, le + 4a8: da9b9593 csneg x19, x12, x27, ls + 4ac: 5ac00200 rbit w0, w16 + 4b0: 5ac006f1 rev16 w17, w23 + 4b4: 5ac009d1 rev w17, w14 + 4b8: 5ac013d8 clz w24, w30 + 4bc: 5ac016d8 cls w24, w22 + 4c0: dac00223 rbit x3, x17 + 4c4: dac005ac rev16 x12, x13 + 4c8: dac00ac9 rev32 x9, x22 + 4cc: dac00c00 rev x0, x0 + 4d0: dac01205 clz x5, x16 + 4d4: dac016d9 cls x25, x22 + 4d8: 1ac0089d udiv w29, w4, w0 + 4dc: 1add0fa0 sdiv w0, w29, w29 + 4e0: 1ad52225 lsl w5, w17, w21 + 4e4: 1ad22529 lsr w9, w9, w18 + 4e8: 1ac82b61 asr w1, w27, w8 + 4ec: 1acd2e92 ror w18, w20, w13 + 4f0: 9acc0b28 udiv x8, x25, x12 + 4f4: 9adc0ca7 sdiv x7, x5, x28 + 4f8: 9adb2225 lsl x5, x17, x27 + 4fc: 9ad42757 lsr x23, x26, x20 + 500: 9adc291c asr x28, x8, x28 + 504: 9ac42fa3 ror x3, x29, x4 + 508: 1b1a55d1 madd w17, w14, w26, w21 + 50c: 1b0bafc1 msub w1, w30, w11, w11 + 510: 9b067221 madd x1, x17, x6, x28 + 514: 9b1ea0de msub x30, x6, x30, x8 + 518: 9b2e20d5 smaddl x21, w6, w14, x8 + 51c: 9b38cd4a smsubl x10, w10, w24, x19 + 520: 9bae6254 umaddl x20, w18, w14, x24 + 524: 9ba59452 umsubl x18, w2, w5, x5 + 528: 1e2d0a48 fmul s8, s18, s13 + 52c: 1e3c19c2 fdiv s2, s14, s28 + 530: 1e3c298f fadd s15, s12, s28 + 534: 1e213980 fsub s0, s12, s1 + 538: 1e240baf fmul s15, s29, s4 + 53c: 1e77082c fmul d12, d1, d23 + 540: 1e72191b fdiv d27, d8, d18 + 544: 1e6b2a97 fadd d23, d20, d11 + 548: 1e723988 fsub d8, d12, d18 + 54c: 1e770b1a fmul d26, d24, d23 + 550: 1f0d66f5 fmadd s21, s23, s13, s25 + 554: 1f01b956 fmsub s22, s10, s1, s14 + 558: 1f227a8e fnmadd s14, s20, s2, s30 + 55c: 1f365ba7 fnmadd s7, s29, s22, s22 + 560: 1f4f14ad fmadd d13, d5, d15, d5 + 564: 1f45a98e fmsub d14, d12, d5, d10 + 568: 1f60066a fnmadd d10, d19, d0, d1 + 56c: 1f620054 fnmadd d20, d2, d2, d0 + 570: 1e204139 fmov s25, s9 + 574: 1e20c094 fabs s20, s4 + 578: 1e214363 fneg s3, s27 + 57c: 1e21c041 fsqrt s1, s2 + 580: 1e22c01e fcvt d30, s0 + 584: 1e60408c fmov d12, d4 + 588: 1e60c361 fabs d1, d27 + 58c: 1e6142c8 fneg d8, d22 + 590: 1e61c16b fsqrt d11, d11 + 594: 1e624396 fcvt s22, d28 + 598: 1e3802dc fcvtzs w28, s22 + 59c: 9e380374 fcvtzs x20, s27 + 5a0: 1e78000e fcvtzs w14, d0 + 5a4: 9e78017a fcvtzs x26, d11 + 5a8: 1e2202dc scvtf s28, w22 + 5ac: 9e220150 scvtf s16, x10 + 5b0: 1e6202a8 scvtf d8, w21 + 5b4: 9e620395 scvtf d21, x28 + 5b8: 1e260318 fmov w24, s24 + 5bc: 9e660268 fmov x8, d19 + 5c0: 1e270188 fmov s8, w12 + 5c4: 9e6700e6 fmov d6, x7 + 5c8: 1e3023c0 fcmp s30, s16 + 5cc: 1e6b2320 fcmp d25, d11 + 5d0: 1e202168 fcmp s11, #0.0 + 5d4: 1e602168 fcmp d11, #0.0 + 5d8: 2910323d stp w29, w12, [x17,#128] + 5dc: 297449d6 ldp w22, w18, [x14,#-96] + 5e0: 6948402b ldpsw x11, x16, [x1,#64] + 5e4: a9072f40 stp x0, x11, [x26,#112] + 5e8: a9410747 ldp x7, x1, [x26,#16] + 5ec: 29801f0a stp w10, w7, [x24,#0]! + 5f0: 29e07307 ldp w7, w28, [x24,#-256]! + 5f4: 69e272b9 ldpsw x25, x28, [x21,#-240]! + 5f8: a9bf49d4 stp x20, x18, [x14,#-16]! + 5fc: a9c529a8 ldp x8, x10, [x13,#80]! + 600: 28b0605a stp w26, w24, [x2],#-128 + 604: 28e866a2 ldp w2, w25, [x21],#-192 + 608: 68ee0ab1 ldpsw x17, x2, [x21],#-144 + 60c: a886296c stp x12, x10, [x11],#96 + 610: a8fe1a38 ldp x24, x6, [x17],#-32 + 614: 282479c3 stnp w3, w30, [x14,#-224] + 618: 286e534f ldnp w15, w20, [x26,#-144] + 61c: a8386596 stnp x22, x25, [x12,#-128] + 620: a8755a3b ldnp x27, x22, [x17,#-176] + 624: 1e601000 fmov d0, #2.000000000000000000e+00 + 628: 1e603000 fmov d0, #2.125000000000000000e+00 + 62c: 1e621000 fmov d0, #4.000000000000000000e+00 + 630: 1e623000 fmov d0, #4.250000000000000000e+00 + 634: 1e641000 fmov d0, #8.000000000000000000e+00 + 638: 1e643000 fmov d0, #8.500000000000000000e+00 + 63c: 1e661000 fmov d0, #1.600000000000000000e+01 + 640: 1e663000 fmov d0, #1.700000000000000000e+01 + 644: 1e681000 fmov d0, #1.250000000000000000e-01 + 648: 1e683000 fmov d0, #1.328125000000000000e-01 + 64c: 1e6a1000 fmov d0, #2.500000000000000000e-01 + 650: 1e6a3000 fmov d0, #2.656250000000000000e-01 + 654: 1e6c1000 fmov d0, #5.000000000000000000e-01 + 658: 1e6c3000 fmov d0, #5.312500000000000000e-01 + 65c: 1e6e1000 fmov d0, #1.000000000000000000e+00 + 660: 1e6e3000 fmov d0, #1.062500000000000000e+00 + 664: 1e701000 fmov d0, #-2.000000000000000000e+00 + 668: 1e703000 fmov d0, #-2.125000000000000000e+00 + 66c: 1e721000 fmov d0, #-4.000000000000000000e+00 + 670: 1e723000 fmov d0, #-4.250000000000000000e+00 + 674: 1e741000 fmov d0, #-8.000000000000000000e+00 + 678: 1e743000 fmov d0, #-8.500000000000000000e+00 + 67c: 1e761000 fmov d0, #-1.600000000000000000e+01 + 680: 1e763000 fmov d0, #-1.700000000000000000e+01 + 684: 1e781000 fmov d0, #-1.250000000000000000e-01 + 688: 1e783000 fmov d0, #-1.328125000000000000e-01 + 68c: 1e7a1000 fmov d0, #-2.500000000000000000e-01 + 690: 1e7a3000 fmov d0, #-2.656250000000000000e-01 + 694: 1e7c1000 fmov d0, #-5.000000000000000000e-01 + 698: 1e7c3000 fmov d0, #-5.312500000000000000e-01 + 69c: 1e7e1000 fmov d0, #-1.000000000000000000e+00 + 6a0: 1e7e3000 fmov d0, #-1.062500000000000000e+00 */ static const unsigned int insns[] = @@ -1166,7 +1166,7 @@ 0x1e723000, 0x1e741000, 0x1e743000, 0x1e761000, 0x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000, 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, - 0x1e7e3000, + 0x1e7e3000, }; // END Generated code -- do not edit @@ -1175,12 +1175,12 @@ unsigned int *insns1 = (unsigned int *)entry; for (unsigned int i = 0; i < sizeof insns / sizeof insns[0]; i++) { if (insns[i] != insns1[i]) { - ok = false; - printf("Ours:\n"); - Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]); - printf("Theirs:\n"); - Disassembler::decode((address)&insns[i], (address)&insns[i+1]); - printf("\n"); + ok = false; + printf("Ours:\n"); + Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]); + printf("Theirs:\n"); + Disassembler::decode((address)&insns[i], (address)&insns[i+1]); + printf("\n"); } } assert(ok, "Assembler smoke test failed"); @@ -1191,7 +1191,7 @@ address PC = __ pc(); __ ld1(v0, __ T16B, Address(r16)); // No offset __ ld1(v0, __ T16B, __ post(r16, 0)); // Post-index - __ ld1(v0, __ T16B, Address(r16, r17)); // + __ ld1(v0, __ T16B, Address(r16, r17)); // #endif // PRODUCT @@ -1368,7 +1368,7 @@ } void Assembler::wrap_label(Label &L, - Assembler::uncond_branch_insn insn) { + Assembler::uncond_branch_insn insn) { if (L.is_bound()) { (this->*insn)(target(L)); } else { @@ -1378,7 +1378,7 @@ } void Assembler::wrap_label(Register r, Label &L, - compare_and_branch_insn insn) { + compare_and_branch_insn insn) { if (L.is_bound()) { (this->*insn)(r, target(L)); } else { @@ -1388,7 +1388,7 @@ } void Assembler::wrap_label(Register r, int bitpos, Label &L, - test_and_branch_insn insn) { + test_and_branch_insn insn) { if (L.is_bound()) { (this->*insn)(r, bitpos, target(L)); } else { @@ -1412,7 +1412,7 @@ // requested ADD operation to a SUB, or vice versa, and then encode // the absolute value of the immediate as for uimm24. void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op, - int negated_op) { + int negated_op) { bool sets_flags = op & 1; // this op sets flags union { unsigned u; @@ -1512,7 +1512,7 @@ float val = (float)value; unsigned result = encoding_for_fp_immediate(val); guarantee(unpack(result) == value, - "Invalid floating-point immediate operand"); + "Invalid floating-point immediate operand"); return result; }
--- a/src/cpu/aarch64/vm/assembler_aarch64.hpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp Thu Apr 22 01:38:42 2021 +0100 @@ -324,7 +324,7 @@ public: enum mode { no_mode, base_plus_offset, pre, post, pcrel, - base_plus_offset_reg, literal }; + base_plus_offset_reg, literal }; // Shift and extend for base reg + reg offset addressing class extend { @@ -418,8 +418,8 @@ Register base() const { guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg - | _mode == post), - "wrong mode"); + | _mode == post), + "wrong mode"); return _base; } long offset() const { @@ -442,45 +442,45 @@ switch(_mode) { case base_plus_offset: { - unsigned size = i->get(31, 30); + unsigned size = i->get(31, 30); if (i->get(26, 26) && i->get(23, 23)) { // SIMD Q Type - Size = 128 bits assert(size == 0, "bad size"); size = 0b100; } - unsigned mask = (1 << size) - 1; - if (_offset < 0 || _offset & mask) - { - i->f(0b00, 25, 24); - i->f(0, 21), i->f(0b00, 11, 10); - i->sf(_offset, 20, 12); - } else { - i->f(0b01, 25, 24); - i->f(_offset >> size, 21, 10); - } + unsigned mask = (1 << size) - 1; + if (_offset < 0 || _offset & mask) + { + i->f(0b00, 25, 24); + i->f(0, 21), i->f(0b00, 11, 10); + i->sf(_offset, 20, 12); + } else { + i->f(0b01, 25, 24); + i->f(_offset >> size, 21, 10); + } } break; case base_plus_offset_reg: { - i->f(0b00, 25, 24); - i->f(1, 21); - i->rf(_index, 16); - i->f(_ext.option(), 15, 13); - unsigned size = i->get(31, 30); + i->f(0b00, 25, 24); + i->f(1, 21); + i->rf(_index, 16); + i->f(_ext.option(), 15, 13); + unsigned size = i->get(31, 30); if (i->get(26, 26) && i->get(23, 23)) { // SIMD Q Type - Size = 128 bits assert(size == 0, "bad size"); size = 0b100; } - if (size == 0) // It's a byte - i->f(_ext.shift() >= 0, 12); - else { - if (_ext.shift() > 0) - assert(_ext.shift() == (int)size, "bad shift"); - i->f(_ext.shift() > 0, 12); - } - i->f(0b10, 11, 10); + if (size == 0) // It's a byte + i->f(_ext.shift() >= 0, 12); + else { + if (_ext.shift() > 0) + assert(_ext.shift() == (int)size, "bad shift"); + i->f(_ext.shift() > 0, 12); + } + i->f(0b10, 11, 10); } break; @@ -521,13 +521,13 @@ if (i->get(26, 26)) { // float switch(i->get(31, 30)) { case 0b10: - size = 2; break; + size = 2; break; case 0b01: - size = 1; break; + size = 1; break; case 0b00: - size = 0; break; + size = 0; break; default: - ShouldNotReachHere(); + ShouldNotReachHere(); } } else { size = i->get(31, 31); @@ -548,7 +548,7 @@ i->sf(_offset / size, 21, 15); i->srf(_base, 5); guarantee(_mode == Address::base_plus_offset, - "Bad addressing mode for non-temporal op"); + "Bad addressing mode for non-temporal op"); } void lea(MacroAssembler *, Register) const; @@ -710,19 +710,19 @@ #undef INSN void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op, - int negated_op); + int negated_op); // Add/subtract (immediate) -#define INSN(NAME, decode, negated) \ - void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \ - starti; \ +#define INSN(NAME, decode, negated) \ + void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \ + starti; \ f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \ - zrf(Rd, 0), srf(Rn, 5); \ - } \ - \ - void NAME(Register Rd, Register Rn, unsigned imm) { \ - starti; \ - add_sub_immediate(Rd, Rn, imm, decode, negated); \ + zrf(Rd, 0), srf(Rn, 5); \ + } \ + \ + void NAME(Register Rd, Register Rn, unsigned imm) { \ + starti; \ + add_sub_immediate(Rd, Rn, imm, decode, negated); \ } INSN(addsw, 0b001, 0b011); @@ -732,10 +732,10 @@ #undef INSN -#define INSN(NAME, decode, negated) \ - void NAME(Register Rd, Register Rn, unsigned imm) { \ - starti; \ - add_sub_immediate(Rd, Rn, imm, decode, negated); \ +#define INSN(NAME, decode, negated) \ + void NAME(Register Rd, Register Rn, unsigned imm) { \ + starti; \ + add_sub_immediate(Rd, Rn, imm, decode, negated); \ } INSN(addw, 0b000, 0b010); @@ -746,12 +746,12 @@ #undef INSN // Logical (immediate) -#define INSN(NAME, decode, is32) \ - void NAME(Register Rd, Register Rn, uint64_t imm) { \ - starti; \ - uint32_t val = encode_logical_immediate(is32, imm); \ - f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ - srf(Rd, 0), zrf(Rn, 5); \ +#define INSN(NAME, decode, is32) \ + void NAME(Register Rd, Register Rn, uint64_t imm) { \ + starti; \ + uint32_t val = encode_logical_immediate(is32, imm); \ + f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ + srf(Rd, 0), zrf(Rn, 5); \ } INSN(andw, 0b000, true); @@ -763,12 +763,12 @@ #undef INSN -#define INSN(NAME, decode, is32) \ - void NAME(Register Rd, Register Rn, uint64_t imm) { \ - starti; \ - uint32_t val = encode_logical_immediate(is32, imm); \ - f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ - zrf(Rd, 0), zrf(Rn, 5); \ +#define INSN(NAME, decode, is32) \ + void NAME(Register Rd, Register Rn, uint64_t imm) { \ + starti; \ + uint32_t val = encode_logical_immediate(is32, imm); \ + f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ + zrf(Rd, 0), zrf(Rn, 5); \ } INSN(ands, 0b111, false); @@ -777,13 +777,13 @@ #undef INSN // Move wide (immediate) -#define INSN(NAME, opcode) \ - void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \ - assert_cond((shift/16)*16 == shift); \ - starti; \ - f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \ - f(imm, 20, 5); \ - rf(Rd, 0); \ +#define INSN(NAME, opcode) \ + void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \ + assert_cond((shift/16)*16 == shift); \ + starti; \ + f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \ + f(imm, 20, 5); \ + rf(Rd, 0); \ } INSN(movnw, 0b000); @@ -796,11 +796,11 @@ #undef INSN // Bitfield -#define INSN(NAME, opcode) \ - void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \ - starti; \ - f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \ - rf(Rn, 5), rf(Rd, 0); \ +#define INSN(NAME, opcode) \ + void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \ + starti; \ + f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \ + rf(Rn, 5), rf(Rd, 0); \ } INSN(sbfmw, 0b0001001100); @@ -813,11 +813,11 @@ #undef INSN // Extract -#define INSN(NAME, opcode) \ - void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \ - starti; \ - f(opcode, 31, 21), f(imms, 15, 10); \ - rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \ +#define INSN(NAME, opcode) \ + void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \ + starti; \ + f(opcode, 31, 21), f(imms, 15, 10); \ + rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \ } INSN(extrw, 0b00010011100); @@ -855,14 +855,14 @@ #undef INSN // Compare & branch (immediate) -#define INSN(NAME, opcode) \ - void NAME(Register Rt, address dest) { \ - long offset = (dest - pc()) >> 2; \ - starti; \ - f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \ - } \ - void NAME(Register Rt, Label &L) { \ - wrap_label(Rt, L, &Assembler::NAME); \ +#define INSN(NAME, opcode) \ + void NAME(Register Rt, address dest) { \ + long offset = (dest - pc()) >> 2; \ + starti; \ + f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \ + } \ + void NAME(Register Rt, Label &L) { \ + wrap_label(Rt, L, &Assembler::NAME); \ } INSN(cbzw, 0b00110100); @@ -873,17 +873,17 @@ #undef INSN // Test & branch (immediate) -#define INSN(NAME, opcode) \ - void NAME(Register Rt, int bitpos, address dest) { \ - long offset = (dest - pc()) >> 2; \ - int b5 = bitpos >> 5; \ - bitpos &= 0x1f; \ - starti; \ - f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \ - rf(Rt, 0); \ - } \ - void NAME(Register Rt, int bitpos, Label &L) { \ - wrap_label(Rt, bitpos, L, &Assembler::NAME); \ +#define INSN(NAME, opcode) \ + void NAME(Register Rt, int bitpos, address dest) { \ + long offset = (dest - pc()) >> 2; \ + int b5 = bitpos >> 5; \ + bitpos &= 0x1f; \ + starti; \ + f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \ + rf(Rt, 0); \ + } \ + void NAME(Register Rt, int bitpos, Label &L) { \ + wrap_label(Rt, bitpos, L, &Assembler::NAME); \ } INSN(tbz, 0b0110110); @@ -901,9 +901,9 @@ f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0); } -#define INSN(NAME, cond) \ - void NAME(address dest) { \ - br(cond, dest); \ +#define INSN(NAME, cond) \ + void NAME(address dest) { \ + br(cond, dest); \ } INSN(beq, EQ); @@ -936,9 +936,9 @@ f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0); } -#define INSN(NAME, opc, op2, LL) \ - void NAME(unsigned imm) { \ - generate_exception(opc, op2, LL, imm); \ +#define INSN(NAME, opc, op2, LL) \ + void NAME(unsigned imm) { \ + generate_exception(opc, op2, LL, imm); \ } INSN(svc, 0b000, 0, 0b01); @@ -1000,7 +1000,7 @@ } enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH, - ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY}; + ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY}; void dsb(barrier imm) { system(0b00, 0b011, 0b00011, imm, 0b100); @@ -1065,9 +1065,9 @@ f(0b00000, 4, 0); } -#define INSN(NAME, opc) \ - void NAME(Register R) { \ - branch_reg(R, opc); \ +#define INSN(NAME, opc) \ + void NAME(Register R) { \ + branch_reg(R, opc); \ } INSN(br, 0b0000); @@ -1078,8 +1078,8 @@ #undef INSN -#define INSN(NAME, opc) \ - void NAME() { \ +#define INSN(NAME, opc) \ + void NAME() { \ branch_reg(dummy_reg, opc); \ } @@ -1110,26 +1110,26 @@ sz, 0b000, ordered); } -#define INSN4(NAME, sz, op, o0) /* Four registers */ \ - void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \ +#define INSN4(NAME, sz, op, o0) /* Four registers */ \ + void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \ guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \ - load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \ + load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \ } -#define INSN3(NAME, sz, op, o0) /* Three registers */ \ - void NAME(Register Rs, Register Rt, Register Rn) { \ +#define INSN3(NAME, sz, op, o0) /* Three registers */ \ + void NAME(Register Rs, Register Rt, Register Rn) { \ guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction"); \ load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \ } -#define INSN2(NAME, sz, op, o0) /* Two registers */ \ - void NAME(Register Rt, Register Rn) { \ +#define INSN2(NAME, sz, op, o0) /* Two registers */ \ + void NAME(Register Rt, Register Rn) { \ load_store_exclusive(dummy_reg, Rt, dummy_reg, \ - Rn, sz, op, o0); \ + Rn, sz, op, o0); \ } #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \ - void NAME(Register Rt1, Register Rt2, Register Rn) { \ + void NAME(Register Rt1, Register Rt2, Register Rn) { \ guarantee(Rt1 != Rt2, "unpredictable instruction"); \ load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0); \ } @@ -1252,23 +1252,23 @@ #undef INSN // Load register (literal) -#define INSN(NAME, opc, V) \ - void NAME(Register Rt, address dest) { \ - long offset = (dest - pc()) >> 2; \ - starti; \ - f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ - sf(offset, 23, 5); \ - rf(Rt, 0); \ - } \ - void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \ - InstructionMark im(this); \ - guarantee(rtype == relocInfo::internal_word_type, \ - "only internal_word_type relocs make sense here"); \ +#define INSN(NAME, opc, V) \ + void NAME(Register Rt, address dest) { \ + long offset = (dest - pc()) >> 2; \ + starti; \ + f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ + sf(offset, 23, 5); \ + rf(Rt, 0); \ + } \ + void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \ + InstructionMark im(this); \ + guarantee(rtype == relocInfo::internal_word_type, \ + "only internal_word_type relocs make sense here"); \ code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \ - NAME(Rt, dest); \ - } \ - void NAME(Register Rt, Label &L) { \ - wrap_label(Rt, L, &Assembler::NAME); \ + NAME(Rt, dest); \ + } \ + void NAME(Register Rt, Label &L) { \ + wrap_label(Rt, L, &Assembler::NAME); \ } INSN(ldrw, 0b00, 0); @@ -1277,13 +1277,13 @@ #undef INSN -#define INSN(NAME, opc, V) \ - void NAME(FloatRegister Rt, address dest) { \ - long offset = (dest - pc()) >> 2; \ - starti; \ - f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ - sf(offset, 23, 5); \ - rf((Register)Rt, 0); \ +#define INSN(NAME, opc, V) \ + void NAME(FloatRegister Rt, address dest) { \ + long offset = (dest - pc()) >> 2; \ + starti; \ + f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ + sf(offset, 23, 5); \ + rf((Register)Rt, 0); \ } INSN(ldrs, 0b00, 1); @@ -1292,16 +1292,16 @@ #undef INSN -#define INSN(NAME, opc, V) \ - void NAME(address dest, prfop op = PLDL1KEEP) { \ - long offset = (dest - pc()) >> 2; \ - starti; \ - f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ - sf(offset, 23, 5); \ - f(op, 4, 0); \ - } \ - void NAME(Label &L, prfop op = PLDL1KEEP) { \ - wrap_label(L, op, &Assembler::NAME); \ +#define INSN(NAME, opc, V) \ + void NAME(address dest, prfop op = PLDL1KEEP) { \ + long offset = (dest - pc()) >> 2; \ + starti; \ + f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ + sf(offset, 23, 5); \ + f(op, 4, 0); \ + } \ + void NAME(Label &L, prfop op = PLDL1KEEP) { \ + wrap_label(L, op, &Assembler::NAME); \ } INSN(prfm, 0b11, 0); @@ -1310,7 +1310,7 @@ // Load/store void ld_st1(int opc, int p1, int V, int L, - Register Rt1, Register Rt2, Address adr, bool no_allocate) { + Register Rt1, Register Rt2, Address adr, bool no_allocate) { starti; f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22); zrf(Rt2, 10), zrf(Rt1, 0); @@ -1322,9 +1322,9 @@ } // Load/store register pair (offset) -#define INSN(NAME, size, p1, V, L, no_allocate) \ - void NAME(Register Rt1, Register Rt2, Address adr) { \ - ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \ +#define INSN(NAME, size, p1, V, L, no_allocate) \ + void NAME(Register Rt1, Register Rt2, Address adr) { \ + ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \ } INSN(stpw, 0b00, 0b101, 0, 0, false); @@ -1341,8 +1341,8 @@ #undef INSN -#define INSN(NAME, size, p1, V, L, no_allocate) \ - void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \ +#define INSN(NAME, size, p1, V, L, no_allocate) \ + void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \ ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \ } @@ -1381,10 +1381,10 @@ adr.encode(current); } -#define INSN(NAME, size, op) \ - void NAME(Register Rt, const Address &adr) { \ - ld_st2(Rt, adr, size, op); \ - } \ +#define INSN(NAME, size, op) \ + void NAME(Register Rt, const Address &adr) { \ + ld_st2(Rt, adr, size, op); \ + } \ INSN(str, 0b11, 0b00); INSN(strw, 0b10, 0b00); @@ -1404,20 +1404,20 @@ #undef INSN -#define INSN(NAME, size, op) \ - void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \ - ld_st2((Register)pfop, adr, size, op); \ +#define INSN(NAME, size, op) \ + void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \ + ld_st2((Register)pfop, adr, size, op); \ } INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with - // writeback modes, but the assembler - // doesn't enfore that. + // writeback modes, but the assembler + // doesn't enfore that. #undef INSN -#define INSN(NAME, size, op) \ - void NAME(FloatRegister Rt, const Address &adr) { \ - ld_st2((Register)Rt, adr, size, op, 1); \ +#define INSN(NAME, size, op) \ + void NAME(FloatRegister Rt, const Address &adr) { \ + ld_st2((Register)Rt, adr, size, op, 1); \ } INSN(strd, 0b11, 0b00); @@ -1432,8 +1432,8 @@ enum shift_kind { LSL, LSR, ASR, ROR }; void op_shifted_reg(unsigned decode, - enum shift_kind kind, unsigned shift, - unsigned size, unsigned op) { + enum shift_kind kind, unsigned shift, + unsigned size, unsigned op) { f(size, 31); f(op, 30, 29); f(decode, 28, 24); @@ -1442,13 +1442,13 @@ } // Logical (shifted register) -#define INSN(NAME, size, op, N) \ - void NAME(Register Rd, Register Rn, Register Rm, \ - enum shift_kind kind = LSL, unsigned shift = 0) { \ - starti; \ - f(N, 21); \ - zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \ - op_shifted_reg(0b01010, kind, shift, size, op); \ +#define INSN(NAME, size, op, N) \ + void NAME(Register Rd, Register Rn, Register Rm, \ + enum shift_kind kind = LSL, unsigned shift = 0) { \ + starti; \ + f(N, 21); \ + zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \ + op_shifted_reg(0b01010, kind, shift, size, op); \ } INSN(andr, 1, 0b00, 0); @@ -1472,14 +1472,14 @@ #undef INSN // Add/subtract (shifted register) -#define INSN(NAME, size, op) \ - void NAME(Register Rd, Register Rn, Register Rm, \ - enum shift_kind kind, unsigned shift = 0) { \ - starti; \ - f(0, 21); \ - assert_cond(kind != ROR); \ - zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \ - op_shifted_reg(0b01011, kind, shift, size, op); \ +#define INSN(NAME, size, op) \ + void NAME(Register Rd, Register Rn, Register Rm, \ + enum shift_kind kind, unsigned shift = 0) { \ + starti; \ + f(0, 21); \ + assert_cond(kind != ROR); \ + zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \ + op_shifted_reg(0b01011, kind, shift, size, op); \ } INSN(add, 1, 0b000); @@ -1495,11 +1495,11 @@ #undef INSN // Add/subtract (extended register) -#define INSN(NAME, op) \ - void NAME(Register Rd, Register Rn, Register Rm, \ - ext::operation option, int amount = 0) { \ - starti; \ - zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \ +#define INSN(NAME, op) \ + void NAME(Register Rd, Register Rn, Register Rm, \ + ext::operation option, int amount = 0) { \ + starti; \ + zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \ add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \ } @@ -1518,11 +1518,11 @@ #undef INSN -#define INSN(NAME, op) \ - void NAME(Register Rd, Register Rn, Register Rm, \ - ext::operation option, int amount = 0) { \ - starti; \ - zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \ +#define INSN(NAME, op) \ + void NAME(Register Rd, Register Rn, Register Rm, \ + ext::operation option, int amount = 0) { \ + starti; \ + zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \ add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \ } @@ -1534,12 +1534,12 @@ #undef INSN // Aliases for short forms of add and sub -#define INSN(NAME) \ - void NAME(Register Rd, Register Rn, Register Rm) { \ - if (Rd == sp || Rn == sp) \ - NAME(Rd, Rn, Rm, ext::uxtx); \ - else \ - NAME(Rd, Rn, Rm, LSL); \ +#define INSN(NAME) \ + void NAME(Register Rd, Register Rn, Register Rm) { \ + if (Rd == sp || Rn == sp) \ + NAME(Rd, Rn, Rm, ext::uxtx); \ + else \ + NAME(Rd, Rn, Rm, LSL); \ } INSN(addw); @@ -1563,9 +1563,9 @@ zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); } - #define INSN(NAME, op) \ - void NAME(Register Rd, Register Rn, Register Rm) { \ - add_sub_carry(op, Rd, Rn, Rm); \ + #define INSN(NAME, op) \ + void NAME(Register Rd, Register Rn, Register Rm) { \ + add_sub_carry(op, Rd, Rn, Rm); \ } INSN(adcw, 0b000); @@ -1592,17 +1592,17 @@ f(imm5, 20, 16), rf(Rn, 5); } -#define INSN(NAME, op) \ - void NAME(Register Rn, Register Rm, int imm, Condition cond) { \ - starti; \ - f(0, 11); \ - conditional_compare(op, 0, 0, Rn, (uintptr_t)Rm, imm, cond); \ - } \ - \ - void NAME(Register Rn, int imm5, int imm, Condition cond) { \ - starti; \ - f(1, 11); \ - conditional_compare(op, 0, 0, Rn, imm5, imm, cond); \ +#define INSN(NAME, op) \ + void NAME(Register Rn, Register Rm, int imm, Condition cond) { \ + starti; \ + f(0, 11); \ + conditional_compare(op, 0, 0, Rn, (uintptr_t)Rm, imm, cond); \ + } \ + \ + void NAME(Register Rn, int imm5, int imm, Condition cond) { \ + starti; \ + f(1, 11); \ + conditional_compare(op, 0, 0, Rn, imm5, imm, cond); \ } INSN(ccmnw, 0b001); @@ -1614,8 +1614,8 @@ // Conditional select void conditional_select(unsigned op, unsigned op2, - Register Rd, Register Rn, Register Rm, - unsigned cond) { + Register Rd, Register Rn, Register Rm, + unsigned cond) { starti; f(op, 31, 29); f(0b11010100, 28, 21); @@ -1624,9 +1624,9 @@ zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0); } -#define INSN(NAME, op, op2) \ +#define INSN(NAME, op, op2) \ void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \ - conditional_select(op, op2, Rd, Rn, Rm, cond); \ + conditional_select(op, op2, Rd, Rn, Rm, cond); \ } INSN(cselw, 0b000, 0b00); @@ -1642,18 +1642,18 @@ // Data processing void data_processing(unsigned op29, unsigned opcode, - Register Rd, Register Rn) { + Register Rd, Register Rn) { f(op29, 31, 29), f(0b11010110, 28, 21); f(opcode, 15, 10); rf(Rn, 5), rf(Rd, 0); } // (1 source) -#define INSN(NAME, op29, opcode2, opcode) \ - void NAME(Register Rd, Register Rn) { \ - starti; \ - f(opcode2, 20, 16); \ - data_processing(op29, opcode, Rd, Rn); \ +#define INSN(NAME, op29, opcode2, opcode) \ + void NAME(Register Rd, Register Rn) { \ + starti; \ + f(opcode2, 20, 16); \ + data_processing(op29, opcode, Rd, Rn); \ } INSN(rbitw, 0b010, 0b00000, 0b00000); @@ -1672,11 +1672,11 @@ #undef INSN // (2 sources) -#define INSN(NAME, op29, opcode) \ - void NAME(Register Rd, Register Rn, Register Rm) { \ - starti; \ - rf(Rm, 16); \ - data_processing(op29, opcode, Rd, Rn); \ +#define INSN(NAME, op29, opcode) \ + void NAME(Register Rd, Register Rn, Register Rm) { \ + starti; \ + rf(Rm, 16); \ + data_processing(op29, opcode, Rd, Rn); \ } INSN(udivw, 0b000, 0b000010); @@ -1697,17 +1697,17 @@ // (3 sources) void data_processing(unsigned op54, unsigned op31, unsigned o0, - Register Rd, Register Rn, Register Rm, - Register Ra) { + Register Rd, Register Rn, Register Rm, + Register Ra) { starti; f(op54, 31, 29), f(0b11011, 28, 24); f(op31, 23, 21), f(o0, 15); zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0); } -#define INSN(NAME, op54, op31, o0) \ - void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \ - data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \ +#define INSN(NAME, op54, op31, o0) \ + void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \ + data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \ } INSN(maddw, 0b000, 0b000, 0); @@ -1721,9 +1721,9 @@ #undef INSN -#define INSN(NAME, op54, op31, o0) \ - void NAME(Register Rd, Register Rn, Register Rm) { \ - data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \ +#define INSN(NAME, op54, op31, o0) \ + void NAME(Register Rd, Register Rn, Register Rm) { \ + data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \ } INSN(smulh, 0b100, 0b010, 0); @@ -1733,7 +1733,7 @@ // Floating-point data-processing (1 source) void data_processing(unsigned op31, unsigned type, unsigned opcode, - FloatRegister Vd, FloatRegister Vn) { + FloatRegister Vd, FloatRegister Vn) { starti; f(op31, 31, 29); f(0b11110, 28, 24); @@ -1741,9 +1741,9 @@ rf(Vn, 5), rf(Vd, 0); } -#define INSN(NAME, op31, type, opcode) \ - void NAME(FloatRegister Vd, FloatRegister Vn) { \ - data_processing(op31, type, opcode, Vd, Vn); \ +#define INSN(NAME, op31, type, opcode) \ + void NAME(FloatRegister Vd, FloatRegister Vn) { \ + data_processing(op31, type, opcode, Vd, Vn); \ } private: @@ -1776,7 +1776,7 @@ // Floating-point data-processing (2 source) void data_processing(unsigned op31, unsigned type, unsigned opcode, - FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { + FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { starti; f(op31, 31, 29); f(0b11110, 28, 24); @@ -1784,9 +1784,9 @@ rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); } -#define INSN(NAME, op31, type, opcode) \ - void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \ - data_processing(op31, type, opcode, Vd, Vn, Vm); \ +#define INSN(NAME, op31, type, opcode) \ + void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \ + data_processing(op31, type, opcode, Vd, Vn, Vm); \ } INSN(fmuls, 0b000, 0b00, 0b0000); @@ -1805,8 +1805,8 @@ // Floating-point data-processing (3 source) void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0, - FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, - FloatRegister Va) { + FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, + FloatRegister Va) { starti; f(op31, 31, 29); f(0b11111, 28, 24); @@ -1814,10 +1814,10 @@ rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0); } -#define INSN(NAME, op31, type, o1, o0) \ - void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \ - FloatRegister Va) { \ - data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \ +#define INSN(NAME, op31, type, o1, o0) \ + void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \ + FloatRegister Va) { \ + data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \ } INSN(fmadds, 0b000, 0b00, 0, 0); @@ -1860,8 +1860,8 @@ // Floating-point<->integer conversions void float_int_convert(unsigned op31, unsigned type, - unsigned rmode, unsigned opcode, - Register Rd, Register Rn) { + unsigned rmode, unsigned opcode, + Register Rd, Register Rn) { starti; f(op31, 31, 29); f(0b11110, 28, 24); @@ -1870,9 +1870,9 @@ zrf(Rn, 5), zrf(Rd, 0); } -#define INSN(NAME, op31, type, rmode, opcode) \ - void NAME(Register Rd, FloatRegister Vn) { \ - float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \ +#define INSN(NAME, op31, type, rmode, opcode) \ + void NAME(Register Rd, FloatRegister Vn) { \ + float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \ } INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000); @@ -1887,9 +1887,9 @@ #undef INSN -#define INSN(NAME, op31, type, rmode, opcode) \ - void NAME(FloatRegister Vd, Register Rn) { \ - float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \ +#define INSN(NAME, op31, type, rmode, opcode) \ + void NAME(FloatRegister Vd, Register Rn) { \ + float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \ } INSN(fmovs, 0b000, 0b00, 0b00, 0b111); @@ -1906,8 +1906,8 @@ // Floating-point compare void float_compare(unsigned op31, unsigned type, - unsigned op, unsigned op2, - FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) { + unsigned op, unsigned op2, + FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) { starti; f(op31, 31, 29); f(0b11110, 28, 24); @@ -1917,15 +1917,15 @@ } -#define INSN(NAME, op31, type, op, op2) \ - void NAME(FloatRegister Vn, FloatRegister Vm) { \ - float_compare(op31, type, op, op2, Vn, Vm); \ +#define INSN(NAME, op31, type, op, op2) \ + void NAME(FloatRegister Vn, FloatRegister Vm) { \ + float_compare(op31, type, op, op2, Vn, Vm); \ } -#define INSN1(NAME, op31, type, op, op2) \ - void NAME(FloatRegister Vn, double d) { \ - assert_cond(d == 0.0); \ - float_compare(op31, type, op, op2, Vn); \ +#define INSN1(NAME, op31, type, op, op2) \ + void NAME(FloatRegister Vn, double d) { \ + assert_cond(d == 0.0); \ + float_compare(op31, type, op, op2, Vn); \ } INSN(fcmps, 0b000, 0b00, 0b00, 0b00000); @@ -2034,31 +2034,31 @@ public: -#define INSN1(NAME, op1, op2) \ - void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \ - ld_st(Vt, T, a, op1, op2); \ +#define INSN1(NAME, op1, op2) \ + void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \ + ld_st(Vt, T, a, op1, op2); \ } -#define INSN2(NAME, op1, op2) \ +#define INSN2(NAME, op1, op2) \ void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \ - assert(Vt->successor() == Vt2, "Registers must be ordered"); \ - ld_st(Vt, T, a, op1, op2); \ + assert(Vt->successor() == Vt2, "Registers must be ordered"); \ + ld_st(Vt, T, a, op1, op2); \ } -#define INSN3(NAME, op1, op2) \ - void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ - SIMD_Arrangement T, const Address &a) { \ - assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \ - "Registers must be ordered"); \ - ld_st(Vt, T, a, op1, op2); \ +#define INSN3(NAME, op1, op2) \ + void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ + SIMD_Arrangement T, const Address &a) { \ + assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \ + "Registers must be ordered"); \ + ld_st(Vt, T, a, op1, op2); \ } -#define INSN4(NAME, op1, op2) \ - void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ - FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \ - assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \ - Vt3->successor() == Vt4, "Registers must be ordered"); \ - ld_st(Vt, T, a, op1, op2); \ +#define INSN4(NAME, op1, op2) \ + void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ + FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \ + assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \ + Vt3->successor() == Vt4, "Registers must be ordered"); \ + ld_st(Vt, T, a, op1, op2); \ } INSN1(ld1, 0b001100010, 0b0111); @@ -2266,10 +2266,10 @@ void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { starti; /* The encodings for the immh:immb fields (bits 22:16) are - * 0001 xxx 8H, 8B/16b shift = xxx - * 001x xxx 4S, 4H/8H shift = xxxx - * 01xx xxx 2D, 2S/4S shift = xxxxx - * 1xxx xxx RESERVED + * 0001 xxx 8H, 8B/16b shift = xxx + * 001x xxx 4S, 4H/8H shift = xxxx + * 01xx xxx 2D, 2S/4S shift = xxxxx + * 1xxx xxx RESERVED */ assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement"); assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value"); @@ -2288,12 +2288,12 @@ void uzp2(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T){ uzp1(Vd, Vn, Vm, T, 1); } - + // Move from general purpose register // mov Vd.T[index], Rn void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) { starti; - f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); + f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0); } @@ -2389,7 +2389,7 @@ }; inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a, - Assembler::Membar_mask_bits b) { + Assembler::Membar_mask_bits b) { return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b)); }
--- a/src/cpu/aarch64/vm/c1_CodeStubs_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/c1_CodeStubs_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -58,34 +58,34 @@ for (int i = 30; i >= 0; i -= 2) // caller-saved fp registers if (i < 8 || i > 15) __ stpd(as_FloatRegister(i), as_FloatRegister(i+1), - Address(__ pre(sp, -2 * wordSize))); + Address(__ pre(sp, -2 * wordSize))); switch(bytecode()) { case Bytecodes::_f2i: { if (v0 != input()->as_float_reg()) - __ fmovs(v0, input()->as_float_reg()); + __ fmovs(v0, input()->as_float_reg()); __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2i)); } break; case Bytecodes::_d2i: { if (v0 != input()->as_double_reg()) - __ fmovd(v0, input()->as_double_reg()); + __ fmovd(v0, input()->as_double_reg()); __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2i)); } break; case Bytecodes::_f2l: { if (v0 != input()->as_float_reg()) - __ fmovs(v0, input()->as_float_reg()); + __ fmovs(v0, input()->as_float_reg()); __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2l)); } break; case Bytecodes::_d2l: { if (v0 != input()->as_double_reg()) - __ fmovd(v0, input()->as_double_reg()); + __ fmovd(v0, input()->as_double_reg()); __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2l)); } break; @@ -98,7 +98,7 @@ for (int i = 0; i < 32; i += 2) if (i < 8 || i > 15) __ ldpd(as_FloatRegister(i), as_FloatRegister(i+1), - Address(__ post(sp, 2 * wordSize))); + Address(__ post(sp, 2 * wordSize))); __ pop(RegSet::range(r0, r29), sp); __ ldr(as_reg(result()), Address(rfp, -wordSize)); @@ -399,7 +399,7 @@ return; // CodeCache is full } Address resolve(SharedRuntime::get_resolve_static_call_stub(), - relocInfo::static_call_type); + relocInfo::static_call_type); address call = __ trampoline_call(resolve); if (call == NULL) { ce->bailout("trampoline stub overflow");
--- a/src/cpu/aarch64/vm/c1_Defs_aarch64.hpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/c1_Defs_aarch64.hpp Thu Apr 22 01:38:42 2021 +0100 @@ -59,7 +59,7 @@ pd_nof_cpu_regs_linearscan = 32, // number of registers visible to linear scan pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan - pd_nof_xmm_regs_linearscan = 0, // like sparc we don't have any of these + pd_nof_xmm_regs_linearscan = 0, // like sparc we don't have any of these pd_first_cpu_reg = 0, pd_last_cpu_reg = 16, pd_first_byte_reg = 0,
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -190,11 +190,11 @@ assert(addr->disp() == 0, "must be"); switch(opr->type()) { case T_INT: - return Address(base, index, Address::sxtw(addr->scale())); + return Address(base, index, Address::sxtw(addr->scale())); case T_LONG: - return Address(base, index, Address::lsl(addr->scale())); + return Address(base, index, Address::lsl(addr->scale())); default: - ShouldNotReachHere(); + ShouldNotReachHere(); } } else { intptr_t addr_offset = intptr_t(addr->disp()); @@ -626,20 +626,20 @@ case T_FLOAT: { if (__ operand_valid_for_float_immediate(c->as_jfloat())) { - __ fmovs(dest->as_float_reg(), (c->as_jfloat())); + __ fmovs(dest->as_float_reg(), (c->as_jfloat())); } else { - __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat()))); - __ ldrs(dest->as_float_reg(), Address(rscratch1)); + __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat()))); + __ ldrs(dest->as_float_reg(), Address(rscratch1)); } break; } case T_DOUBLE: { if (__ operand_valid_for_float_immediate(c->as_jdouble())) { - __ fmovd(dest->as_double_reg(), (c->as_jdouble())); + __ fmovd(dest->as_double_reg(), (c->as_jdouble())); } else { - __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble()))); - __ ldrd(dest->as_double_reg(), Address(rscratch1)); + __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble()))); + __ ldrd(dest->as_double_reg(), Address(rscratch1)); } break; } @@ -655,10 +655,10 @@ case T_OBJECT: { if (! c->as_jobject()) - __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix())); + __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix())); else { - const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL); - reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false); + const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL); + reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false); } } break; @@ -672,10 +672,10 @@ { Register reg = zr; if (c->as_jint_bits() == 0) - __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix())); + __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix())); else { - __ movw(rscratch1, c->as_jint_bits()); - __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix())); + __ movw(rscratch1, c->as_jint_bits()); + __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix())); } } break; @@ -684,12 +684,12 @@ { Register reg = zr; if (c->as_jlong_bits() == 0) - __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(), - lo_word_offset_in_bytes)); + __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(), + lo_word_offset_in_bytes)); else { - __ mov(rscratch1, (intptr_t)c->as_jlong_bits()); - __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(), - lo_word_offset_in_bytes)); + __ mov(rscratch1, (intptr_t)c->as_jlong_bits()); + __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(), + lo_word_offset_in_bytes)); } } break; @@ -1021,9 +1021,9 @@ // address that matches klass_offset_in_bytes() will be loaded // as a word, not a long. if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { - __ ldrw(dest->as_register(), as_Address(from_addr)); + __ ldrw(dest->as_register(), as_Address(from_addr)); } else { - __ ldr(dest->as_register(), as_Address(from_addr)); + __ ldr(dest->as_register(), as_Address(from_addr)); } break; case T_INT: @@ -1128,9 +1128,9 @@ // Assembler::EQ does not permit unordered branches, so we add // another branch here. Likewise, Assembler::NE does not permit // ordered branches. - if ((is_unordered && op->cond() == lir_cond_equal) - || (!is_unordered && op->cond() == lir_cond_notEqual)) - __ br(Assembler::VS, *(op->ublock()->label())); + if ((is_unordered && op->cond() == lir_cond_equal) + || (!is_unordered && op->cond() == lir_cond_notEqual)) + __ br(Assembler::VS, *(op->ublock()->label())); switch(op->cond()) { case lir_cond_equal: acond = Assembler::EQ; break; case lir_cond_notEqual: acond = Assembler::NE; break; @@ -1166,103 +1166,103 @@ switch (op->bytecode()) { case Bytecodes::_i2f: { - __ scvtfws(dest->as_float_reg(), src->as_register()); - break; + __ scvtfws(dest->as_float_reg(), src->as_register()); + break; } case Bytecodes::_i2d: { - __ scvtfwd(dest->as_double_reg(), src->as_register()); - break; + __ scvtfwd(dest->as_double_reg(), src->as_register()); + break; } case Bytecodes::_l2d: { - __ scvtfd(dest->as_double_reg(), src->as_register_lo()); - break; + __ scvtfd(dest->as_double_reg(), src->as_register_lo()); + break; } case Bytecodes::_l2f: { - __ scvtfs(dest->as_float_reg(), src->as_register_lo()); - break; + __ scvtfs(dest->as_float_reg(), src->as_register_lo()); + break; } case Bytecodes::_f2d: { - __ fcvts(dest->as_double_reg(), src->as_float_reg()); - break; + __ fcvts(dest->as_double_reg(), src->as_float_reg()); + break; } case Bytecodes::_d2f: { - __ fcvtd(dest->as_float_reg(), src->as_double_reg()); - break; + __ fcvtd(dest->as_float_reg(), src->as_double_reg()); + break; } case Bytecodes::_i2c: { - __ ubfx(dest->as_register(), src->as_register(), 0, 16); - break; + __ ubfx(dest->as_register(), src->as_register(), 0, 16); + break; } case Bytecodes::_i2l: { - __ sxtw(dest->as_register_lo(), src->as_register()); - break; + __ sxtw(dest->as_register_lo(), src->as_register()); + break; } case Bytecodes::_i2s: { - __ sxth(dest->as_register(), src->as_register()); - break; + __ sxth(dest->as_register(), src->as_register()); + break; } case Bytecodes::_i2b: { - __ sxtb(dest->as_register(), src->as_register()); - break; + __ sxtb(dest->as_register(), src->as_register()); + break; } case Bytecodes::_l2i: { - _masm->block_comment("FIXME: This could be a no-op"); - __ uxtw(dest->as_register(), src->as_register_lo()); - break; + _masm->block_comment("FIXME: This could be a no-op"); + __ uxtw(dest->as_register(), src->as_register_lo()); + break; } case Bytecodes::_d2l: { - Register tmp = op->tmp1()->as_register(); - __ clear_fpsr(); - __ fcvtzd(dest->as_register_lo(), src->as_double_reg()); - __ get_fpsr(tmp); - __ tst(tmp, 1); // FPSCR.IOC - __ br(Assembler::NE, *(op->stub()->entry())); - __ bind(*op->stub()->continuation()); - break; + Register tmp = op->tmp1()->as_register(); + __ clear_fpsr(); + __ fcvtzd(dest->as_register_lo(), src->as_double_reg()); + __ get_fpsr(tmp); + __ tst(tmp, 1); // FPSCR.IOC + __ br(Assembler::NE, *(op->stub()->entry())); + __ bind(*op->stub()->continuation()); + break; } case Bytecodes::_f2i: { - Register tmp = op->tmp1()->as_register(); - __ clear_fpsr(); - __ fcvtzsw(dest->as_register(), src->as_float_reg()); - __ get_fpsr(tmp); - __ tst(tmp, 1); // FPSCR.IOC - __ br(Assembler::NE, *(op->stub()->entry())); - __ bind(*op->stub()->continuation()); - break; + Register tmp = op->tmp1()->as_register(); + __ clear_fpsr(); + __ fcvtzsw(dest->as_register(), src->as_float_reg()); + __ get_fpsr(tmp); + __ tst(tmp, 1); // FPSCR.IOC + __ br(Assembler::NE, *(op->stub()->entry())); + __ bind(*op->stub()->continuation()); + break; } case Bytecodes::_f2l: { - Register tmp = op->tmp1()->as_register(); - __ clear_fpsr(); - __ fcvtzs(dest->as_register_lo(), src->as_float_reg()); - __ get_fpsr(tmp); - __ tst(tmp, 1); // FPSCR.IOC - __ br(Assembler::NE, *(op->stub()->entry())); - __ bind(*op->stub()->continuation()); - break; + Register tmp = op->tmp1()->as_register(); + __ clear_fpsr(); + __ fcvtzs(dest->as_register_lo(), src->as_float_reg()); + __ get_fpsr(tmp); + __ tst(tmp, 1); // FPSCR.IOC + __ br(Assembler::NE, *(op->stub()->entry())); + __ bind(*op->stub()->continuation()); + break; } case Bytecodes::_d2i: { - Register tmp = op->tmp1()->as_register(); - __ clear_fpsr(); - __ fcvtzdw(dest->as_register(), src->as_double_reg()); - __ get_fpsr(tmp); - __ tst(tmp, 1); // FPSCR.IOC - __ br(Assembler::NE, *(op->stub()->entry())); - __ bind(*op->stub()->continuation()); - break; + Register tmp = op->tmp1()->as_register(); + __ clear_fpsr(); + __ fcvtzdw(dest->as_register(), src->as_double_reg()); + __ get_fpsr(tmp); + __ tst(tmp, 1); // FPSCR.IOC + __ br(Assembler::NE, *(op->stub()->entry())); + __ bind(*op->stub()->continuation()); + break; } default: ShouldNotReachHere(); } @@ -1271,7 +1271,7 @@ void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { if (op->init_check()) { __ ldrb(rscratch1, Address(op->klass()->as_register(), - InstanceKlass::init_state_offset())); + InstanceKlass::init_state_offset())); __ cmpw(rscratch1, InstanceKlass::fully_initialized); add_debug_info_for_null_check_here(op->stub()->info()); __ br(Assembler::NE, *op->stub()->entry()); @@ -1339,7 +1339,7 @@ for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { Label next_test; __ lea(rscratch2, - Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); + Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); Address recv_addr(rscratch2); __ ldr(rscratch1, recv_addr); __ cbnz(rscratch1, next_test); @@ -1401,9 +1401,9 @@ Register mdo = klass_RInfo; __ mov_metadata(mdo, md->constant_encoding()); Address data_addr - = __ form_address(rscratch2, mdo, - md->byte_offset_of_slot(data, DataLayout::DataLayout::header_offset()), - LogBytesPerWord); + = __ form_address(rscratch2, mdo, + md->byte_offset_of_slot(data, DataLayout::DataLayout::header_offset()), + LogBytesPerWord); int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); __ ldr(rscratch1, data_addr); __ orr(rscratch1, rscratch1, header_bits); @@ -1449,11 +1449,11 @@ __ cmp(klass_RInfo, k_RInfo); __ br(Assembler::EQ, *success_target); - __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); + __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); - __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize))); + __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize))); // result is a boolean - __ cbzw(klass_RInfo, *failure_target); + __ cbzw(klass_RInfo, *failure_target); // successful cast, fall through to profile or jump } } else { @@ -1481,8 +1481,8 @@ __ mov_metadata(mdo, md->constant_encoding()); Address counter_addr = __ form_address(rscratch2, mdo, - md->byte_offset_of_slot(data, CounterData::count_offset()), - LogBytesPerWord); + md->byte_offset_of_slot(data, CounterData::count_offset()), + LogBytesPerWord); __ ldr(rscratch1, counter_addr); __ sub(rscratch1, rscratch1, DataLayout::counter_increment); __ str(rscratch1, counter_addr); @@ -1528,9 +1528,9 @@ Register mdo = klass_RInfo; __ mov_metadata(mdo, md->constant_encoding()); Address data_addr - = __ form_address(rscratch2, mdo, - md->byte_offset_of_slot(data, DataLayout::header_offset()), - LogBytesPerInt); + = __ form_address(rscratch2, mdo, + md->byte_offset_of_slot(data, DataLayout::header_offset()), + LogBytesPerInt); int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); __ ldrw(rscratch1, data_addr); __ orrw(rscratch1, rscratch1, header_bits); @@ -1658,7 +1658,7 @@ } assert(result->is_single_cpu() || result->is_double_cpu(), - "expect single register for result"); + "expect single register for result"); if (opr1->is_constant() && opr2->is_constant() && opr1->type() == T_INT && opr2->type() == T_INT) { jint val1 = opr1->as_jint(); @@ -1722,7 +1722,7 @@ // cpu register - cpu register assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT, - "should be"); + "should be"); Register rreg = right->as_register(); switch (code) { case lir_add: __ addw (dest->as_register(), lreg, rreg); break; @@ -1747,39 +1747,39 @@ // FIXME. This is fugly: we really need to factor all this logic. switch(right->type()) { case T_LONG: - c = right->as_constant_ptr()->as_jlong(); - break; + c = right->as_constant_ptr()->as_jlong(); + break; case T_INT: case T_ADDRESS: - c = right->as_constant_ptr()->as_jint(); - break; + c = right->as_constant_ptr()->as_jint(); + break; default: - ShouldNotReachHere(); - break; + ShouldNotReachHere(); + break; } assert(code == lir_add || code == lir_sub, "mismatched arithmetic op"); if (c == 0 && dreg == lreg) { - COMMENT("effective nop elided"); - return; + COMMENT("effective nop elided"); + return; } switch(left->type()) { case T_INT: - switch (code) { + switch (code) { case lir_add: __ addw(dreg, lreg, c); break; case lir_sub: __ subw(dreg, lreg, c); break; default: ShouldNotReachHere(); - } - break; + } + break; case T_OBJECT: case T_ADDRESS: - switch (code) { + switch (code) { case lir_add: __ add(dreg, lreg, c); break; case lir_sub: __ sub(dreg, lreg, c); break; default: ShouldNotReachHere(); - } - break; - ShouldNotReachHere(); + } + break; + ShouldNotReachHere(); } } else { ShouldNotReachHere(); @@ -1798,7 +1798,7 @@ case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break; case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break; default: - ShouldNotReachHere(); + ShouldNotReachHere(); } } else if (right->is_constant()) { @@ -1806,8 +1806,8 @@ Register dreg = as_reg(dest); assert(code == lir_add || code == lir_sub, "mismatched arithmetic op"); if (c == 0 && dreg == lreg_lo) { - COMMENT("effective nop elided"); - return; + COMMENT("effective nop elided"); + return; } switch (code) { case lir_add: __ add(dreg, lreg_lo, c); break; @@ -1841,11 +1841,11 @@ case lir_div_strictfp: // fall through case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; default: - ShouldNotReachHere(); + ShouldNotReachHere(); } } else { if (right->is_constant()) { - ShouldNotReachHere(); + ShouldNotReachHere(); } ShouldNotReachHere(); } @@ -1869,7 +1869,7 @@ } void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { - + assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register"); Register Rleft = left->is_single_cpu() ? left->as_register() : left->as_register_lo(); @@ -2120,8 +2120,8 @@ case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break; case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break; default: - ShouldNotReachHere(); - break; + ShouldNotReachHere(); + break; } break; case T_LONG: @@ -2132,8 +2132,8 @@ case lir_shr: __ asrv (dreg, lreg, count->as_register()); break; case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break; default: - ShouldNotReachHere(); - break; + ShouldNotReachHere(); + break; } break; default: @@ -2155,8 +2155,8 @@ case lir_shr: __ asrw (dreg, lreg, count); break; case lir_ushr: __ lsrw (dreg, lreg, count); break; default: - ShouldNotReachHere(); - break; + ShouldNotReachHere(); + break; } break; case T_LONG: @@ -2167,8 +2167,8 @@ case lir_shr: __ asr (dreg, lreg, count); break; case lir_ushr: __ lsr (dreg, lreg, count); break; default: - ShouldNotReachHere(); - break; + ShouldNotReachHere(); + break; } break; default: @@ -2376,10 +2376,10 @@ // safely do the copy. Label cont, slow; -#define PUSH(r1, r2) \ +#define PUSH(r1, r2) \ stp(r1, r2, __ pre(sp, -2 * wordSize)); -#define POP(r1, r2) \ +#define POP(r1, r2) \ ldp(r1, r2, __ post(sp, 2 * wordSize)); __ PUSH(src, dst); @@ -2416,23 +2416,23 @@ int lh_offset = in_bytes(Klass::layout_helper_offset()); Address klass_lh_addr(tmp, lh_offset); jint objArray_lh = Klass::array_layout_helper(T_OBJECT); - __ ldrw(rscratch1, klass_lh_addr); - __ mov(rscratch2, objArray_lh); + __ ldrw(rscratch1, klass_lh_addr); + __ mov(rscratch2, objArray_lh); __ eorw(rscratch1, rscratch1, rscratch2); __ cbnzw(rscratch1, *stub->entry()); } // Spill because stubs can use any register they like and it's // easier to restore just those that we care about. - __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord)); - __ stp(length, src_pos, Address(sp, 2*BytesPerWord)); - __ str(src, Address(sp, 4*BytesPerWord)); + __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord)); + __ stp(length, src_pos, Address(sp, 2*BytesPerWord)); + __ str(src, Address(sp, 4*BytesPerWord)); __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale))); - __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type)); + __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type)); assert_different_registers(c_rarg0, dst, dst_pos, length); __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale))); - __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type)); + __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type)); assert_different_registers(c_rarg1, dst, length); __ uxtw(c_rarg2, length); assert_different_registers(c_rarg2, dst); @@ -2458,19 +2458,19 @@ __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); } #endif - assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1); + assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1); // Restore previously spilled arguments - __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord)); - __ ldp(length, src_pos, Address(sp, 2*BytesPerWord)); - __ ldr(src, Address(sp, 4*BytesPerWord)); + __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord)); + __ ldp(length, src_pos, Address(sp, 2*BytesPerWord)); + __ ldr(src, Address(sp, 4*BytesPerWord)); // return value is -1^K where K is partial copied count __ eonw(rscratch1, r0, zr); // adjust length down and src/end pos up by partial copied count - __ subw(length, length, rscratch1); - __ addw(src_pos, src_pos, rscratch1); - __ addw(dst_pos, dst_pos, rscratch1); + __ subw(length, length, rscratch1); + __ addw(src_pos, src_pos, rscratch1); + __ addw(dst_pos, dst_pos, rscratch1); } __ b(*stub->entry()); @@ -2500,28 +2500,28 @@ if (basic_type != T_OBJECT) { if (UseCompressedClassPointers) { - __ ldrw(rscratch1, dst_klass_addr); - __ cmpw(tmp, rscratch1); + __ ldrw(rscratch1, dst_klass_addr); + __ cmpw(tmp, rscratch1); } else { - __ ldr(rscratch1, dst_klass_addr); - __ cmp(tmp, rscratch1); + __ ldr(rscratch1, dst_klass_addr); + __ cmp(tmp, rscratch1); } __ br(Assembler::NE, halt); if (UseCompressedClassPointers) { - __ ldrw(rscratch1, src_klass_addr); - __ cmpw(tmp, rscratch1); + __ ldrw(rscratch1, src_klass_addr); + __ cmpw(tmp, rscratch1); } else { - __ ldr(rscratch1, src_klass_addr); - __ cmp(tmp, rscratch1); + __ ldr(rscratch1, src_klass_addr); + __ cmp(tmp, rscratch1); } __ br(Assembler::EQ, known_ok); } else { if (UseCompressedClassPointers) { - __ ldrw(rscratch1, dst_klass_addr); - __ cmpw(tmp, rscratch1); + __ ldrw(rscratch1, dst_klass_addr); + __ cmpw(tmp, rscratch1); } else { - __ ldr(rscratch1, dst_klass_addr); - __ cmp(tmp, rscratch1); + __ ldr(rscratch1, dst_klass_addr); + __ cmp(tmp, rscratch1); } __ br(Assembler::EQ, known_ok); __ cmp(src, dst); @@ -2647,11 +2647,11 @@ ciKlass* receiver = vc_data->receiver(i); if (receiver == NULL) { Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); - __ mov_metadata(rscratch1, known_klass->constant_encoding()); - __ lea(rscratch2, recv_addr); + __ mov_metadata(rscratch1, known_klass->constant_encoding()); + __ lea(rscratch2, recv_addr); __ str(rscratch1, Address(rscratch2)); Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); - __ addptr(data_addr, DataLayout::counter_increment); + __ addptr(data_addr, DataLayout::counter_increment); return; } } @@ -2907,7 +2907,7 @@ void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { if (dest->is_address() || src->is_address()) { move_op(src, dest, type, lir_patch_none, info, - /*pop_fpu_stack*/false, /*unaligned*/false, /*wide*/false); + /*pop_fpu_stack*/false, /*unaligned*/false, /*wide*/false); } else { ShouldNotReachHere(); } @@ -3018,47 +3018,47 @@ start_insn = i; switch (op->code()) { case lir_cmp: - LIR_Opr opr1 = op->as_Op2()->in_opr1(); - LIR_Opr opr2 = op->as_Op2()->in_opr2(); - if (opr1->is_cpu_register() && opr1->is_single_cpu() - && opr2->is_constant() - && opr2->type() == T_INT) { - reg_opr = opr1; - reg = opr1->as_register(); - first_key = opr2->as_constant_ptr()->as_jint(); - next_key = first_key + 1; - state = cmp_s; - goto next_state; - } - break; + LIR_Opr opr1 = op->as_Op2()->in_opr1(); + LIR_Opr opr2 = op->as_Op2()->in_opr2(); + if (opr1->is_cpu_register() && opr1->is_single_cpu() + && opr2->is_constant() + && opr2->type() == T_INT) { + reg_opr = opr1; + reg = opr1->as_register(); + first_key = opr2->as_constant_ptr()->as_jint(); + next_key = first_key + 1; + state = cmp_s; + goto next_state; + } + break; } break; case cmp_s: switch (op->code()) { case lir_branch: - if (op->as_OpBranch()->cond() == lir_cond_equal) { - state = beq_s; - last_insn = i; - goto next_state; - } + if (op->as_OpBranch()->cond() == lir_cond_equal) { + state = beq_s; + last_insn = i; + goto next_state; + } } state = start_s; break; case beq_s: switch (op->code()) { case lir_cmp: { - LIR_Opr opr1 = op->as_Op2()->in_opr1(); - LIR_Opr opr2 = op->as_Op2()->in_opr2(); - if (opr1->is_cpu_register() && opr1->is_single_cpu() - && opr1->as_register() == reg - && opr2->is_constant() - && opr2->type() == T_INT - && opr2->as_constant_ptr()->as_jint() == next_key) { - last_key = next_key; - next_key++; - state = cmp_s; - goto next_state; - } + LIR_Opr opr1 = op->as_Op2()->in_opr1(); + LIR_Opr opr2 = op->as_Op2()->in_opr2(); + if (opr1->is_cpu_register() && opr1->is_single_cpu() + && opr1->as_register() == reg + && opr2->is_constant() + && opr2->type() == T_INT + && opr2->as_constant_ptr()->as_jint() == next_key) { + last_key = next_key; + next_key++; + state = cmp_s; + goto next_state; + } } } last_key = next_key; @@ -3069,44 +3069,44 @@ } if (state == start_s) { if (first_key < last_key - 5L && reg != noreg) { - { - // printf("found run register %d starting at insn %d low value %d high value %d\n", - // reg->encoding(), - // start_insn, first_key, last_key); - // for (int i = 0; i < inst->length(); i++) { - // inst->at(i)->print(); - // tty->print("\n"); - // } - // tty->print("\n"); - } - - struct tableswitch *sw = &switches[tableswitch_count]; - sw->_insn_index = start_insn, sw->_first_key = first_key, - sw->_last_key = last_key, sw->_reg = reg; - inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after)); - { - // Insert the new table of branches - int offset = last_insn; - for (int n = first_key; n < last_key; n++) { - inst->insert_before - (last_insn + 1, - new LIR_OpBranch(lir_cond_always, T_ILLEGAL, - inst->at(offset)->as_OpBranch()->label())); - offset -= 2, i++; - } - } - // Delete all the old compare-and-branch instructions - for (int n = first_key; n < last_key; n++) { - inst->remove_at(start_insn); - inst->remove_at(start_insn); - } - // Insert the tableswitch instruction - inst->insert_before(start_insn, - new LIR_Op2(lir_cmp, lir_cond_always, - LIR_OprFact::intConst(tableswitch_count), - reg_opr)); - inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches)); - tableswitch_count++; + { + // printf("found run register %d starting at insn %d low value %d high value %d\n", + // reg->encoding(), + // start_insn, first_key, last_key); + // for (int i = 0; i < inst->length(); i++) { + // inst->at(i)->print(); + // tty->print("\n"); + // } + // tty->print("\n"); + } + + struct tableswitch *sw = &switches[tableswitch_count]; + sw->_insn_index = start_insn, sw->_first_key = first_key, + sw->_last_key = last_key, sw->_reg = reg; + inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after)); + { + // Insert the new table of branches + int offset = last_insn; + for (int n = first_key; n < last_key; n++) { + inst->insert_before + (last_insn + 1, + new LIR_OpBranch(lir_cond_always, T_ILLEGAL, + inst->at(offset)->as_OpBranch()->label())); + offset -= 2, i++; + } + } + // Delete all the old compare-and-branch instructions + for (int n = first_key; n < last_key; n++) { + inst->remove_at(start_insn); + inst->remove_at(start_insn); + } + // Insert the tableswitch instruction + inst->insert_before(start_insn, + new LIR_Op2(lir_cmp, lir_cond_always, + LIR_OprFact::intConst(tableswitch_count), + reg_opr)); + inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches)); + tableswitch_count++; } reg = noreg; last_key = -2147483648;
--- a/src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -158,9 +158,9 @@ LIR_Opr tmp = new_pointer_register(); if (Assembler::operand_valid_for_add_sub_immediate(disp)) { __ add(tmp, tmp, LIR_OprFact::intptrConst(disp)); - index = tmp; + index = tmp; } else { - __ move(tmp, LIR_OprFact::intptrConst(disp)); + __ move(tmp, LIR_OprFact::intptrConst(disp)); __ add(tmp, index, tmp); index = tmp; } @@ -538,18 +538,18 @@ } else { assert (x->op() == Bytecodes::_lmul || x->op() == Bytecodes::_ladd || x->op() == Bytecodes::_lsub, - "expect lmul, ladd or lsub"); + "expect lmul, ladd or lsub"); // add, sub, mul left.load_item(); if (! right.is_register()) { if (x->op() == Bytecodes::_lmul || ! right.is_constant() - || ! Assembler::operand_valid_for_add_sub_immediate(right.get_jlong_constant())) { - right.load_item(); + || ! Assembler::operand_valid_for_add_sub_immediate(right.get_jlong_constant())) { + right.load_item(); } else { // add, sub - assert (x->op() == Bytecodes::_ladd || x->op() == Bytecodes::_lsub, "expect ladd or lsub"); - // don't load constants to save register - right.load_nonconstant(); + assert (x->op() == Bytecodes::_ladd || x->op() == Bytecodes::_lsub, "expect ladd or lsub"); + // don't load constants to save register + right.load_nonconstant(); } } rlock_result(x); @@ -593,7 +593,7 @@ } else if (x->op() == Bytecodes::_iadd || x->op() == Bytecodes::_isub) { if (right.is_constant() - && Assembler::operand_valid_for_add_sub_immediate(right.get_jint_constant())) { + && Assembler::operand_valid_for_add_sub_immediate(right.get_jint_constant())) { right.load_nonconstant(); } else { right.load_item(); @@ -605,10 +605,10 @@ if (right.is_constant()) { int c = right.get_jint_constant(); if (! is_power_of_2(c) && ! is_power_of_2(c + 1) && ! is_power_of_2(c - 1)) { - // Cannot use constant op. - right.load_item(); + // Cannot use constant op. + right.load_item(); } else { - right.dont_load_item(); + right.dont_load_item(); } } else { right.load_item(); @@ -647,7 +647,7 @@ rlock_result(x); if (right.is_constant()) { right.dont_load_item(); - + switch (x->op()) { case Bytecodes::_ishl: { int c = right.get_jint_constant() & 0x1f; @@ -733,9 +733,9 @@ rlock_result(x); if (right.is_constant() && ((right.type()->tag() == intTag - && Assembler::operand_valid_for_logical_immediate(true, right.get_jint_constant())) - || (right.type()->tag() == longTag - && Assembler::operand_valid_for_logical_immediate(false, right.get_jlong_constant())))) { + && Assembler::operand_valid_for_logical_immediate(true, right.get_jint_constant())) + || (right.type()->tag() == longTag + && Assembler::operand_valid_for_logical_immediate(false, right.get_jlong_constant())))) { right.dont_load_item(); } else { right.load_item(); @@ -832,7 +832,7 @@ LIR_Opr ill = LIR_OprFact::illegalOpr; // for convenience if (type == objectType) __ cas_obj(addr, cmp.result(), val.result(), new_register(T_INT), new_register(T_INT), - result); + result); else if (type == intType) __ cas_int(addr, cmp.result(), val.result(), ill, ill); else if (type == longType) @@ -1295,14 +1295,14 @@ if (tag == longTag) { if (yin->is_constant() - && Assembler::operand_valid_for_add_sub_immediate(yin->get_jlong_constant())) { + && Assembler::operand_valid_for_add_sub_immediate(yin->get_jlong_constant())) { yin->dont_load_item(); } else { yin->load_item(); } } else if (tag == intTag) { if (yin->is_constant() - && Assembler::operand_valid_for_add_sub_immediate(yin->get_jint_constant())) { + && Assembler::operand_valid_for_add_sub_immediate(yin->get_jint_constant())) { yin->dont_load_item(); } else { yin->load_item(); @@ -1376,7 +1376,7 @@ if (is_obj) { // Do the pre-write barrier, if any. pre_barrier(LIR_OprFact::address(addr), LIR_OprFact::illegalOpr /* pre_val */, - true /* do_load */, false /* patch */, NULL); + true /* do_load */, false /* patch */, NULL); __ move(data, addr); assert(src->is_register(), "must be register"); // Seems to be a precise address @@ -1397,8 +1397,8 @@ // We can cope with a constant increment in an xadd if (! (x->is_add() - && value.is_constant() - && can_inline_as_constant(x->value()))) { + && value.is_constant() + && can_inline_as_constant(x->value()))) { value.load_item(); } @@ -1434,7 +1434,7 @@ ptr = new_pointer_register(); __ add(src.result(), off.result(), ptr); pre_barrier(ptr, LIR_OprFact::illegalOpr /* pre_val */, - true /* do_load */, false /* patch */, NULL); + true /* do_load */, false /* patch */, NULL); } __ xchg(LIR_OprFact::address(addr), data, dst, tmp); if (is_obj) {
--- a/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -38,8 +38,8 @@ #include "runtime/stubRoutines.hpp" void C1_MacroAssembler::float_cmp(bool is_float, int unordered_result, - FloatRegister f0, FloatRegister f1, - Register result) + FloatRegister f0, FloatRegister f1, + Register result) { Label done; if (is_float) { @@ -337,7 +337,7 @@ sub(index, index, 1); for (int i = -unroll; i < 0; i++) { if (-i == remainder) - bind(entry_point); + bind(entry_point); str(zr, Address(rscratch1, i * wordSize)); } if (remainder == 0)
--- a/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.hpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.hpp Thu Apr 22 01:38:42 2021 +0100 @@ -53,8 +53,8 @@ void initialize_body(Register obj, Register len_in_bytes, int hdr_size_in_bytes, Register t1); void float_cmp(bool is_float, int unordered_result, - FloatRegister f0, FloatRegister f1, - Register result); + FloatRegister f0, FloatRegister f1, + Register result); // locking // hdr : must be r0, contents destroyed
--- a/src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -250,9 +250,9 @@ for (int i = 0; i < FrameMap::nof_fpu_regs; i++) { FloatRegister r = as_FloatRegister(i); { - int sp_offset = fpu_reg_save_offsets[i]; - oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset), - r->as_VMReg()); + int sp_offset = fpu_reg_save_offsets[i]; + oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset), + r->as_VMReg()); } } } @@ -268,7 +268,7 @@ if (save_fpu_registers) { for (int i = 30; i >= 0; i -= 2) __ stpd(as_FloatRegister(i), as_FloatRegister(i+1), - Address(__ pre(sp, -2 * wordSize))); + Address(__ pre(sp, -2 * wordSize))); } else { __ add(sp, sp, -32 * wordSize); } @@ -280,7 +280,7 @@ if (restore_fpu_registers) { for (int i = 0; i < 32; i += 2) __ ldpd(as_FloatRegister(i), as_FloatRegister(i+1), - Address(__ post(sp, 2 * wordSize))); + Address(__ post(sp, 2 * wordSize))); } else { __ add(sp, sp, 32 * wordSize); } @@ -293,7 +293,7 @@ if (restore_fpu_registers) { for (int i = 0; i < 32; i += 2) __ ldpd(as_FloatRegister(i), as_FloatRegister(i+1), - Address(__ post(sp, 2 * wordSize))); + Address(__ post(sp, 2 * wordSize))); } else { __ add(sp, sp, 32 * wordSize); } @@ -741,7 +741,7 @@ // if we got here then the TLAB allocation failed, so try // refilling the TLAB or allocating directly from eden. Label retry_tlab, try_eden; - __ tlab_refill(retry_tlab, try_eden, slow_path); // does not destroy r3 (klass), returns r5 + __ tlab_refill(retry_tlab, try_eden, slow_path); // does not destroy r3 (klass), returns r5 __ bind(retry_tlab); @@ -827,7 +827,7 @@ int tag = ((id == new_type_array_id) ? Klass::_lh_array_tag_type_value : Klass::_lh_array_tag_obj_value); - __ mov(rscratch1, tag); + __ mov(rscratch1, tag); __ cmpw(t0, rscratch1); __ br(Assembler::EQ, ok); __ stop("assert(is an array klass)"); @@ -844,7 +844,7 @@ assert_different_registers(length, klass, obj, arr_size, t1, t2); // check that array length is small enough for fast path. - __ mov(rscratch1, C1_MacroAssembler::max_array_allocation_length); + __ mov(rscratch1, C1_MacroAssembler::max_array_allocation_length); __ cmpw(length, rscratch1); __ br(Assembler::HI, slow_path); @@ -860,8 +860,8 @@ // since size is positive ldrw does right thing on 64bit __ ldrw(t1, Address(klass, Klass::layout_helper_offset())); __ lslvw(arr_size, length, t1); - __ ubfx(t1, t1, Klass::_lh_header_size_shift, - exact_log2(Klass::_lh_header_size_mask + 1)); + __ ubfx(t1, t1, Klass::_lh_header_size_shift, + exact_log2(Klass::_lh_header_size_mask + 1)); __ add(arr_size, arr_size, t1); __ add(arr_size, arr_size, MinObjAlignmentInBytesMask); // align up __ andr(arr_size, arr_size, ~MinObjAlignmentInBytesMask); @@ -888,8 +888,8 @@ // since size is postive movw does right thing on 64bit __ movw(arr_size, length); __ lslvw(arr_size, length, t1); - __ ubfx(t1, t1, Klass::_lh_header_size_shift, - exact_log2(Klass::_lh_header_size_mask + 1)); + __ ubfx(t1, t1, Klass::_lh_header_size_shift, + exact_log2(Klass::_lh_header_size_mask + 1)); __ add(arr_size, arr_size, t1); __ add(arr_size, arr_size, MinObjAlignmentInBytesMask); // align up __ andr(arr_size, arr_size, ~MinObjAlignmentInBytesMask); @@ -916,7 +916,7 @@ __ enter(); OopMap* map = save_live_registers(sasm); int call_offset; - if (id == new_type_array_id) { + if (id == new_type_array_id) { call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length); } else { call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length); @@ -940,9 +940,9 @@ // r19,: rank // r2: address of 1st dimension OopMap* map = save_live_registers(sasm); - __ mov(c_rarg1, r0); - __ mov(c_rarg3, r2); - __ mov(c_rarg2, r19); + __ mov(c_rarg1, r0); + __ mov(c_rarg3, r2); + __ mov(c_rarg2, r19); int call_offset = __ call_RT(r0, noreg, CAST_FROM_FN_PTR(address, new_multi_array), r1, r2, r3); oop_maps = new OopMapSet(); @@ -1007,7 +1007,7 @@ // __ bl(slow_subtype_check); // Note that the subclass is pushed first, and is therefore deepest. enum layout { - r0_off, r0_off_hi, + r0_off, r0_off_hi, r2_off, r2_off_hi, r4_off, r4_off_hi, r5_off, r5_off_hi, @@ -1018,26 +1018,26 @@ }; __ set_info("slow_subtype_check", dont_gc_arguments); - __ push(RegSet::of(r0, r2, r4, r5), sp); + __ push(RegSet::of(r0, r2, r4, r5), sp); // This is called by pushing args and not with C abi // __ ldr(r4, Address(sp, (klass_off) * VMRegImpl::stack_slot_size)); // subclass // __ ldr(r0, Address(sp, (sup_k_off) * VMRegImpl::stack_slot_size)); // superclass - __ ldp(r4, r0, Address(sp, (sup_k_off) * VMRegImpl::stack_slot_size)); + __ ldp(r4, r0, Address(sp, (sup_k_off) * VMRegImpl::stack_slot_size)); Label miss; __ check_klass_subtype_slow_path(r4, r0, r2, r5, NULL, &miss); // fallthrough on success: - __ mov(rscratch1, 1); + __ mov(rscratch1, 1); __ str(rscratch1, Address(sp, (result_off) * VMRegImpl::stack_slot_size)); // result - __ pop(RegSet::of(r0, r2, r4, r5), sp); + __ pop(RegSet::of(r0, r2, r4, r5), sp); __ ret(lr); __ bind(miss); __ str(zr, Address(sp, (result_off) * VMRegImpl::stack_slot_size)); // result - __ pop(RegSet::of(r0, r2, r4, r5), sp); + __ pop(RegSet::of(r0, r2, r4, r5), sp); __ ret(lr); } break; @@ -1179,9 +1179,9 @@ BarrierSet* bs = Universe::heap()->barrier_set(); if (bs->kind() != BarrierSet::G1SATBCTLogging) { - __ mov(r0, (int)id); - __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), r0); - __ should_not_reach_here(); + __ mov(r0, (int)id); + __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), r0); + __ should_not_reach_here(); break; } @@ -1207,8 +1207,8 @@ __ sub(tmp, tmp, wordSize); __ str(tmp, queue_index); __ ldr(rscratch2, buffer); - __ add(tmp, tmp, rscratch2); - f.load_argument(0, rscratch2); + __ add(tmp, tmp, rscratch2); + f.load_argument(0, rscratch2); __ str(rscratch2, Address(tmp, 0)); __ b(done); @@ -1255,13 +1255,13 @@ __ load_byte_map_base(byte_map_base); __ ldrb(rscratch1, Address(byte_map_base, card_offset)); __ cmpw(rscratch1, (int)G1SATBCardTableModRefBS::g1_young_card_val()); - __ br(Assembler::EQ, done); + __ br(Assembler::EQ, done); - assert((int)CardTableModRefBS::dirty_card_val() == 0, "must be 0"); + assert((int)CardTableModRefBS::dirty_card_val() == 0, "must be 0"); __ membar(Assembler::StoreLoad); __ ldrb(rscratch1, Address(byte_map_base, card_offset)); - __ cbzw(rscratch1, done); + __ cbzw(rscratch1, done); // storing region crossing non-NULL, card is clean. // dirty card and log. @@ -1279,9 +1279,9 @@ // Reuse LR to hold buffer_addr const Register buffer_addr = lr; - __ ldr(buffer_addr, buffer); - __ str(card_addr, Address(buffer_addr, rscratch1)); - __ b(done); + __ ldr(buffer_addr, buffer); + __ str(card_addr, Address(buffer_addr, rscratch1)); + __ b(done); __ bind(runtime); __ push_call_clobbered_registers();
--- a/src/cpu/aarch64/vm/frame_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/frame_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -733,11 +733,11 @@ #undef DESCRIBE_FP_OFFSET -#define DESCRIBE_FP_OFFSET(name) \ - { \ - unsigned long *p = (unsigned long *)fp; \ +#define DESCRIBE_FP_OFFSET(name) \ + { \ + unsigned long *p = (unsigned long *)fp; \ printf("0x%016lx 0x%016lx %s\n", (unsigned long)(p + frame::name##_offset), \ - p[frame::name##_offset], #name); \ + p[frame::name##_offset], #name); \ } static __thread unsigned long nextfp; @@ -807,11 +807,11 @@ CodeBlob *cb = CodeCache::find_blob((address)pc); if (cb != NULL) { if (cb->is_nmethod()) { - ResourceMark rm; - nmethod* nm = (nmethod*)cb; - printf("nmethod %s\n", nm->method()->name_and_sig_as_C_string()); + ResourceMark rm; + nmethod* nm = (nmethod*)cb; + printf("nmethod %s\n", nm->method()->name_and_sig_as_C_string()); } else if (cb->name()) { - printf("CodeBlob %s\n", cb->name()); + printf("CodeBlob %s\n", cb->name()); } } } @@ -829,7 +829,7 @@ } extern "C" void pf(unsigned long sp, unsigned long fp, unsigned long pc, - unsigned long bcx, unsigned long thread) { + unsigned long bcx, unsigned long thread) { if (!reg_map) { reg_map = NEW_C_HEAP_OBJ(RegisterMap, mtNone); ::new (reg_map) RegisterMap((JavaThread*)thread, false);
--- a/src/cpu/aarch64/vm/globals_aarch64.hpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/globals_aarch64.hpp Thu Apr 22 01:38:42 2021 +0100 @@ -77,9 +77,9 @@ #endif #define ARCH_FLAGS(develop, product, diagnostic, experimental, notproduct) \ - \ - product(bool, NearCpool, true, \ - "constant pool is close to instructions") \ + \ + product(bool, NearCpool, true, \ + "constant pool is close to instructions") \ \ product(bool, UseBarriersForVolatile, false, \ "Use memory barriers to implement volatile accesses") \
--- a/src/cpu/aarch64/vm/icache_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/icache_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -30,7 +30,7 @@ extern void aarch64TestHook(); void ICacheStubGenerator::generate_icache_flush( - ICache::flush_icache_stub_t* flush_icache_stub) { + ICache::flush_icache_stub_t* flush_icache_stub) { // Give anyone who calls this a surprise *flush_icache_stub = (ICache::flush_icache_stub_t)NULL; }
--- a/src/cpu/aarch64/vm/immediate_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/immediate_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -138,17 +138,17 @@ // construct a 32 bit immediate value for a logical immediate operation int expandLogicalImmediate(u_int32_t immN, u_int32_t immr, - u_int32_t imms, u_int64_t &bimm) + u_int32_t imms, u_int64_t &bimm) { - int len; // ought to be <= 6 - u_int32_t levels; // 6 bits - u_int32_t tmask_and; // 6 bits - u_int32_t wmask_and; // 6 bits - u_int32_t tmask_or; // 6 bits - u_int32_t wmask_or; // 6 bits - u_int64_t imm64; // 64 bits + int len; // ought to be <= 6 + u_int32_t levels; // 6 bits + u_int32_t tmask_and; // 6 bits + u_int32_t wmask_and; // 6 bits + u_int32_t tmask_or; // 6 bits + u_int32_t wmask_or; // 6 bits + u_int64_t imm64; // 64 bits u_int64_t tmask, wmask; // 64 bits - u_int32_t S, R, diff; // 6 bits? + u_int32_t S, R, diff; // 6 bits? if (immN == 1) { len = 6; // looks like 7 given the spec above but this cannot be! @@ -157,8 +157,8 @@ u_int32_t val = (~imms & 0x3f); for (int i = 5; i > 0; i--) { if (val & (1 << i)) { - len = i; - break; + len = i; + break; } } if (len < 1) { @@ -166,12 +166,12 @@ } // for valid inputs leading 1s in immr must be less than leading // zeros in imms - int len2 = 0; // ought to be < len + int len2 = 0; // ought to be < len u_int32_t val2 = (~immr & 0x3f); for (int i = 5; i > 0; i--) { if (!(val2 & (1 << i))) { - len2 = i; - break; + len2 = i; + break; } } if (len2 >= len) { @@ -187,7 +187,7 @@ S = imms & levels; R = immr & levels; - + // 6 bit arithmetic! diff = S - R; tmask_and = (diff | ~levels) & 0x3f; @@ -204,8 +204,8 @@ u_int64_t or_bits_top = (0 << nbits) | or_bits_sub; tmask = ((tmask - & (replicate(and_bits_top, 2 * nbits, 32 / nbits))) - | replicate(or_bits_top, 2 * nbits, 32 / nbits)); + & (replicate(and_bits_top, 2 * nbits, 32 / nbits))) + | replicate(or_bits_top, 2 * nbits, 32 / nbits)); } wmask_and = (immr | ~levels) & 0x3f; @@ -223,8 +223,8 @@ u_int64_t or_bits_top = (or_bits_sub << nbits) | 0; wmask = ((wmask - & (replicate(and_bits_top, 2 * nbits, 32 / nbits))) - | replicate(or_bits_top, 2 * nbits, 32 / nbits)); + & (replicate(and_bits_top, 2 * nbits, 32 / nbits))) + | replicate(or_bits_top, 2 * nbits, 32 / nbits)); } if (diff & (1U << 6)) { @@ -256,7 +256,7 @@ } // now sort the inverse table qsort(InverseLITable, li_table_entry_count, - sizeof(InverseLITable[0]), compare_immediate_pair); + sizeof(InverseLITable[0]), compare_immediate_pair); } // public APIs provided for logical immediate lookup and reverse lookup @@ -275,7 +275,7 @@ result = (struct li_pair *) bsearch(&pair, InverseLITable, li_table_entry_count, - sizeof(InverseLITable[0]), compare_immediate_pair); + sizeof(InverseLITable[0]), compare_immediate_pair); if (result) { return result->encoding; @@ -353,4 +353,3 @@ res = (s << 7) | (r << 4) | f; return res; } -
--- a/src/cpu/aarch64/vm/interp_masm_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/interp_masm_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -224,8 +224,8 @@ // little-endian machines allow us that. // n.b. unlike x86 cache already includes the index offset lea(bytecode, Address(cache, - ConstantPoolCache::base_offset() - + ConstantPoolCacheEntry::indices_offset())); + ConstantPoolCache::base_offset() + + ConstantPoolCacheEntry::indices_offset())); ldarw(bytecode, bytecode); const int shift_count = (1 + byte_no) * BitsPerByte; ubfx(bytecode, bytecode, shift_count, BitsPerByte); @@ -773,7 +773,7 @@ // Load the old header from BasicLock structure ldr(header_reg, Address(swap_reg, - BasicLock::displaced_header_offset_in_bytes())); + BasicLock::displaced_header_offset_in_bytes())); // Test for recursion cbz(header_reg, done); @@ -896,7 +896,7 @@ ldr(rscratch1, addr); subs(rscratch1, rscratch1, (unsigned)DataLayout::counter_increment); Label L; - br(Assembler::LO, L); // skip store if counter overflow + br(Assembler::LO, L); // skip store if counter overflow str(rscratch1, addr); bind(L); } else { @@ -911,7 +911,7 @@ ldr(rscratch1, addr); adds(rscratch1, rscratch1, DataLayout::counter_increment); Label L; - br(Assembler::CS, L); // skip store if counter overflow + br(Assembler::CS, L); // skip store if counter overflow str(rscratch1, addr); bind(L); } @@ -1008,7 +1008,7 @@ // so we do this adds(bumped_count, bumped_count, DataLayout::counter_increment); Label L; - br(Assembler::CS, L); // skip store if counter overflow + br(Assembler::CS, L); // skip store if counter overflow str(bumped_count, data); bind(L); // The method data pointer needs to be updated to reflect the new target. @@ -1036,7 +1036,7 @@ } -void InterpreterMacroAssembler::profile_call(Register mdp) { +void InterpreterMacroAssembler::profile_call(Register mdp) { if (ProfileInterpreter) { Label profile_continue; @@ -1155,14 +1155,14 @@ if (start_row == last_row) { // The only thing left to do is handle the null case. if (is_virtual_call) { - cbz(reg2, found_null); + cbz(reg2, found_null); // Receiver did not match any saved receiver and there is no empty row for it. // Increment total counter to indicate polymorphic case. increment_mdp_data_at(mdp, in_bytes(CounterData::count_offset())); b(done); bind(found_null); } else { - cbnz(reg2, done); + cbnz(reg2, done); } break; } @@ -1383,7 +1383,7 @@ #endif // !CC_INTERP -void InterpreterMacroAssembler::notify_method_entry() { +void InterpreterMacroAssembler::notify_method_entry() { // Whenever JVMTI is interp_only_mode, method entry/exit events are sent to // track stack depth. If it is possible to enter interp_only_mode we add // the code to check if the event should be sent. @@ -1452,7 +1452,7 @@ void InterpreterMacroAssembler::increment_mask_and_jump(Address counter_addr, int increment, int mask, Register scratch, Register scratch2, - bool preloaded, + bool preloaded, Condition cond, Label* where) { if (!preloaded) { ldrw(scratch, counter_addr);
--- a/src/cpu/aarch64/vm/interp_masm_aarch64.hpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/interp_masm_aarch64.hpp Thu Apr 22 01:38:42 2021 +0100 @@ -233,7 +233,7 @@ void increment_mask_and_jump(Address counter_addr, int increment, int mask, Register scratch, Register scratch2, - bool preloaded, + bool preloaded, Condition cond, Label* where); void set_mdp_flag_at(Register mdp_in, int flag_constant); void test_mdp_data_at(Register mdp_in, int offset, Register value,
--- a/src/cpu/aarch64/vm/interpreter_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/interpreter_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -276,7 +276,7 @@ { unsigned long offset; assert(SafepointSynchronize::_not_synchronized == 0, - "SafepointSynchronize::_not_synchronized"); + "SafepointSynchronize::_not_synchronized"); __ adrp(rscratch2, SafepointSynchronize::address_of_state(), offset); __ ldrw(rscratch2, Address(rscratch2, offset)); __ cbnz(rscratch2, slow_path);
--- a/src/cpu/aarch64/vm/jniFastGetField_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/jniFastGetField_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -73,7 +73,7 @@ unsigned long offset; __ adrp(rcounter_addr, - SafepointSynchronize::safepoint_counter_addr(), offset); + SafepointSynchronize::safepoint_counter_addr(), offset); Address safepoint_counter_addr(rcounter_addr, offset); __ ldrw(rcounter, safepoint_counter_addr); __ andw(rscratch1, rcounter, 1); @@ -177,4 +177,3 @@ address JNI_FastGetField::generate_fast_get_double_field() { return generate_fast_get_int_field0(T_DOUBLE); } -
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -118,21 +118,21 @@ // unsigned insn2 = ((unsigned*)branch)[1]; if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && - Instruction_aarch64::extract(insn, 4, 0) == - Instruction_aarch64::extract(insn2, 9, 5)) { - // Load/store register (unsigned immediate) - unsigned size = Instruction_aarch64::extract(insn2, 31, 30); - Instruction_aarch64::patch(branch + sizeof (unsigned), - 21, 10, offset_lo >> size); - guarantee(((dest >> size) << size) == dest, "misaligned target"); - instructions = 2; + Instruction_aarch64::extract(insn, 4, 0) == + Instruction_aarch64::extract(insn2, 9, 5)) { + // Load/store register (unsigned immediate) + unsigned size = Instruction_aarch64::extract(insn2, 31, 30); + Instruction_aarch64::patch(branch + sizeof (unsigned), + 21, 10, offset_lo >> size); + guarantee(((dest >> size) << size) == dest, "misaligned target"); + instructions = 2; } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && - Instruction_aarch64::extract(insn, 4, 0) == - Instruction_aarch64::extract(insn2, 4, 0)) { - // add (immediate) - Instruction_aarch64::patch(branch + sizeof (unsigned), - 21, 10, offset_lo); - instructions = 2; + Instruction_aarch64::extract(insn, 4, 0) == + Instruction_aarch64::extract(insn2, 4, 0)) { + // add (immediate) + Instruction_aarch64::patch(branch + sizeof (unsigned), + 21, 10, offset_lo); + instructions = 2; } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && Instruction_aarch64::extract(insn, 4, 0) == Instruction_aarch64::extract(insn2, 4, 0)) { @@ -238,12 +238,12 @@ // unsigned insn2 = ((unsigned*)insn_addr)[1]; if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && - Instruction_aarch64::extract(insn, 4, 0) == - Instruction_aarch64::extract(insn2, 9, 5)) { - // Load/store register (unsigned immediate) - unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); - unsigned int size = Instruction_aarch64::extract(insn2, 31, 30); - return address(target_page + (byte_offset << size)); + Instruction_aarch64::extract(insn, 4, 0) == + Instruction_aarch64::extract(insn2, 9, 5)) { + // Load/store register (unsigned immediate) + unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); + unsigned int size = Instruction_aarch64::extract(insn2, 31, 30); + return address(target_page + (byte_offset << size)); } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && Instruction_aarch64::extract(insn, 4, 0) == Instruction_aarch64::extract(insn2, 4, 0)) { @@ -257,7 +257,7 @@ target_page = (target_page & 0xffffffff) | ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32); } - return (address)target_page; + return (address)target_page; } } else { ShouldNotReachHere(); @@ -268,8 +268,8 @@ assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch"); assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch"); return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5)) - + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16) - + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32)); + + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16) + + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32)); } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { return 0; @@ -306,12 +306,12 @@ void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_java_fp, Register last_java_pc, - Register scratch) { + Register scratch) { if (last_java_pc->is_valid()) { str(last_java_pc, Address(rthread, - JavaThread::frame_anchor_offset() - + JavaFrameAnchor::last_Java_pc_offset())); + JavaThread::frame_anchor_offset() + + JavaFrameAnchor::last_Java_pc_offset())); } // determine last_java_sp register @@ -333,7 +333,7 @@ void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_java_fp, address last_java_pc, - Register scratch) { + Register scratch) { if (last_java_pc != NULL) { adr(scratch, last_java_pc); } else { @@ -344,8 +344,8 @@ } str(scratch, Address(rthread, - JavaThread::frame_anchor_offset() - + JavaFrameAnchor::last_Java_pc_offset())); + JavaThread::frame_anchor_offset() + + JavaFrameAnchor::last_Java_pc_offset())); set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch); } @@ -353,7 +353,7 @@ void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_java_fp, Label &L, - Register scratch) { + Register scratch) { if (L.is_bound()) { set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch); } else { @@ -605,11 +605,11 @@ } void MacroAssembler::call_VM_base(Register oop_result, - Register java_thread, - Register last_java_sp, - address entry_point, - int number_of_arguments, - bool check_exceptions) { + Register java_thread, + Register last_java_sp, + address entry_point, + int number_of_arguments, + bool check_exceptions) { // determine java_thread register if (!java_thread->is_valid()) { java_thread = rthread; @@ -1010,8 +1010,8 @@ if (vtable_index.is_register()) { lea(method_result, Address(recv_klass, - vtable_index.as_register(), - Address::lsl(LogBytesPerWord))); + vtable_index.as_register(), + Address::lsl(LogBytesPerWord))); ldr(method_result, Address(method_result, vtable_offset_in_bytes)); } else { vtable_offset_in_bytes += vtable_index.as_constant() * wordSize; @@ -1131,7 +1131,7 @@ // scans count pointer sized words at [addr] for occurence of value, // generic void MacroAssembler::repne_scan(Register addr, Register value, Register count, - Register scratch) { + Register scratch) { Label Lloop, Lexit; cbz(count, Lexit); bind(Lloop); @@ -1146,7 +1146,7 @@ // scans count 4 byte words at [addr] for occurence of value, // generic void MacroAssembler::repne_scanw(Register addr, Register value, Register count, - Register scratch) { + Register scratch) { Label Lloop, Lexit; cbz(count, Lexit); bind(Lloop); @@ -1322,17 +1322,17 @@ #endif if (arg_slot.is_constant()) { return Address(esp, arg_slot.as_constant() * stackElementSize - + offset); + + offset); } else { add(rscratch1, esp, arg_slot.as_register(), - ext::uxtx, exact_log2(stackElementSize)); + ext::uxtx, exact_log2(stackElementSize)); return Address(rscratch1, offset); } } void MacroAssembler::call_VM_leaf_base(address entry_point, int number_of_arguments, - Label *retaddr) { + Label *retaddr) { stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize))); // We add 1 to number_of_arguments because the thread in arg0 is @@ -1362,7 +1362,7 @@ } void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, - Register arg_1, Register arg_2) { + Register arg_1, Register arg_2) { pass_arg0(this, arg_0); pass_arg1(this, arg_1); pass_arg2(this, arg_2); @@ -1514,9 +1514,9 @@ for (i = 0; i < 4; i++) { imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL); if (imm_h[i] == 0) { - zero_count++; + zero_count++; } else if (imm_h[i] == 0xffffL) { - neg_count++; + neg_count++; } } if (zero_count == 4) { @@ -1527,80 +1527,80 @@ movn(dst, 0); } else if (zero_count == 3) { for (i = 0; i < 4; i++) { - if (imm_h[i] != 0L) { - movz(dst, (u_int32_t)imm_h[i], (i << 4)); - break; - } + if (imm_h[i] != 0L) { + movz(dst, (u_int32_t)imm_h[i], (i << 4)); + break; + } } } else if (neg_count == 3) { // one MOVN will do for (int i = 0; i < 4; i++) { - if (imm_h[i] != 0xffffL) { - movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); - break; - } + if (imm_h[i] != 0xffffL) { + movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); + break; + } } } else if (zero_count == 2) { // one MOVZ and one MOVK will do for (i = 0; i < 3; i++) { - if (imm_h[i] != 0L) { - movz(dst, (u_int32_t)imm_h[i], (i << 4)); - i++; - break; - } + if (imm_h[i] != 0L) { + movz(dst, (u_int32_t)imm_h[i], (i << 4)); + i++; + break; + } } for (;i < 4; i++) { - if (imm_h[i] != 0L) { - movk(dst, (u_int32_t)imm_h[i], (i << 4)); - } + if (imm_h[i] != 0L) { + movk(dst, (u_int32_t)imm_h[i], (i << 4)); + } } } else if (neg_count == 2) { // one MOVN and one MOVK will do for (i = 0; i < 4; i++) { - if (imm_h[i] != 0xffffL) { - movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); - i++; - break; - } + if (imm_h[i] != 0xffffL) { + movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); + i++; + break; + } } for (;i < 4; i++) { - if (imm_h[i] != 0xffffL) { - movk(dst, (u_int32_t)imm_h[i], (i << 4)); - } + if (imm_h[i] != 0xffffL) { + movk(dst, (u_int32_t)imm_h[i], (i << 4)); + } } } else if (zero_count == 1) { // one MOVZ and two MOVKs will do for (i = 0; i < 4; i++) { - if (imm_h[i] != 0L) { - movz(dst, (u_int32_t)imm_h[i], (i << 4)); - i++; - break; - } + if (imm_h[i] != 0L) { + movz(dst, (u_int32_t)imm_h[i], (i << 4)); + i++; + break; + } } for (;i < 4; i++) { - if (imm_h[i] != 0x0L) { - movk(dst, (u_int32_t)imm_h[i], (i << 4)); - } + if (imm_h[i] != 0x0L) { + movk(dst, (u_int32_t)imm_h[i], (i << 4)); + } } } else if (neg_count == 1) { // one MOVN and two MOVKs will do for (i = 0; i < 4; i++) { - if (imm_h[i] != 0xffffL) { - movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); - i++; - break; - } + if (imm_h[i] != 0xffffL) { + movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); + i++; + break; + } } for (;i < 4; i++) { - if (imm_h[i] != 0xffffL) { - movk(dst, (u_int32_t)imm_h[i], (i << 4)); - } + if (imm_h[i] != 0xffffL) { + movk(dst, (u_int32_t)imm_h[i], (i << 4)); + } } } else { // use a MOVZ and 3 MOVKs (makes it easier to debug) movz(dst, (u_int32_t)imm_h[0], 0); for (i = 1; i < 4; i++) { - movk(dst, (u_int32_t)imm_h[i], (i << 4)); + movk(dst, (u_int32_t)imm_h[i], (i << 4)); } } } @@ -1661,7 +1661,7 @@ unsigned long word_offset = byte_offset >> shift; unsigned long masked_offset = word_offset & 0xfff000; if (Address::offset_ok_for_immed(word_offset - masked_offset) - && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) { + && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) { add(Rd, base, masked_offset << shift); word_offset -= masked_offset; return Address(Rd, word_offset << shift); @@ -1694,7 +1694,7 @@ int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb, - bool want_remainder, Register scratch) + bool want_remainder, Register scratch) { // Full implementation of Java idiv and irem. The function // returns the (pc) offset of the div instruction - may be needed @@ -1724,7 +1724,7 @@ } int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb, - bool want_remainder, Register scratch) + bool want_remainder, Register scratch) { // Full implementation of Java ldiv and lrem. The function // returns the (pc) offset of the div instruction - may be needed @@ -2012,8 +2012,8 @@ // If a constant does not fit in an immediate field, generate some // number of MOV instructions and then perform the operation. void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, - add_sub_imm_insn insn1, - add_sub_reg_insn insn2) { + add_sub_imm_insn insn1, + add_sub_reg_insn insn2) { assert(Rd != zr, "Rd = zr and not setting flags?"); if (operand_valid_for_add_sub_immediate((int)imm)) { (this->*insn1)(Rd, Rn, imm); @@ -2032,8 +2032,8 @@ // Seperate vsn which sets the flags. Optimisations are more restricted // because we must set the flags correctly. void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, - add_sub_imm_insn insn1, - add_sub_reg_insn insn2) { + add_sub_imm_insn insn1, + add_sub_reg_insn insn2) { if (operand_valid_for_add_sub_immediate((int)imm)) { (this->*insn1)(Rd, Rn, imm); } else { @@ -2104,7 +2104,7 @@ // register+offset Address. void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, - Label &succeed, Label *fail) { + Label &succeed, Label *fail) { // oldv holds comparison value // newv holds value to write in exchange // addr identifies memory word to compare against/update @@ -2140,7 +2140,7 @@ } void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, - Label &succeed, Label *fail) { + Label &succeed, Label *fail) { // oldv holds comparison value // newv holds value to write in exchange // addr identifies memory word to compare against/update @@ -2392,7 +2392,7 @@ if (!save_vectors) { for (int i = 30; i >= 0; i -= 2) stpd(as_FloatRegister(i), as_FloatRegister(i+1), - Address(pre(sp, -2 * wordSize))); + Address(pre(sp, -2 * wordSize))); } else { for (int i = 30; i >= 0; i -= 2) stpq(as_FloatRegister(i), as_FloatRegister(i+1), @@ -3162,7 +3162,7 @@ cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift()); return; } else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 - && Universe::narrow_klass_shift() == 0) { + && Universe::narrow_klass_shift() == 0) { // Only the bottom 32 bits matter cmpw(trial_klass, tmp); return; @@ -3795,7 +3795,7 @@ if (TLABStats) { // increment number of slow_allocations addmw(Address(rthread, in_bytes(JavaThread::tlab_slow_allocations_offset())), - 1, rscratch1); + 1, rscratch1); } b(try_eden); @@ -3803,10 +3803,10 @@ if (TLABStats) { // increment number of refills addmw(Address(rthread, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1, - rscratch1); + rscratch1); // accumulate wastage -- t1 is amount free in tlab addmw(Address(rthread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1, - rscratch1); + rscratch1); } // if tlab is currently allocated (top or end != null) then @@ -3826,7 +3826,7 @@ unsigned long offset; // dubious reloc why not an oop reloc? adrp(rscratch1, ExternalAddress((address)Universe::intArrayKlassObj_addr()), - offset); + offset); ldr(t1, Address(rscratch1, offset)); } // store klass last. concurrent gcs assumes klass length is valid if @@ -4138,7 +4138,7 @@ // int i, j; // unsigned c; // unsigned char bc[ASIZE]; -// +// // /* Preprocessing */ // for (i = 0; i < ASIZE; ++i) // bc[i] = 0; @@ -4147,7 +4147,7 @@ // ++i; // if (c < ASIZE) bc[c] = i; // } -// +// // /* Searching */ // j = 0; // while (j <= n - m) { @@ -4679,8 +4679,8 @@ } void MacroAssembler::string_equals(Register str1, Register str2, - Register cnt, Register result, - Register tmp1) { + Register cnt, Register result, + Register tmp1) { Label SAME_CHARS, DONE, SHORT_LOOP, SHORT_STRING, NEXT_WORD; @@ -4815,21 +4815,21 @@ BIND(SAME); mov(result, true); - BIND(DIFFER); // result already set - + BIND(DIFFER); // result already set + BLOCK_COMMENT("} char_arrays_equals"); } // encode char[] to byte[] in ISO_8859_1 void MacroAssembler::encode_iso_array(Register src, Register dst, - Register len, Register result, - FloatRegister Vtmp1, FloatRegister Vtmp2, + Register len, Register result, + FloatRegister Vtmp1, FloatRegister Vtmp2, FloatRegister Vtmp3, FloatRegister Vtmp4) { Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1; Register tmp1 = rscratch1; - mov(result, len); // Save initial len + mov(result, len); // Save initial len subs(len, len, 32); br(LT, LOOP_8);
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp Thu Apr 22 01:38:42 2021 +0100 @@ -100,9 +100,9 @@ MacroAssembler(CodeBuffer* code) : Assembler(code) { use_XOR_for_compressed_class_base = (operand_valid_for_logical_immediate(false /*is32*/, - (uint64_t)Universe::narrow_klass_base()) - && ((uint64_t)Universe::narrow_klass_base() - > (1u << log2_intptr(CompressedClassSpaceSize)))); + (uint64_t)Universe::narrow_klass_base()) + && ((uint64_t)Universe::narrow_klass_base() + > (1u << log2_intptr(CompressedClassSpaceSize)))); } // Biased locking support @@ -553,9 +553,9 @@ // idiv variant which deals with MINLONG as dividend and -1 as divisor int corrected_idivl(Register result, Register ra, Register rb, - bool want_remainder, Register tmp = rscratch1); + bool want_remainder, Register tmp = rscratch1); int corrected_idivq(Register result, Register ra, Register rb, - bool want_remainder, Register tmp = rscratch1); + bool want_remainder, Register tmp = rscratch1); // Support for NULL-checks // @@ -572,7 +572,7 @@ unsigned insn = *(unsigned*)insn_addr; return target_addr_for_insn(insn_addr, insn); } - + // Required platform-specific helpers for Label::patch_instructions. // They _shadow_ the declarations in AbstractAssembler, which are undefined. static int pd_patch_instruction_size(address branch, address target); @@ -742,17 +742,17 @@ void set_last_Java_frame(Register last_java_sp, Register last_java_fp, address last_java_pc, - Register scratch); + Register scratch); void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Label &last_java_pc, - Register scratch); + Register scratch); void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Register last_java_pc, - Register scratch); + Register scratch); void reset_last_Java_frame(Register thread); @@ -971,10 +971,10 @@ void cmpptr(Register src1, Address src2); void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, - Label &suceed, Label *fail); + Label &suceed, Label *fail); void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, - Label &suceed, Label *fail); + Label &suceed, Label *fail); void atomic_add(Register prev, RegisterOrConstant incr, Register addr); void atomic_addw(Register prev, RegisterOrConstant incr, Register addr); @@ -1051,9 +1051,9 @@ void popa(); void repne_scan(Register addr, Register value, Register count, - Register scratch); + Register scratch); void repne_scanw(Register addr, Register value, Register count, - Register scratch); + Register scratch); typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm); typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift); @@ -1061,52 +1061,52 @@ // If a constant does not fit in an immediate field, generate some // number of MOV instructions and then perform the operation void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, - add_sub_imm_insn insn1, - add_sub_reg_insn insn2); + add_sub_imm_insn insn1, + add_sub_reg_insn insn2); // Seperate vsn which sets the flags void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, - add_sub_imm_insn insn1, - add_sub_reg_insn insn2); + add_sub_imm_insn insn1, + add_sub_reg_insn insn2); -#define WRAP(INSN) \ - void INSN(Register Rd, Register Rn, unsigned imm) { \ +#define WRAP(INSN) \ + void INSN(Register Rd, Register Rn, unsigned imm) { \ wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \ - } \ - \ - void INSN(Register Rd, Register Rn, Register Rm, \ - enum shift_kind kind, unsigned shift = 0) { \ - Assembler::INSN(Rd, Rn, Rm, kind, shift); \ - } \ - \ - void INSN(Register Rd, Register Rn, Register Rm) { \ - Assembler::INSN(Rd, Rn, Rm); \ - } \ - \ - void INSN(Register Rd, Register Rn, Register Rm, \ - ext::operation option, int amount = 0) { \ - Assembler::INSN(Rd, Rn, Rm, option, amount); \ + } \ + \ + void INSN(Register Rd, Register Rn, Register Rm, \ + enum shift_kind kind, unsigned shift = 0) { \ + Assembler::INSN(Rd, Rn, Rm, kind, shift); \ + } \ + \ + void INSN(Register Rd, Register Rn, Register Rm) { \ + Assembler::INSN(Rd, Rn, Rm); \ + } \ + \ + void INSN(Register Rd, Register Rn, Register Rm, \ + ext::operation option, int amount = 0) { \ + Assembler::INSN(Rd, Rn, Rm, option, amount); \ } WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw) #undef WRAP -#define WRAP(INSN) \ - void INSN(Register Rd, Register Rn, unsigned imm) { \ +#define WRAP(INSN) \ + void INSN(Register Rd, Register Rn, unsigned imm) { \ wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \ - } \ - \ - void INSN(Register Rd, Register Rn, Register Rm, \ - enum shift_kind kind, unsigned shift = 0) { \ - Assembler::INSN(Rd, Rn, Rm, kind, shift); \ - } \ - \ - void INSN(Register Rd, Register Rn, Register Rm) { \ - Assembler::INSN(Rd, Rn, Rm); \ - } \ - \ - void INSN(Register Rd, Register Rn, Register Rm, \ - ext::operation option, int amount = 0) { \ - Assembler::INSN(Rd, Rn, Rm, option, amount); \ + } \ + \ + void INSN(Register Rd, Register Rn, Register Rm, \ + enum shift_kind kind, unsigned shift = 0) { \ + Assembler::INSN(Rd, Rn, Rm, kind, shift); \ + } \ + \ + void INSN(Register Rd, Register Rn, Register Rm) { \ + Assembler::INSN(Rd, Rn, Rm); \ + } \ + \ + void INSN(Register Rd, Register Rn, Register Rm, \ + ext::operation option, int amount = 0) { \ + Assembler::INSN(Rd, Rn, Rm, option, amount); \ } WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw) @@ -1119,13 +1119,13 @@ void adrp(Register reg1, const Address &dest, unsigned long &byte_offset); void tableswitch(Register index, jint lowbound, jint highbound, - Label &jumptable, Label &jumptable_end, int stride = 1) { + Label &jumptable, Label &jumptable_end, int stride = 1) { adr(rscratch1, jumptable); subsw(rscratch2, index, lowbound); subsw(zr, rscratch2, highbound - lowbound); br(Assembler::HS, jumptable_end); add(rscratch1, rscratch1, rscratch2, - ext::sxtw, exact_log2(stride * Assembler::instruction_size)); + ext::sxtw, exact_log2(stride * Assembler::instruction_size)); br(rscratch1); } @@ -1174,11 +1174,11 @@ bool upper = false); void string_compare(Register str1, Register str2, - Register cnt1, Register cnt2, Register result, - Register tmp1); + Register cnt1, Register cnt2, Register result, + Register tmp1); void string_equals(Register str1, Register str2, - Register cnt, Register result, - Register tmp1); + Register cnt, Register result, + Register tmp1); void char_arrays_equals(Register ary1, Register ary2, Register result, Register tmp1); void fill_words(Register base, Register cnt, Register value);
--- a/src/cpu/aarch64/vm/methodHandles_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/methodHandles_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -310,7 +310,7 @@ __ verify_klass_ptr(temp2_defc); __ check_klass_subtype(temp1_recv_klass, temp2_defc, temp3, L_ok); // If we get here, the type check failed! - __ hlt(0); + __ hlt(0); // __ STOP("receiver class disagrees with MemberName.clazz"); __ bind(L_ok); }
--- a/src/cpu/aarch64/vm/nativeInst_aarch64.hpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/nativeInst_aarch64.hpp Thu Apr 22 01:38:42 2021 +0100 @@ -165,7 +165,7 @@ static void insert(address code_pos, address entry); static void replace_mt_safe(address instr_addr, address code_buffer); - + // Similar to replace_mt_safe, but just changes the destination. The // important thing is that free-running threads are able to execute // this call instruction at all times. If the call is an immediate BL
--- a/src/cpu/aarch64/vm/relocInfo_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/relocInfo_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -43,11 +43,11 @@ { oop_Relocation *reloc = (oop_Relocation *)this; if (NativeInstruction::is_ldr_literal_at(addr())) { - address constptr = (address)code()->oop_addr_at(reloc->oop_index()); - bytes = MacroAssembler::pd_patch_instruction_size(addr(), constptr); - assert(*(address*)constptr == x, "error in oop relocation"); + address constptr = (address)code()->oop_addr_at(reloc->oop_index()); + bytes = MacroAssembler::pd_patch_instruction_size(addr(), constptr); + assert(*(address*)constptr == x, "error in oop relocation"); } else{ - bytes = MacroAssembler::patch_oop(addr(), x); + bytes = MacroAssembler::patch_oop(addr(), x); } } break;
--- a/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -95,7 +95,7 @@ // the "natural" place and will override any oopMap // setting for it. We must therefore force the layout // so that it agrees with the frame sender code. - r0_off = fpu_state_off+FPUStateSizeInWords, + r0_off = fpu_state_off+FPUStateSizeInWords, rfp_off = r0_off + 30 * 2, return_off = rfp_off + 2, // slot for return address reg_save_size = return_off + 2}; @@ -140,9 +140,9 @@ Register r = as_Register(i); if (r < rheapbase && r != rscratch1 && r != rscratch2) { int sp_offset = 2 * (i + 32); // SP offsets are in 4-byte words, - // register slots are 8 bytes - // wide, 32 floating-point - // registers + // register slots are 8 bytes + // wide, 32 floating-point + // registers oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset + additional_frame_slots), r->as_VMReg()); } @@ -152,7 +152,7 @@ FloatRegister r = as_FloatRegister(i); int sp_offset = save_vectors ? (4 * i) : (2 * i); oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset), - r->as_VMReg()); + r->as_VMReg()); } return oop_map; @@ -364,7 +364,7 @@ for (int i = 0; i < total_args_passed; i++) { if (sig_bt[i] == T_VOID) { assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); - continue; + continue; } // offset to start parameters @@ -393,8 +393,8 @@ if (r_1->is_stack()) { // memory to memory use rscratch1 int ld_off = (r_1->reg2stack() * VMRegImpl::stack_slot_size - + extraspace - + words_pushed * wordSize); + + extraspace + + words_pushed * wordSize); if (!r_2->is_valid()) { // sign extend?? __ ldrw(rscratch1, Address(sp, ld_off)); @@ -1600,7 +1600,7 @@ freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding()] = true; } #endif - int_args++; + int_args++; break; } case T_OBJECT: @@ -1608,34 +1608,34 @@ object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], ((i == 0) && (!is_static)), &receiver_offset); - int_args++; + int_args++; break; case T_VOID: break; case T_FLOAT: float_move(masm, in_regs[i], out_regs[c_arg]); - float_args++; - break; + float_args++; + break; case T_DOUBLE: assert( i + 1 < total_in_args && in_sig_bt[i + 1] == T_VOID && out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); double_move(masm, in_regs[i], out_regs[c_arg]); - float_args++; + float_args++; break; case T_LONG : long_move(masm, in_regs[i], out_regs[c_arg]); - int_args++; + int_args++; break; case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); default: move32_64(masm, in_regs[i], out_regs[c_arg]); - int_args++; + int_args++; } } @@ -1648,8 +1648,8 @@ // load oop into a register __ movoop(c_rarg1, - JNIHandles::make_local(method->method_holder()->java_mirror()), - /*immediate*/true); + JNIHandles::make_local(method->method_holder()->java_mirror()), + /*immediate*/true); // Now handlize the static class mirror it's known not-null. __ str(c_rarg1, Address(sp, klass_offset)); @@ -2333,7 +2333,7 @@ #ifdef ASSERT0 { Label L; __ ldr(rscratch1, Address(rthread, - JavaThread::last_Java_fp_offset())); + JavaThread::last_Java_fp_offset())); __ cbz(rscratch1, L); __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared"); __ bind(L); @@ -2548,8 +2548,8 @@ __ mov(c_rarg0, rthread); __ lea(rscratch1, - RuntimeAddress(CAST_FROM_FN_PTR(address, - Deoptimization::uncommon_trap))); + RuntimeAddress(CAST_FROM_FN_PTR(address, + Deoptimization::uncommon_trap))); __ blr(rscratch1); __ bind(retaddr); @@ -2578,8 +2578,8 @@ // Pop deoptimized frame (int) __ ldrw(r2, Address(r4, - Deoptimization::UnrollBlock:: - size_of_deoptimized_frame_offset_in_bytes())); + Deoptimization::UnrollBlock:: + size_of_deoptimized_frame_offset_in_bytes())); __ sub(r2, r2, 2 * wordSize); __ add(sp, sp, r2); __ ldp(rfp, lr, __ post(sp, 2 * wordSize)); @@ -2588,24 +2588,24 @@ // Stack bang to make sure there's enough room for these interpreter frames. if (UseStackBanging) { __ ldrw(r1, Address(r4, - Deoptimization::UnrollBlock:: - total_frame_sizes_offset_in_bytes())); + Deoptimization::UnrollBlock:: + total_frame_sizes_offset_in_bytes())); __ bang_stack_size(r1, r2); } // Load address of array of frame pcs into r2 (address*) __ ldr(r2, Address(r4, - Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); + Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); // Load address of array of frame sizes into r5 (intptr_t*) __ ldr(r5, Address(r4, - Deoptimization::UnrollBlock:: - frame_sizes_offset_in_bytes())); + Deoptimization::UnrollBlock:: + frame_sizes_offset_in_bytes())); // Counter __ ldrw(r3, Address(r4, - Deoptimization::UnrollBlock:: - number_of_frames_offset_in_bytes())); // (int) + Deoptimization::UnrollBlock:: + number_of_frames_offset_in_bytes())); // (int) // Now adjust the caller's stack to make up for the extra locals but // record the original sp so that we can save it in the skeletal @@ -2616,29 +2616,29 @@ __ mov(sender_sp, sp); __ ldrw(r1, Address(r4, - Deoptimization::UnrollBlock:: - caller_adjustment_offset_in_bytes())); // (int) + Deoptimization::UnrollBlock:: + caller_adjustment_offset_in_bytes())); // (int) __ sub(sp, sp, r1); // Push interpreter frames in a loop Label loop; __ bind(loop); __ ldr(r1, Address(r5, 0)); // Load frame size - __ sub(r1, r1, 2 * wordSize); // We'll push pc and rfp by hand - __ ldr(lr, Address(r2, 0)); // Save return address - __ enter(); // and old rfp & set new rfp - __ sub(sp, sp, r1); // Prolog + __ sub(r1, r1, 2 * wordSize); // We'll push pc and rfp by hand + __ ldr(lr, Address(r2, 0)); // Save return address + __ enter(); // and old rfp & set new rfp + __ sub(sp, sp, r1); // Prolog __ str(sender_sp, Address(rfp, frame::interpreter_frame_sender_sp_offset * wordSize)); // Make it walkable // This value is corrected by layout_activation_impl __ str(zr, Address(rfp, frame::interpreter_frame_last_sp_offset * wordSize)); __ mov(sender_sp, sp); // Pass sender_sp to next frame - __ add(r5, r5, wordSize); // Bump array pointer (sizes) - __ add(r2, r2, wordSize); // Bump array pointer (pcs) - __ subsw(r3, r3, 1); // Decrement counter + __ add(r5, r5, wordSize); // Bump array pointer (sizes) + __ add(r2, r2, wordSize); // Bump array pointer (pcs) + __ subsw(r3, r3, 1); // Decrement counter __ br(Assembler::GT, loop); - __ ldr(lr, Address(r2, 0)); // save final return address + __ ldr(lr, Address(r2, 0)); // save final return address // Re-push self-frame - __ enter(); // & old rfp & set new rfp + __ enter(); // & old rfp & set new rfp // Use rfp because the frames look interpreted now // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
--- a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -604,24 +604,24 @@ case BarrierSet::G1SATBCTLogging: // With G1, don't generate the call if we statically know that the target in uninitialized if (!dest_uninitialized) { - __ push_call_clobbered_registers(); - if (count == c_rarg0) { - if (addr == c_rarg1) { - // exactly backwards!! + __ push_call_clobbered_registers(); + if (count == c_rarg0) { + if (addr == c_rarg1) { + // exactly backwards!! __ mov(rscratch1, c_rarg0); __ mov(c_rarg0, c_rarg1); __ mov(c_rarg1, rscratch1); - } else { - __ mov(c_rarg1, count); - __ mov(c_rarg0, addr); - } - } else { - __ mov(c_rarg0, addr); - __ mov(c_rarg1, count); - } - __ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_pre), 2); - __ pop_call_clobbered_registers(); - break; + } else { + __ mov(c_rarg1, count); + __ mov(c_rarg0, addr); + } + } else { + __ mov(c_rarg0, addr); + __ mov(c_rarg1, count); + } + __ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_pre), 2); + __ pop_call_clobbered_registers(); + break; case BarrierSet::CardTableModRef: case BarrierSet::CardTableExtension: case BarrierSet::ModRef: @@ -658,7 +658,7 @@ case BarrierSet::G1SATBCTLogging: { - __ push_call_clobbered_registers(); + __ push_call_clobbered_registers(); // must compute element count unless barrier set interface is changed (other platforms supply count) assert_different_registers(start, end, scratch); __ lea(scratch, Address(end, BytesPerHeapOop)); @@ -667,7 +667,7 @@ __ mov(c_rarg0, start); __ mov(c_rarg1, scratch); __ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_post), 2); - __ pop_call_clobbered_registers(); + __ pop_call_clobbered_registers(); } break; case BarrierSet::CardTableModRef: @@ -688,8 +688,8 @@ if (UseConcMarkSweepGC) { __ membar(__ StoreStore); } - __ BIND(L_loop); - __ strb(zr, Address(start, count)); + __ BIND(L_loop); + __ strb(zr, Address(start, count)); __ subs(count, count, 1); __ br(Assembler::GE, L_loop); } @@ -762,7 +762,7 @@ // s and d are adjusted to point to the remaining words to copy // void generate_copy_longs(Label &start, Register s, Register d, Register count, - copy_direction direction) { + copy_direction direction) { int unit = wordSize * direction; int bias = (UseSIMDForMemoryOps ? 4:2) * wordSize; @@ -1100,7 +1100,7 @@ Label Lpair, Lword, Lint, Lshort, Lbyte; assert(granularity - && granularity <= sizeof (jlong), "Impossible granularity in copy_memory_small"); + && granularity <= sizeof (jlong), "Impossible granularity in copy_memory_small"); const Register t0 = r3, t1 = r4, t2 = r5, t3 = r6; @@ -1146,7 +1146,7 @@ // void copy_memory(bool is_aligned, Register s, Register d, - Register count, Register tmp, int step) { + Register count, Register tmp, int step) { copy_direction direction = step < 0 ? copy_backwards : copy_forwards; bool is_backwards = step < 0; int granularity = uabs(step); @@ -1217,7 +1217,7 @@ __ ldp(t4, t5, Address(s, 32)); __ ldp(t6, t7, Address(s, 48)); __ ldp(t8, t9, Address(send, -16)); - + __ stp(t0, t1, Address(d, 0)); __ stp(t2, t3, Address(d, 16)); __ stp(t4, t5, Address(d, 32)); @@ -1292,10 +1292,10 @@ __ sub(count, count, wordSize/granularity); } else { if (is_backwards) { - __ andr(rscratch2, s, 2 * wordSize - 1); + __ andr(rscratch2, s, 2 * wordSize - 1); } else { - __ neg(rscratch2, s); - __ andr(rscratch2, rscratch2, 2 * wordSize - 1); + __ neg(rscratch2, s); + __ andr(rscratch2, rscratch2, 2 * wordSize - 1); } // rscratch2 is the byte adjustment needed to align s. __ cbz(rscratch2, aligned); @@ -1313,11 +1313,11 @@ // Align s and d, adjust count if (is_backwards) { - __ sub(s, s, rscratch2); - __ sub(d, d, rscratch2); + __ sub(s, s, rscratch2); + __ sub(d, d, rscratch2); } else { - __ add(s, s, rscratch2); - __ add(d, d, rscratch2); + __ add(s, s, rscratch2); + __ add(d, d, rscratch2); } #else copy_memory_small(s, d, rscratch2, rscratch1, step); @@ -1395,7 +1395,7 @@ // used by generate_conjoint_int_oop_copy(). // address generate_disjoint_copy(size_t size, bool aligned, bool is_oop, address *entry, - const char *name, bool dest_uninitialized = false) { + const char *name, bool dest_uninitialized = false) { Register s = c_rarg0, d = c_rarg1, count = c_rarg2; __ align(CodeEntryAlignment); StubCodeMark mark(this, "StubRoutines", name); @@ -1417,7 +1417,7 @@ if (is_oop) { __ pop(RegSet::of(d, count), sp); if (VerifyOops) - verify_oop_array(size, d, count, r16); + verify_oop_array(size, d, count, r16); __ sub(count, count, 1); // make an inclusive end pointer __ lea(count, Address(d, count, Address::lsl(exact_log2(size)))); gen_write_ref_array_post_barrier(d, count, rscratch1); @@ -1444,8 +1444,8 @@ // cache line boundaries will still be loaded and stored atomicly. // address generate_conjoint_copy(size_t size, bool aligned, bool is_oop, address nooverlap_target, - address *entry, const char *name, - bool dest_uninitialized = false) { + address *entry, const char *name, + bool dest_uninitialized = false) { Register s = c_rarg0, d = c_rarg1, count = c_rarg2; StubCodeMark mark(this, "StubRoutines", name); @@ -1473,7 +1473,7 @@ if (is_oop) { __ pop(RegSet::of(d, count), sp); if (VerifyOops) - verify_oop_array(size, d, count, r16); + verify_oop_array(size, d, count, r16); __ sub(count, count, 1); // make an inclusive end pointer __ lea(count, Address(d, count, Address::lsl(exact_log2(size)))); gen_write_ref_array_post_barrier(d, count, rscratch1); @@ -1556,7 +1556,7 @@ // used by generate_conjoint_short_copy(). // address generate_disjoint_short_copy(bool aligned, - address* entry, const char *name) { + address* entry, const char *name) { const bool not_oop = false; return generate_disjoint_copy(sizeof (jshort), aligned, not_oop, entry, name); } @@ -1601,7 +1601,7 @@ // used by generate_conjoint_int_oop_copy(). // address generate_disjoint_int_copy(bool aligned, address *entry, - const char *name, bool dest_uninitialized = false) { + const char *name, bool dest_uninitialized = false) { const bool not_oop = false; return generate_disjoint_copy(sizeof (jint), aligned, not_oop, entry, name); } @@ -1621,8 +1621,8 @@ // cache line boundaries will still be loaded and stored atomicly. // address generate_conjoint_int_copy(bool aligned, address nooverlap_target, - address *entry, const char *name, - bool dest_uninitialized = false) { + address *entry, const char *name, + bool dest_uninitialized = false) { const bool not_oop = false; return generate_conjoint_copy(sizeof (jint), aligned, not_oop, nooverlap_target, entry, name); } @@ -1659,8 +1659,8 @@ // c_rarg2 - element count, treated as size_t, can be zero // address generate_conjoint_long_copy(bool aligned, - address nooverlap_target, address *entry, - const char *name, bool dest_uninitialized = false) { + address nooverlap_target, address *entry, + const char *name, bool dest_uninitialized = false) { const bool not_oop = false; return generate_conjoint_copy(sizeof (jlong), aligned, not_oop, nooverlap_target, entry, name); } @@ -1680,7 +1680,7 @@ // no-overlap entry point used by generate_conjoint_long_oop_copy(). // address generate_disjoint_oop_copy(bool aligned, address *entry, - const char *name, bool dest_uninitialized) { + const char *name, bool dest_uninitialized) { const bool is_oop = true; const size_t size = UseCompressedOops ? sizeof (jint) : sizeof (jlong); return generate_disjoint_copy(size, aligned, is_oop, entry, name, dest_uninitialized); @@ -1697,8 +1697,8 @@ // c_rarg2 - element count, treated as size_t, can be zero // address generate_conjoint_oop_copy(bool aligned, - address nooverlap_target, address *entry, - const char *name, bool dest_uninitialized) { + address nooverlap_target, address *entry, + const char *name, bool dest_uninitialized) { const bool is_oop = true; const size_t size = UseCompressedOops ? sizeof (jint) : sizeof (jlong); return generate_conjoint_copy(size, aligned, is_oop, nooverlap_target, entry, @@ -1766,7 +1766,7 @@ // checked. assert_different_registers(from, to, count, ckoff, ckval, start_to, - copied_oop, r19_klass, count_save); + copied_oop, r19_klass, count_save); __ align(CodeEntryAlignment); StubCodeMark mark(this, "StubRoutines", name); @@ -2423,23 +2423,23 @@ //*** jint // Aligned versions StubRoutines::_arrayof_jint_disjoint_arraycopy = generate_disjoint_int_copy(true, &entry, - "arrayof_jint_disjoint_arraycopy"); + "arrayof_jint_disjoint_arraycopy"); StubRoutines::_arrayof_jint_arraycopy = generate_conjoint_int_copy(true, entry, &entry_jint_arraycopy, - "arrayof_jint_arraycopy"); + "arrayof_jint_arraycopy"); // In 64 bit we need both aligned and unaligned versions of jint arraycopy. // entry_jint_arraycopy always points to the unaligned version StubRoutines::_jint_disjoint_arraycopy = generate_disjoint_int_copy(false, &entry, - "jint_disjoint_arraycopy"); + "jint_disjoint_arraycopy"); StubRoutines::_jint_arraycopy = generate_conjoint_int_copy(false, entry, - &entry_jint_arraycopy, - "jint_arraycopy"); + &entry_jint_arraycopy, + "jint_arraycopy"); //*** jlong // It is always aligned StubRoutines::_arrayof_jlong_disjoint_arraycopy = generate_disjoint_long_copy(true, &entry, - "arrayof_jlong_disjoint_arraycopy"); + "arrayof_jlong_disjoint_arraycopy"); StubRoutines::_arrayof_jlong_arraycopy = generate_conjoint_long_copy(true, entry, &entry_jlong_arraycopy, - "arrayof_jlong_arraycopy"); + "arrayof_jlong_arraycopy"); StubRoutines::_jlong_disjoint_arraycopy = StubRoutines::_arrayof_jlong_disjoint_arraycopy; StubRoutines::_jlong_arraycopy = StubRoutines::_arrayof_jlong_arraycopy; @@ -2450,18 +2450,18 @@ bool aligned = !UseCompressedOops; StubRoutines::_arrayof_oop_disjoint_arraycopy - = generate_disjoint_oop_copy(aligned, &entry, "arrayof_oop_disjoint_arraycopy", + = generate_disjoint_oop_copy(aligned, &entry, "arrayof_oop_disjoint_arraycopy", /*dest_uninitialized*/false); StubRoutines::_arrayof_oop_arraycopy - = generate_conjoint_oop_copy(aligned, entry, &entry_oop_arraycopy, "arrayof_oop_arraycopy", + = generate_conjoint_oop_copy(aligned, entry, &entry_oop_arraycopy, "arrayof_oop_arraycopy", /*dest_uninitialized*/false); // Aligned versions without pre-barriers StubRoutines::_arrayof_oop_disjoint_arraycopy_uninit - = generate_disjoint_oop_copy(aligned, &entry, "arrayof_oop_disjoint_arraycopy_uninit", - /*dest_uninitialized*/true); + = generate_disjoint_oop_copy(aligned, &entry, "arrayof_oop_disjoint_arraycopy_uninit", + /*dest_uninitialized*/true); StubRoutines::_arrayof_oop_arraycopy_uninit - = generate_conjoint_oop_copy(aligned, entry, NULL, "arrayof_oop_arraycopy_uninit", - /*dest_uninitialized*/true); + = generate_conjoint_oop_copy(aligned, entry, NULL, "arrayof_oop_arraycopy_uninit", + /*dest_uninitialized*/true); } StubRoutines::_oop_disjoint_arraycopy = StubRoutines::_arrayof_oop_disjoint_arraycopy; @@ -3144,11 +3144,11 @@ switch (size) { case 4: // int32_t - __ ldrw(c_rarg1, Address(c_rarg0, 0)); + __ ldrw(c_rarg1, Address(c_rarg0, 0)); break; case 8: // int64_t - __ ldr(c_rarg1, Address(c_rarg0, 0)); + __ ldr(c_rarg1, Address(c_rarg0, 0)); break; default: ShouldNotReachHere();
--- a/src/cpu/aarch64/vm/stubRoutines_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/stubRoutines_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -270,8 +270,8 @@ // Constants for Neon CRC232 implementation // k3 = 0x78ED02D5 = x^288 mod poly - bit reversed // k4 = 0xED627DAE = x^256 mod poly - bit reversed - 0x78ED02D5UL, 0xED627DAEUL, // k4:k3 - 0xED78D502UL, 0x62EDAE7DUL, // byte swap - 0x02D578EDUL, 0x7DAEED62UL, // word swap - 0xD502ED78UL, 0xAE7D62EDUL, // byte swap of word swap + 0x78ED02D5UL, 0xED627DAEUL, // k4:k3 + 0xED78D502UL, 0x62EDAE7DUL, // byte swap + 0x02D578EDUL, 0x7DAEED62UL, // word swap + 0xD502ED78UL, 0xAE7D62EDUL, // byte swap of word swap };
--- a/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -69,8 +69,8 @@ { Label L; __ ldr(rscratch1, Address(rfp, - frame::interpreter_frame_monitor_block_top_offset * - wordSize)); + frame::interpreter_frame_monitor_block_top_offset * + wordSize)); __ mov(rscratch2, sp); __ cmp(rscratch1, rscratch2); // maximal rsp for current rfp (stack // grows negative) @@ -144,8 +144,8 @@ __ lea(c_rarg1, Address((address)name)); if (pass_oop) { __ call_VM(r0, CAST_FROM_FN_PTR(address, - InterpreterRuntime:: - create_klass_exception), + InterpreterRuntime:: + create_klass_exception), c_rarg1, c_rarg2); } else { // kind of lame ExternalAddress can't take NULL because @@ -196,7 +196,7 @@ __ ldrh(rscratch1, Address(rscratch1, ConstMethod::max_stack_offset())); __ add(rscratch1, rscratch1, frame::interpreter_frame_monitor_size() + 2); __ ldr(rscratch2, - Address(rfp, frame::interpreter_frame_initial_sp_offset * wordSize)); + Address(rfp, frame::interpreter_frame_initial_sp_offset * wordSize)); __ sub(rscratch1, rscratch2, rscratch1, ext::uxtw, 3); __ andr(sp, rscratch1, -16); @@ -219,9 +219,9 @@ __ ldr(rscratch1, Address(rmethod, Method::const_offset())); __ ldrh(rscratch1, Address(rscratch1, ConstMethod::max_stack_offset())); __ add(rscratch1, rscratch1, frame::interpreter_frame_monitor_size() - + (EnableInvokeDynamic ? 2 : 0)); + + (EnableInvokeDynamic ? 2 : 0)); __ ldr(rscratch2, - Address(rfp, frame::interpreter_frame_initial_sp_offset * wordSize)); + Address(rfp, frame::interpreter_frame_initial_sp_offset * wordSize)); __ sub(rscratch1, rscratch2, rscratch1, ext::uxtx, 3); __ andr(sp, rscratch1, -16); @@ -376,7 +376,7 @@ // Test to see if we should create a method data oop unsigned long offset; __ adrp(rscratch2, ExternalAddress((address)&InvocationCounter::InterpreterProfileLimit), - offset); + offset); __ ldrw(rscratch2, Address(rscratch2, offset)); __ cmp(r0, rscratch2); __ br(Assembler::LT, *profile_method_continue); @@ -388,8 +388,8 @@ { unsigned long offset; __ adrp(rscratch2, - ExternalAddress((address)&InvocationCounter::InterpreterInvocationLimit), - offset); + ExternalAddress((address)&InvocationCounter::InterpreterInvocationLimit), + offset); __ ldrw(rscratch2, Address(rscratch2, offset)); __ cmpw(r0, rscratch2); __ br(Assembler::HS, *overflow); @@ -637,7 +637,7 @@ __ ldr(rscratch1, Address(rmethod, Method::const_offset())); __ ldrh(rscratch1, Address(rscratch1, ConstMethod::max_stack_offset())); __ add(rscratch1, rscratch1, frame::interpreter_frame_monitor_size() - + (EnableInvokeDynamic ? 2 : 0)); + + (EnableInvokeDynamic ? 2 : 0)); __ sub(rscratch1, sp, rscratch1, ext::uxtw, 3); __ andr(sp, rscratch1, -16); } @@ -879,7 +879,7 @@ const Address constMethod (rmethod, Method::const_offset()); const Address access_flags (rmethod, Method::access_flags_offset()); const Address size_of_parameters(r2, ConstMethod:: - size_of_parameters_offset()); + size_of_parameters_offset()); // get parameter size (always needed) __ ldr(r2, constMethod); @@ -1137,7 +1137,7 @@ __ ldrw(rscratch2, Address(rscratch2, offset)); } assert(SafepointSynchronize::_not_synchronized == 0, - "SafepointSynchronize::_not_synchronized"); + "SafepointSynchronize::_not_synchronized"); Label L; __ cbnz(rscratch2, L); __ ldrw(rscratch2, Address(rthread, JavaThread::suspend_flags_offset())); @@ -1232,7 +1232,7 @@ // restore bcp to have legal interpreter frame, i.e., bci == 0 <=> // rbcp == code_base() - __ ldr(rbcp, Address(rmethod, Method::const_offset())); // get ConstMethod* + __ ldr(rbcp, Address(rmethod, Method::const_offset())); // get ConstMethod* __ add(rbcp, rbcp, in_bytes(ConstMethod::codes_offset())); // get codebase // handle exceptions (exception handling will handle unlocking!) { @@ -1266,8 +1266,8 @@ // monitor expect in c_rarg1 for slow unlock path __ lea (c_rarg1, Address(rfp, // address of first monitor - (intptr_t)(frame::interpreter_frame_initial_sp_offset * - wordSize - sizeof(BasicObjectLock)))); + (intptr_t)(frame::interpreter_frame_initial_sp_offset * + wordSize - sizeof(BasicObjectLock)))); __ ldr(t, Address(c_rarg1, BasicObjectLock::obj_offset_in_bytes())); __ cbnz(t, unlock); @@ -1301,8 +1301,8 @@ // remove activation __ ldr(esp, Address(rfp, - frame::interpreter_frame_sender_sp_offset * - wordSize)); // get sender sp + frame::interpreter_frame_sender_sp_offset * + wordSize)); // get sender sp // remove frame anchor __ leave(); @@ -1757,7 +1757,7 @@ __ add(rscratch1, rscratch1, frame::interpreter_frame_monitor_size() + (EnableInvokeDynamic ? 2 : 0) + 2); __ ldr(rscratch2, - Address(rfp, frame::interpreter_frame_initial_sp_offset * wordSize)); + Address(rfp, frame::interpreter_frame_initial_sp_offset * wordSize)); __ sub(rscratch1, rscratch2, rscratch1, ext::uxtx, 3); __ andr(sp, rscratch1, -16); @@ -1812,7 +1812,7 @@ __ get_method(r0); __ ldr(r0, Address(r0, Method::const_offset())); __ load_unsigned_short(r0, Address(r0, in_bytes(ConstMethod:: - size_of_parameters_offset()))); + size_of_parameters_offset()))); __ lsl(r0, r0, Interpreter::logStackElementSize); __ restore_locals(); // XXX do we need this? __ sub(rlocals, rlocals, r0); @@ -1889,9 +1889,9 @@ __ ldr(rscratch1, Address(rmethod, Method::const_offset())); __ ldrh(rscratch1, Address(rscratch1, ConstMethod::max_stack_offset())); __ add(rscratch1, rscratch1, frame::interpreter_frame_monitor_size() - + (EnableInvokeDynamic ? 2 : 0)); + + (EnableInvokeDynamic ? 2 : 0)); __ ldr(rscratch2, - Address(rfp, frame::interpreter_frame_initial_sp_offset * wordSize)); + Address(rfp, frame::interpreter_frame_initial_sp_offset * wordSize)); __ sub(rscratch1, rscratch2, rscratch1, ext::uxtw, 3); __ andr(sp, rscratch1, -16);
--- a/src/cpu/aarch64/vm/templateTable_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/templateTable_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -76,7 +76,7 @@ } static inline Address laddress(Register r, Register scratch, - InterpreterMacroAssembler* _masm) { + InterpreterMacroAssembler* _masm) { __ lea(scratch, Address(rlocals, r, Address::lsl(3))); return Address(scratch, Interpreter::local_offset_in_bytes(1)); } @@ -86,7 +86,7 @@ } static inline Address daddress(Register r, Register scratch, - InterpreterMacroAssembler* _masm) { + InterpreterMacroAssembler* _masm) { return laddress(r, scratch, _masm); } @@ -969,7 +969,7 @@ index_check(r3, r1); // prefer index in r1 __ lea(rscratch1, Address(r3, r1, Address::uxtw(2))); __ strw(r0, Address(rscratch1, - arrayOopDesc::base_offset_in_bytes(T_INT))); + arrayOopDesc::base_offset_in_bytes(T_INT))); } void TemplateTable::lastore() { @@ -982,7 +982,7 @@ index_check(r3, r1); // prefer index in r1 __ lea(rscratch1, Address(r3, r1, Address::uxtw(3))); __ str(r0, Address(rscratch1, - arrayOopDesc::base_offset_in_bytes(T_LONG))); + arrayOopDesc::base_offset_in_bytes(T_LONG))); } void TemplateTable::fastore() { @@ -995,7 +995,7 @@ index_check(r3, r1); // prefer index in r1 __ lea(rscratch1, Address(r3, r1, Address::uxtw(2))); __ strs(v0, Address(rscratch1, - arrayOopDesc::base_offset_in_bytes(T_FLOAT))); + arrayOopDesc::base_offset_in_bytes(T_FLOAT))); } void TemplateTable::dastore() { @@ -1008,7 +1008,7 @@ index_check(r3, r1); // prefer index in r1 __ lea(rscratch1, Address(r3, r1, Address::uxtw(3))); __ strd(v0, Address(rscratch1, - arrayOopDesc::base_offset_in_bytes(T_DOUBLE))); + arrayOopDesc::base_offset_in_bytes(T_DOUBLE))); } void TemplateTable::aastore() { @@ -1032,7 +1032,7 @@ // Move superklass into r0 __ load_klass(r0, r3); __ ldr(r0, Address(r0, - ObjArrayKlass::element_klass_offset())); + ObjArrayKlass::element_klass_offset())); // Compress array + index*oopSize + 12 into a single register. Frees r2. // Generate subtype check. Blows r2, r5 @@ -1087,7 +1087,7 @@ __ lea(rscratch1, Address(r3, r1, Address::uxtw(0))); __ strb(r0, Address(rscratch1, - arrayOopDesc::base_offset_in_bytes(T_BYTE))); + arrayOopDesc::base_offset_in_bytes(T_BYTE))); } void TemplateTable::castore() @@ -1101,7 +1101,7 @@ index_check(r3, r1); // prefer index in r1 __ lea(rscratch1, Address(r3, r1, Address::uxtw(1))); __ strh(r0, Address(rscratch1, - arrayOopDesc::base_offset_in_bytes(T_CHAR))); + arrayOopDesc::base_offset_in_bytes(T_CHAR))); } void TemplateTable::sastore() @@ -1168,7 +1168,7 @@ __ ldr(r2, at_tos_p1()); // load a __ str(r0, at_tos_p1()); // store b __ str(r2, at_tos()); // store a - __ push(r0); // push b + __ push(r0); // push b // stack: ..., b, a, b } @@ -1700,7 +1700,7 @@ // compute return address as bci __ ldr(rscratch2, Address(rmethod, Method::const_offset())); __ add(rscratch2, rscratch2, - in_bytes(ConstMethod::codes_offset()) - (is_wide ? 5 : 3)); + in_bytes(ConstMethod::codes_offset()) - (is_wide ? 5 : 3)); __ sub(r1, rbcp, rscratch2); __ push_i(r1); // Adjust the bcp by the 16-bit displacement in r2 @@ -1736,7 +1736,7 @@ __ push(r1); __ push(r2); __ call_VM(noreg, CAST_FROM_FN_PTR(address, - InterpreterRuntime::build_method_counters), rmethod); + InterpreterRuntime::build_method_counters), rmethod); __ pop(r2); __ pop(r1); __ pop(r0); @@ -1751,7 +1751,7 @@ if (ProfileInterpreter) { // Are we profiling? __ ldr(r1, Address(rmethod, in_bytes(Method::method_data_offset()))); - __ cbz(r1, no_mdo); + __ cbz(r1, no_mdo); // Increment the MDO backedge counter const Address mdo_backedge_counter(r1, in_bytes(MethodData::backedge_counter_offset()) + in_bytes(InvocationCounter::counter_offset())); @@ -1777,8 +1777,8 @@ if (ProfileInterpreter) { // Test to see if we should create a method data oop - __ lea(rscratch1, ExternalAddress((address) &InvocationCounter::InterpreterProfileLimit)); - __ ldrw(rscratch1, rscratch1); + __ lea(rscratch1, ExternalAddress((address) &InvocationCounter::InterpreterProfileLimit)); + __ ldrw(rscratch1, rscratch1); __ cmpw(r0, rscratch1); __ br(Assembler::LT, dispatch); @@ -1787,8 +1787,8 @@ if (UseOnStackReplacement) { // check for overflow against w1 which is the MDO taken count - __ lea(rscratch1, ExternalAddress((address) &InvocationCounter::InterpreterBackwardBranchLimit)); - __ ldrw(rscratch1, rscratch1); + __ lea(rscratch1, ExternalAddress((address) &InvocationCounter::InterpreterBackwardBranchLimit)); + __ ldrw(rscratch1, rscratch1); __ cmpw(r1, rscratch1); __ br(Assembler::LO, dispatch); // Intel == Assembler::below @@ -1807,8 +1807,8 @@ if (UseOnStackReplacement) { // check for overflow against w0, which is the sum of the // counters - __ lea(rscratch1, ExternalAddress((address) &InvocationCounter::InterpreterBackwardBranchLimit)); - __ ldrw(rscratch1, rscratch1); + __ lea(rscratch1, ExternalAddress((address) &InvocationCounter::InterpreterBackwardBranchLimit)); + __ ldrw(rscratch1, rscratch1); __ cmpw(r0, rscratch1); __ br(Assembler::HS, backedge_counter_overflow); // Intel == Assembler::aboveEqual } @@ -1839,7 +1839,7 @@ // invocation counter overflow __ bind(backedge_counter_overflow); __ neg(r2, r2); - __ add(r2, r2, rbcp); // branch bcp + __ add(r2, r2, rbcp); // branch bcp // IcoResult frequency_counter_overflow([JavaThread*], address branch_bcp) __ call_VM(noreg, CAST_FROM_FN_PTR(address, @@ -1855,7 +1855,7 @@ // r0: osr nmethod (osr ok) or NULL (osr not possible) // w1: target bytecode // r2: scratch - __ cbz(r0, dispatch); // test result -- no osr if null + __ cbz(r0, dispatch); // test result -- no osr if null // nmethod may have been invalidated (VM may block upon call_VM return) __ ldrw(r2, Address(r0, nmethod::entry_bci_offset())); // InvalidOSREntryBci == -2 which overflows cmpw as unsigned @@ -1877,7 +1877,7 @@ // remove activation // get sender esp __ ldr(esp, - Address(rfp, frame::interpreter_frame_sender_sp_offset * wordSize)); + Address(rfp, frame::interpreter_frame_sender_sp_offset * wordSize)); // remove frame anchor __ leave(); // Ensure compiled code always sees stack at proper alignment @@ -2116,8 +2116,8 @@ Label loop; __ bind(loop); // int h = (i + j) >> 1; - __ addw(h, i, j); // h = i + j; - __ lsrw(h, h, 1); // h = (i + j) >> 1; + __ addw(h, i, j); // h = i + j; + __ lsrw(h, h, 1); // h = (i + j) >> 1; // if (key < array[h].fast_match()) { // j = h; // } else { @@ -2294,15 +2294,15 @@ ByteSize cp_base_offset = ConstantPoolCache::base_offset(); // Field offset __ ldr(off, Address(cache, in_bytes(cp_base_offset + - ConstantPoolCacheEntry::f2_offset()))); + ConstantPoolCacheEntry::f2_offset()))); // Flags __ ldrw(flags, Address(cache, in_bytes(cp_base_offset + - ConstantPoolCacheEntry::flags_offset()))); + ConstantPoolCacheEntry::flags_offset()))); // klass overwrite register if (is_static) { __ ldr(obj, Address(cache, in_bytes(cp_base_offset + - ConstantPoolCacheEntry::f1_offset()))); + ConstantPoolCacheEntry::f1_offset()))); const int mirror_offset = in_bytes(Klass::java_mirror_offset()); __ ldr(obj, Address(obj, mirror_offset)); } @@ -2593,10 +2593,10 @@ // could be one or two words depending on its type. As a result, // we must find the type to determine where the object is. __ ldrw(c_rarg3, Address(c_rarg2, - in_bytes(cp_base_offset + - ConstantPoolCacheEntry::flags_offset()))); + in_bytes(cp_base_offset + + ConstantPoolCacheEntry::flags_offset()))); __ lsr(c_rarg3, c_rarg3, - ConstantPoolCacheEntry::tos_state_shift); + ConstantPoolCacheEntry::tos_state_shift); ConstantPoolCacheEntry::verify_tos_state_shift(); Label nope2, done, ok; __ ldr(c_rarg1, at_tos_p1()); // initially assume a one word jvalue @@ -2893,7 +2893,7 @@ // test for volatile with r3 __ ldrw(r3, Address(r2, in_bytes(base + - ConstantPoolCacheEntry::flags_offset()))); + ConstantPoolCacheEntry::flags_offset()))); // replace index with field offset from cache entry __ ldr(r1, Address(r2, in_bytes(base + ConstantPoolCacheEntry::f2_offset()))); @@ -2989,7 +2989,7 @@ __ ldr(r1, Address(r2, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::f2_offset()))); __ ldrw(r3, Address(r2, in_bytes(ConstantPoolCache::base_offset() + - ConstantPoolCacheEntry::flags_offset()))); + ConstantPoolCacheEntry::flags_offset()))); // r0: object __ verify_oop(r0); @@ -3056,7 +3056,7 @@ // access constant pool cache __ get_cache_and_index_at_bcp(r2, r3, 2); __ ldr(r1, Address(r2, in_bytes(ConstantPoolCache::base_offset() + - ConstantPoolCacheEntry::f2_offset()))); + ConstantPoolCacheEntry::f2_offset()))); // 8179954: We need to make sure that the code generated for // volatile accesses forms a sequentially-consistent set of @@ -3095,7 +3095,7 @@ { Label notVolatile; __ ldrw(r3, Address(r2, in_bytes(ConstantPoolCache::base_offset() + - ConstantPoolCacheEntry::flags_offset()))); + ConstantPoolCacheEntry::flags_offset()))); __ tbz(r3, ConstantPoolCacheEntry::is_volatile_shift, notVolatile); __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore); __ bind(notVolatile); @@ -3116,10 +3116,10 @@ void TemplateTable::prepare_invoke(int byte_no, Register method, // linked method (or i-klass) - Register index, // itable index, MethodType, etc. - Register recv, // if caller wants to see it - Register flags // if caller wants to test it - ) { + Register index, // itable index, MethodType, etc. + Register recv, // if caller wants to see it + Register flags // if caller wants to test it + ) { // determine flags Bytecodes::Code code = bytecode(); const bool is_invokeinterface = code == Bytecodes::_invokeinterface; @@ -3249,7 +3249,7 @@ assert(byte_no == f1_byte, "use this argument"); prepare_invoke(byte_no, rmethod, noreg, // get f1 Method* - r2); // get receiver also for null check + r2); // get receiver also for null check __ verify_oop(r2); __ null_check(r2); // do the call @@ -3280,7 +3280,7 @@ assert(byte_no == f1_byte, "use this argument"); prepare_invoke(byte_no, r0, rmethod, // get f1 Klass*, f2 Method* - r2, r3); // recv, flags + r2, r3); // recv, flags // r0: interface klass (from f1) // rmethod: method (from f2) @@ -3479,7 +3479,7 @@ if (UseTLAB) { __ tlab_allocate(r0, r3, 0, noreg, r1, - allow_shared_alloc ? allocate_shared : slow_case); + allow_shared_alloc ? allocate_shared : slow_case); if (ZeroTLAB) { // the fields have been already cleared
--- a/src/cpu/aarch64/vm/vtableStubs_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/cpu/aarch64/vm/vtableStubs_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -238,50 +238,50 @@ // The JVM98 app. _202_jess has a megamorphic interface call. // The itable code looks like this: - // ldr xmethod, [xscratch2,#CompiledICHolder::holder_klass_offset] - // ldr x0, [xscratch2] - // ldr w10, [x1,#oopDesc::klass_offset_in_bytes] - // mov xheapbase, #0x3c000000 // #narrow_klass_base - // movk xheapbase, #0x3f7, lsl #32 - // add x10, xheapbase, x10 - // mov xheapbase, #0xe7ff0000 // #heapbase - // movk xheapbase, #0x3f7, lsl #32 - // ldr w11, [x10,#vtable_length_offset] - // add x11, x10, x11, uxtx #3 - // add x11, x11, #itableMethodEntry::method_offset_in_bytes - // ldr x10, [x11] - // cmp xmethod, x10 + // ldr xmethod, [xscratch2,#CompiledICHolder::holder_klass_offset] + // ldr x0, [xscratch2] + // ldr w10, [x1,#oopDesc::klass_offset_in_bytes] + // mov xheapbase, #0x3c000000 // #narrow_klass_base + // movk xheapbase, #0x3f7, lsl #32 + // add x10, xheapbase, x10 + // mov xheapbase, #0xe7ff0000 // #heapbase + // movk xheapbase, #0x3f7, lsl #32 + // ldr w11, [x10,#vtable_length_offset] + // add x11, x10, x11, uxtx #3 + // add x11, x11, #itableMethodEntry::method_offset_in_bytes + // ldr x10, [x11] + // cmp xmethod, x10 // b.eq success // search: - // cbz x10, no_such_interface - // add x11, x11, #0x10 - // ldr x10, [x11] - // cmp xmethod, x10 - // b.ne search + // cbz x10, no_such_interface + // add x11, x11, #0x10 + // ldr x10, [x11] + // cmp xmethod, x10 + // b.ne search // success: - // ldr w10, [x1,#oopDesc::klass_offset_in_bytes] - // mov xheapbase, #0x3c000000 // #narrow_klass_base - // movk xheapbase, #0x3f7, lsl #32 - // add x10, xheapbase, x10 - // mov xheapbase, #0xe7ff0000 // #heapbase - // movk xheapbase, #0x3f7, lsl #32 - // ldr w11, [x10,#vtable_length_offset] - // add x11, x10, x11, uxtx #3 - // add x11, x11, #itableMethodEntry::method_offset_in_bytes - // add x10, x10, #itentry_off - // ldr xmethod, [x11] - // cmp x0, xmethod - // b.eq found_method + // ldr w10, [x1,#oopDesc::klass_offset_in_bytes] + // mov xheapbase, #0x3c000000 // #narrow_klass_base + // movk xheapbase, #0x3f7, lsl #32 + // add x10, xheapbase, x10 + // mov xheapbase, #0xe7ff0000 // #heapbase + // movk xheapbase, #0x3f7, lsl #32 + // ldr w11, [x10,#vtable_length_offset] + // add x11, x10, x11, uxtx #3 + // add x11, x11, #itableMethodEntry::method_offset_in_bytes + // add x10, x10, #itentry_off + // ldr xmethod, [x11] + // cmp x0, xmethod + // b.eq found_method // search2: - // cbz xmethod, 0x000003ffa872e6cc - // add x11, x11, #0x10 - // ldr xmethod, [x11] - // cmp x0, xmethod - // b.ne search2 - // ldr w11, [x11,#itableOffsetEntry::offset_offset_in_bytes] - // ldr xmethod, [x10,w11,uxtw] - // ldr xscratch1, [xmethod,#Method::from_compiled_offset] - // br xscratch1 + // cbz xmethod, 0x000003ffa872e6cc + // add x11, x11, #0x10 + // ldr xmethod, [x11] + // cmp x0, xmethod + // b.ne search2 + // ldr w11, [x11,#itableOffsetEntry::offset_offset_in_bytes] + // ldr xmethod, [x10,w11,uxtw] + // ldr xscratch1, [xmethod,#Method::from_compiled_offset] + // br xscratch1 // no_such_interface: // b throw_ICCE_entry
--- a/src/os_cpu/linux_aarch64/vm/os_linux_aarch64.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/os_cpu/linux_aarch64/vm/os_linux_aarch64.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -542,7 +542,7 @@ ucontext_t *uc = (ucontext_t*)context; st->print_cr("Registers:"); for (int r = 0; r < 31; r++) - st->print_cr( "R%d=" INTPTR_FORMAT, r, (int64_t)uc->uc_mcontext.regs[r]); + st->print_cr( "R%d=" INTPTR_FORMAT, r, (int64_t)uc->uc_mcontext.regs[r]); st->cr(); intptr_t *sp = (intptr_t *)os::Linux::ucontext_get_sp(uc); @@ -573,7 +573,7 @@ // this is only for the "general purpose" registers for (int r = 0; r < 31; r++) - st->print_cr( "R%d=" INTPTR_FORMAT, r, (int64_t)uc->uc_mcontext.regs[r]); + st->print_cr( "R%d=" INTPTR_FORMAT, r, (int64_t)uc->uc_mcontext.regs[r]); st->cr(); }
--- a/src/share/vm/c1/c1_Canonicalizer.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/share/vm/c1/c1_Canonicalizer.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -941,7 +941,7 @@ // AARCH64 cannot handle shifts which are not either 0, or log2 of the type size #ifdef AARCH64 if (*log2_scale != 0 && - (1 << *log2_scale) != type2aelembytes(x->basic_type(), true)) + (1 << *log2_scale) != type2aelembytes(x->basic_type(), true)) return false; #endif
--- a/src/share/vm/c1/c1_LIR.hpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/share/vm/c1/c1_LIR.hpp Thu Apr 22 01:38:42 2021 +0100 @@ -2146,7 +2146,7 @@ #endif #if defined (TARGET_ARCH_aarch64) void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, - ConversionStub* stub = NULL, LIR_Opr tmp1 = LIR_OprDesc::illegalOpr()) { + ConversionStub* stub = NULL, LIR_Opr tmp1 = LIR_OprDesc::illegalOpr()) { append(new LIR_OpConvert(code, left, dst, stub, tmp1, LIR_OprDesc::illegalOpr())); } #else
--- a/src/share/vm/memory/metaspace.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/share/vm/memory/metaspace.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -3086,24 +3086,24 @@ // with a single MOVK instruction. We can do this iff the // compressed class base is a multiple of 4G. for (char *a = (char*)align_ptr_up(requested_addr, 4*G); - a < (char*)(1024*G); - a += 4*G) { + a < (char*)(1024*G); + a += 4*G) { if (UseSharedSpaces - && ! can_use_cds_with_metaspace_addr(a, cds_base)) { - // We failed to find an aligned base that will reach. Fall - // back to using our requested addr. - metaspace_rs = ReservedSpace(compressed_class_space_size(), + && ! can_use_cds_with_metaspace_addr(a, cds_base)) { + // We failed to find an aligned base that will reach. Fall + // back to using our requested addr. + metaspace_rs = ReservedSpace(compressed_class_space_size(), _reserve_alignment, large_pages, requested_addr, 0); - break; + break; } metaspace_rs = ReservedSpace(compressed_class_space_size(), - _reserve_alignment, - large_pages, - a, 0); + _reserve_alignment, + large_pages, + a, 0); if (metaspace_rs.is_reserved()) - break; + break; } } @@ -3361,7 +3361,7 @@ // on the medium chunk list. The next chunk will be small and progress // from there. This size calculated by -version. _first_class_chunk_word_size = MIN2((size_t)MediumChunk*6, - (size_t) ((CompressedClassSpaceSize/BytesPerWord)*2)); + (size_t) ((CompressedClassSpaceSize/BytesPerWord)*2)); _first_class_chunk_word_size = align_word_size_up(_first_class_chunk_word_size); // Arbitrarily set the initial virtual space to a multiple // of the boot class loader size.
--- a/src/share/vm/opto/memnode.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/share/vm/opto/memnode.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -3180,7 +3180,7 @@ Node* alloc = AllocateNode::Ideal_allocation(in(MemBarNode::Precedent), phase); if ((alloc != NULL) && alloc->is_Allocate() && AARCH64_ONLY ( alloc->as_Allocate()->does_not_escape_thread() ) - NOT_AARCH64 ( alloc->as_Allocate()->_is_non_escaping ) + NOT_AARCH64 ( alloc->as_Allocate()->_is_non_escaping ) ) { // The allocated object does not escape. eliminate = true;
--- a/src/share/vm/runtime/vm_version.cpp Fri Feb 05 20:19:33 2021 +0000 +++ b/src/share/vm/runtime/vm_version.cpp Thu Apr 22 01:38:42 2021 +0100 @@ -197,7 +197,7 @@ #define CPU IA32_ONLY("x86") \ IA64_ONLY("ia64") \ AMD64_ONLY("amd64") \ - AARCH64_ONLY("aarch64") \ + AARCH64_ONLY("aarch64") \ SPARC_ONLY("sparc") #endif // ZERO #endif
--- a/test/aarch64/DoubleArithTests.java Fri Feb 05 20:19:33 2021 +0000 +++ b/test/aarch64/DoubleArithTests.java Thu Apr 22 01:38:42 2021 +0100 @@ -1,49 +1,49 @@ public class DoubleArithTests { private static double test_neg(double a) { - return -a; + return -a; } private static double test_add(double a, double b) { - return a + b; + return a + b; } private static double test_sub(double a, double b) { - return a - b; + return a - b; } private static double test_mul(double a, double b) { - return a * b; + return a * b; } private static double test_div(double a, double b) { - return a / b; + return a / b; } private static double test_rem(double a, double b) { - return a % b; + return a % b; } private static void assertThat(boolean assertion) { - if (! assertion) { - throw new AssertionError(); - } + if (! assertion) { + throw new AssertionError(); + } } public static void main(String[] args) { - assertThat(test_neg(10.0) == -10.0); - assertThat(test_add(3.0, 2.0) == 5.0); + assertThat(test_neg(10.0) == -10.0); + assertThat(test_add(3.0, 2.0) == 5.0); - assertThat(test_sub(40.0, 13.0) == 27.0); + assertThat(test_sub(40.0, 13.0) == 27.0); - assertThat(test_mul(5.0, 200.0) == 1000.0); + assertThat(test_mul(5.0, 200.0) == 1000.0); - assertThat(test_div(30.0, 3.0) == 10.0); - assertThat(test_div(30.0, 0.0) == Double.POSITIVE_INFINITY); + assertThat(test_div(30.0, 3.0) == 10.0); + assertThat(test_div(30.0, 0.0) == Double.POSITIVE_INFINITY); - assertThat(test_rem(30.0, 3.0) == 0.0); - assertThat(test_rem(29.0, 3.0) == 2.0); - assertThat(Double.isNaN(test_rem(30.0, 0.0))); + assertThat(test_rem(30.0, 3.0) == 0.0); + assertThat(test_rem(29.0, 3.0) == 2.0); + assertThat(Double.isNaN(test_rem(30.0, 0.0))); } }
--- a/test/aarch64/DoubleCmpTests.java Fri Feb 05 20:19:33 2021 +0000 +++ b/test/aarch64/DoubleCmpTests.java Thu Apr 22 01:38:42 2021 +0100 @@ -2,101 +2,101 @@ public class DoubleCmpTests { private static boolean test_isEq(double a, double b) { - return a == b; + return a == b; } private static boolean test_isNe(double a, double b) { - return a != b; + return a != b; } private static boolean test_isLt(double a, double b) { - return a < b; + return a < b; } private static boolean test_isLe(double a, double b) { - return a <= b; + return a <= b; } private static boolean test_isGe(double a, double b) { - return a >= b; + return a >= b; } private static boolean test_isGt(double a, double b) { - return a > b; + return a > b; } private static boolean test_isEqC(double a) { - return a == 7.; + return a == 7.; } private static boolean test_isNeC(double a) { - return a != 7.; + return a != 7.; } private static boolean test_isLtC(double a) { - return a < 7.; + return a < 7.; } private static boolean test_isLeC(double a) { - return a <= 7.; + return a <= 7.; } private static boolean test_isGeC(double a) { - return a >= 7.; + return a >= 7.; } private static boolean test_isGtC(double a) { - return a > 7.; + return a > 7.; } private static void assertThat(boolean assertion) { - if (! assertion) { - throw new AssertionError(); - } + if (! assertion) { + throw new AssertionError(); + } } public static void main(String[] args) { - assertThat(test_isEq(7., 7.)); - assertThat(! test_isEq(70., 7.)); - assertThat(! test_isNe(7., 7.)); - assertThat(test_isNe(70., 7.)); + assertThat(test_isEq(7., 7.)); + assertThat(! test_isEq(70., 7.)); + assertThat(! test_isNe(7., 7.)); + assertThat(test_isNe(70., 7.)); - assertThat(test_isLt(7., 70.)); - assertThat(! test_isLt(70., 7.)); - assertThat(! test_isLt(7., 7.)); + assertThat(test_isLt(7., 70.)); + assertThat(! test_isLt(70., 7.)); + assertThat(! test_isLt(7., 7.)); - assertThat(test_isLe(7., 70.)); - assertThat(! test_isLe(70., 7.)); - assertThat(test_isLe(7., 7.)); + assertThat(test_isLe(7., 70.)); + assertThat(! test_isLe(70., 7.)); + assertThat(test_isLe(7., 7.)); - assertThat(!test_isGe(7., 70.)); - assertThat(test_isGe(70., 7.)); - assertThat(test_isGe(7., 7.)); + assertThat(!test_isGe(7., 70.)); + assertThat(test_isGe(70., 7.)); + assertThat(test_isGe(7., 7.)); - assertThat(!test_isGt(7., 70.)); - assertThat(test_isGt(70., 7.)); - assertThat(! test_isGt(7., 7.)); + assertThat(!test_isGt(7., 70.)); + assertThat(test_isGt(70., 7.)); + assertThat(! test_isGt(7., 7.)); - assertThat(test_isEqC(7.)); - assertThat(! test_isEqC(70.)); - assertThat(! test_isNeC(7.)); - assertThat(test_isNeC(70.)); + assertThat(test_isEqC(7.)); + assertThat(! test_isEqC(70.)); + assertThat(! test_isNeC(7.)); + assertThat(test_isNeC(70.)); - assertThat(test_isLtC(6.)); - assertThat(! test_isLtC(70.)); - assertThat(! test_isLtC(7.)); + assertThat(test_isLtC(6.)); + assertThat(! test_isLtC(70.)); + assertThat(! test_isLtC(7.)); - assertThat(test_isLeC(6.)); - assertThat(! test_isLeC(70.)); - assertThat(test_isLeC(7.)); + assertThat(test_isLeC(6.)); + assertThat(! test_isLeC(70.)); + assertThat(test_isLeC(7.)); - assertThat(!test_isGeC(6.)); - assertThat(test_isGeC(70.)); - assertThat(test_isGeC(7.)); + assertThat(!test_isGeC(6.)); + assertThat(test_isGeC(70.)); + assertThat(test_isGeC(7.)); - assertThat(!test_isGtC(6.)); - assertThat(test_isGtC(70.)); - assertThat(! test_isGtC(7.)); + assertThat(!test_isGtC(6.)); + assertThat(test_isGtC(70.)); + assertThat(! test_isGtC(7.)); } }
--- a/test/aarch64/FloatArithTests.java Fri Feb 05 20:19:33 2021 +0000 +++ b/test/aarch64/FloatArithTests.java Thu Apr 22 01:38:42 2021 +0100 @@ -1,49 +1,49 @@ public class FloatArithTests { private static float test_neg(float a) { - return -a; + return -a; } private static float test_add(float a, float b) { - return a + b; + return a + b; } private static float test_sub(float a, float b) { - return a - b; + return a - b; } private static float test_mul(float a, float b) { - return a * b; + return a * b; } private static float test_div(float a, float b) { - return a / b; + return a / b; } private static float test_rem(float a, float b) { - return a % b; + return a % b; } private static void assertThat(boolean assertion) { - if (! assertion) { - throw new AssertionError(); - } + if (! assertion) { + throw new AssertionError(); + } } public static void main(String[] args) { - assertThat(test_neg(10F) == -10F); - assertThat(test_add(3F, 2F) == 5F); + assertThat(test_neg(10F) == -10F); + assertThat(test_add(3F, 2F) == 5F); - assertThat(test_sub(40F, 13F) == 27F); + assertThat(test_sub(40F, 13F) == 27F); - assertThat(test_mul(5F, 200F) == 1000F); + assertThat(test_mul(5F, 200F) == 1000F); - assertThat(test_div(30F, 3F) == 10F); - assertThat(test_div(30, 0) == Float.POSITIVE_INFINITY); + assertThat(test_div(30F, 3F) == 10F); + assertThat(test_div(30, 0) == Float.POSITIVE_INFINITY); - assertThat(test_rem(30F, 3F) == 0); - assertThat(test_rem(29F, 3F) == 2F); - assertThat(Float.isNaN(test_rem(30F, 0F))); + assertThat(test_rem(30F, 3F) == 0); + assertThat(test_rem(29F, 3F) == 2F); + assertThat(Float.isNaN(test_rem(30F, 0F))); } }
--- a/test/aarch64/FloatCmpTests.java Fri Feb 05 20:19:33 2021 +0000 +++ b/test/aarch64/FloatCmpTests.java Thu Apr 22 01:38:42 2021 +0100 @@ -2,101 +2,101 @@ public class FloatCmpTests { private static boolean test_isEq(float a, float b) { - return a == b; + return a == b; } private static boolean test_isNe(float a, float b) { - return a != b; + return a != b; } private static boolean test_isLt(float a, float b) { - return a < b; + return a < b; } private static boolean test_isLe(float a, float b) { - return a <= b; + return a <= b; } private static boolean test_isGe(float a, float b) { - return a >= b; + return a >= b; } private static boolean test_isGt(float a, float b) { - return a > b; + return a > b; } private static boolean test_isEqC(float a) { - return a == 7F; + return a == 7F; } private static boolean test_isNeC(float a) { - return a != 7F; + return a != 7F; } private static boolean test_isLtC(float a) { - return a < 7F; + return a < 7F; } private static boolean test_isLeC(float a) { - return a <= 7F; + return a <= 7F; } private static boolean test_isGeC(float a) { - return a >= 7F; + return a >= 7F; } private static boolean test_isGtC(float a) { - return a > 7F; + return a > 7F; } private static void assertThat(boolean assertion) { - if (! assertion) { - throw new AssertionError(); - } + if (! assertion) { + throw new AssertionError(); + } } public static void main(String[] args) { - assertThat(test_isEq(7F, 7F)); - assertThat(! test_isEq(70F, 7F)); - assertThat(! test_isNe(7F, 7F)); - assertThat(test_isNe(70F, 7F)); + assertThat(test_isEq(7F, 7F)); + assertThat(! test_isEq(70F, 7F)); + assertThat(! test_isNe(7F, 7F)); + assertThat(test_isNe(70F, 7F)); - assertThat(test_isLt(7F, 70F)); - assertThat(! test_isLt(70F, 7F)); - assertThat(! test_isLt(7F, 7F)); + assertThat(test_isLt(7F, 70F)); + assertThat(! test_isLt(70F, 7F)); + assertThat(! test_isLt(7F, 7F)); - assertThat(test_isLe(7F, 70F)); - assertThat(! test_isLe(70F, 7F)); - assertThat(test_isLe(7F, 7F)); + assertThat(test_isLe(7F, 70F)); + assertThat(! test_isLe(70F, 7F)); + assertThat(test_isLe(7F, 7F)); - assertThat(!test_isGe(7F, 70F)); - assertThat(test_isGe(70F, 7F)); - assertThat(test_isGe(7F, 7F)); + assertThat(!test_isGe(7F, 70F)); + assertThat(test_isGe(70F, 7F)); + assertThat(test_isGe(7F, 7F)); - assertThat(!test_isGt(7F, 70F)); - assertThat(test_isGt(70F, 7F)); - assertThat(! test_isGt(7F, 7F)); + assertThat(!test_isGt(7F, 70F)); + assertThat(test_isGt(70F, 7F)); + assertThat(! test_isGt(7F, 7F)); - assertThat(test_isEqC(7F)); - assertThat(! test_isEqC(70F)); - assertThat(! test_isNeC(7F)); - assertThat(test_isNeC(70F)); + assertThat(test_isEqC(7F)); + assertThat(! test_isEqC(70F)); + assertThat(! test_isNeC(7F)); + assertThat(test_isNeC(70F)); - assertThat(test_isLtC(6F)); - assertThat(! test_isLtC(70F)); - assertThat(! test_isLtC(7F)); + assertThat(test_isLtC(6F)); + assertThat(! test_isLtC(70F)); + assertThat(! test_isLtC(7F)); - assertThat(test_isLeC(6F)); - assertThat(! test_isLeC(70F)); - assertThat(test_isLeC(7F)); + assertThat(test_isLeC(6F)); + assertThat(! test_isLeC(70F)); + assertThat(test_isLeC(7F)); - assertThat(!test_isGeC(6F)); - assertThat(test_isGeC(70F)); - assertThat(test_isGeC(7F)); + assertThat(!test_isGeC(6F)); + assertThat(test_isGeC(70F)); + assertThat(test_isGeC(7F)); - assertThat(!test_isGtC(6F)); - assertThat(test_isGtC(70F)); - assertThat(! test_isGtC(7F)); + assertThat(!test_isGtC(6F)); + assertThat(test_isGtC(70F)); + assertThat(! test_isGtC(7F)); } }
--- a/test/aarch64/IntArithTests.java Fri Feb 05 20:19:33 2021 +0000 +++ b/test/aarch64/IntArithTests.java Thu Apr 22 01:38:42 2021 +0100 @@ -8,124 +8,123 @@ private static final int IIMM24_5 = 0x1001000; // Should not encode as imm private static int test_neg(int a) { - return -a; + return -a; } private static int test_addi(int a, int b) { - return a + b; + return a + b; } private static int test_addic0(int a) { - return a + IIMM12_0; + return a + IIMM12_0; } private static int test_addic1(int a) { - return a + IIMM12_1; + return a + IIMM12_1; } private static int test_addic2(int a) { - return a + IIMM12_2; + return a + IIMM12_2; } private static int test_addic3(int a) { - return a + IIMM24_3; + return a + IIMM24_3; } private static int test_addic4(int a) { - return a + IIMM24_4; + return a + IIMM24_4; } private static int test_addic5(int a) { - return a + IIMM24_5; + return a + IIMM24_5; } private static int test_subi(int a, int b) { - return a - b; + return a - b; } private static int test_subc1(int a) { - return a - 11; + return a - 11; } private static int test_mulic1(int a) { - // Generates shl. - return a * 8; + // Generates shl. + return a * 8; } private static int test_mulic2(int a) { - // Generates shl followed by add. - return a * 9; + // Generates shl followed by add. + return a * 9; } private static int test_mulic3(int a) { - // Generates shl followed by sub. - return a * 7; + // Generates shl followed by sub. + return a * 7; } private static int test_mulic4(int a) { - // Generates normal mul. - return a * 10; + // Generates normal mul. + return a * 10; } private static int test_muli(int a, int b) { - // Generates normal mul. - return a * b; + // Generates normal mul. + return a * b; } private static int test_divi(int a, int b) { - return a / b; + return a / b; } private static int test_remi(int a, int b) { - return a % b; + return a % b; } private static void assertThat(boolean assertion) { - if (! assertion) { - throw new AssertionError(); - } + if (! assertion) { + throw new AssertionError(); + } } public static void main(String[] args) { - assertThat(test_neg(10) == -10); - assertThat(test_addi(3, 2) == 5); - assertThat(test_addi(Integer.MAX_VALUE, 1) == Integer.MIN_VALUE); - assertThat(test_addic0(3) == 4); - assertThat(test_addic1(3) == 0x1002); - assertThat(test_addic2(3) == 0x1004); - assertThat(test_addic3(3) == 0x1003); - assertThat(test_addic4(3) == 0xfff003); - assertThat(test_addic5(3) == 0x1001003); + assertThat(test_neg(10) == -10); + assertThat(test_addi(3, 2) == 5); + assertThat(test_addi(Integer.MAX_VALUE, 1) == Integer.MIN_VALUE); + assertThat(test_addic0(3) == 4); + assertThat(test_addic1(3) == 0x1002); + assertThat(test_addic2(3) == 0x1004); + assertThat(test_addic3(3) == 0x1003); + assertThat(test_addic4(3) == 0xfff003); + assertThat(test_addic5(3) == 0x1001003); - assertThat(test_subi(40, 13) == 27); - assertThat(test_subi(Integer.MIN_VALUE, 1) == Integer.MAX_VALUE); - assertThat(test_subc1(40) == 29); + assertThat(test_subi(40, 13) == 27); + assertThat(test_subi(Integer.MIN_VALUE, 1) == Integer.MAX_VALUE); + assertThat(test_subc1(40) == 29); - assertThat(test_mulic1(5) == 40); - assertThat(test_mulic2(5) == 45); - assertThat(test_mulic3(5) == 35); - assertThat(test_mulic4(5) == 50); - assertThat(test_muli(5, 200) == 1000); + assertThat(test_mulic1(5) == 40); + assertThat(test_mulic2(5) == 45); + assertThat(test_mulic3(5) == 35); + assertThat(test_mulic4(5) == 50); + assertThat(test_muli(5, 200) == 1000); - assertThat(test_divi(30, 3) == 10); - assertThat(test_divi(29, 3) == 9); - assertThat(test_divi(Integer.MIN_VALUE, -1) == Integer.MIN_VALUE); - try { - test_divi(30, 0); - throw new AssertionError(); - } catch (ArithmeticException ex) { - // Pass. - } + assertThat(test_divi(30, 3) == 10); + assertThat(test_divi(29, 3) == 9); + assertThat(test_divi(Integer.MIN_VALUE, -1) == Integer.MIN_VALUE); + try { + test_divi(30, 0); + throw new AssertionError(); + } catch (ArithmeticException ex) { + // Pass. + } - assertThat(test_remi(30, 3) == 0); - assertThat(test_remi(29, 3) == 2); - assertThat(test_remi(Integer.MIN_VALUE, -1) == 0); - try { - test_remi(30, 0); - throw new AssertionError(); - } catch (ArithmeticException ex) { - // Pass. - } + assertThat(test_remi(30, 3) == 0); + assertThat(test_remi(29, 3) == 2); + assertThat(test_remi(Integer.MIN_VALUE, -1) == 0); + try { + test_remi(30, 0); + throw new AssertionError(); + } catch (ArithmeticException ex) { + // Pass. + } } } -
--- a/test/aarch64/IntCmpTests.java Fri Feb 05 20:19:33 2021 +0000 +++ b/test/aarch64/IntCmpTests.java Thu Apr 22 01:38:42 2021 +0100 @@ -2,101 +2,101 @@ public class IntCmpTests { private static boolean test_isEq(int a, int b) { - return a == b; + return a == b; } private static boolean test_isNe(int a, int b) { - return a != b; + return a != b; } private static boolean test_isLt(int a, int b) { - return a < b; + return a < b; } private static boolean test_isLe(int a, int b) { - return a <= b; + return a <= b; } private static boolean test_isGe(int a, int b) { - return a >= b; + return a >= b; } private static boolean test_isGt(int a, int b) { - return a > b; + return a > b; } private static boolean test_isEqC(int a) { - return a == 7; + return a == 7; } private static boolean test_isNeC(int a) { - return a != 7; + return a != 7; } private static boolean test_isLtC(int a) { - return a < 7; + return a < 7; } private static boolean test_isLeC(int a) { - return a <= 7; + return a <= 7; } private static boolean test_isGeC(int a) { - return a >= 7; + return a >= 7; } private static boolean test_isGtC(int a) { - return a > 7; + return a > 7; } private static void assertThat(boolean assertion) { - if (! assertion) { - throw new AssertionError(); - } + if (! assertion) { + throw new AssertionError(); + } } public static void main(String[] args) { - assertThat(test_isEq(7, 7)); - assertThat(! test_isEq(70, 7)); - assertThat(! test_isNe(7, 7)); - assertThat(test_isNe(70, 7)); + assertThat(test_isEq(7, 7)); + assertThat(! test_isEq(70, 7)); + assertThat(! test_isNe(7, 7)); + assertThat(test_isNe(70, 7)); - assertThat(test_isLt(7, 70)); - assertThat(! test_isLt(70, 7)); - assertThat(! test_isLt(7, 7)); + assertThat(test_isLt(7, 70)); + assertThat(! test_isLt(70, 7)); + assertThat(! test_isLt(7, 7)); - assertThat(test_isLe(7, 70)); - assertThat(! test_isLe(70, 7)); - assertThat(test_isLe(7, 7)); + assertThat(test_isLe(7, 70)); + assertThat(! test_isLe(70, 7)); + assertThat(test_isLe(7, 7)); - assertThat(!test_isGe(7, 70)); - assertThat(test_isGe(70, 7)); - assertThat(test_isGe(7, 7)); + assertThat(!test_isGe(7, 70)); + assertThat(test_isGe(70, 7)); + assertThat(test_isGe(7, 7)); - assertThat(!test_isGt(7, 70)); - assertThat(test_isGt(70, 7)); - assertThat(! test_isGt(7, 7)); + assertThat(!test_isGt(7, 70)); + assertThat(test_isGt(70, 7)); + assertThat(! test_isGt(7, 7)); - assertThat(test_isEqC(7)); - assertThat(! test_isEqC(70)); - assertThat(! test_isNeC(7)); - assertThat(test_isNeC(70)); + assertThat(test_isEqC(7)); + assertThat(! test_isEqC(70)); + assertThat(! test_isNeC(7)); + assertThat(test_isNeC(70)); - assertThat(test_isLtC(6)); - assertThat(! test_isLtC(70)); - assertThat(! test_isLtC(7)); + assertThat(test_isLtC(6)); + assertThat(! test_isLtC(70)); + assertThat(! test_isLtC(7)); - assertThat(test_isLeC(6)); - assertThat(! test_isLeC(70)); - assertThat(test_isLeC(7)); + assertThat(test_isLeC(6)); + assertThat(! test_isLeC(70)); + assertThat(test_isLeC(7)); - assertThat(!test_isGeC(6)); - assertThat(test_isGeC(70)); - assertThat(test_isGeC(7)); + assertThat(!test_isGeC(6)); + assertThat(test_isGeC(70)); + assertThat(test_isGeC(7)); - assertThat(!test_isGtC(6)); - assertThat(test_isGtC(70)); - assertThat(! test_isGtC(7)); + assertThat(!test_isGtC(6)); + assertThat(test_isGtC(70)); + assertThat(! test_isGtC(7)); } }
--- a/test/aarch64/IntLogicTests.java Fri Feb 05 20:19:33 2021 +0000 +++ b/test/aarch64/IntLogicTests.java Thu Apr 22 01:38:42 2021 +0100 @@ -1,66 +1,65 @@ public class IntLogicTests { private static int test_and(int a, int b) { - return a & b; + return a & b; } private static int test_andc1(int a) { - // Generates immediate instruction. - return a & 0xf0f0f0f0; + // Generates immediate instruction. + return a & 0xf0f0f0f0; } private static int test_andc2(int a) { - // Generates non-immediate instruction. - return a & 0x123456d5; + // Generates non-immediate instruction. + return a & 0x123456d5; } private static int test_or(int a, int b) { - return a | b; + return a | b; } private static int test_orc1(int a) { - // Generates immediate instruction. - return a | 0xf0f0f0f0; + // Generates immediate instruction. + return a | 0xf0f0f0f0; } private static int test_orc2(int a) { - // Generates non-immediate instruction. - return a | 0x123456d5; + // Generates non-immediate instruction. + return a | 0x123456d5; } private static int test_xor(int a, int b) { - return a ^ b; + return a ^ b; } private static int test_xorc1(int a) { - // Generates immediate instruction. - return a ^ 0xf0f0f0f0; + // Generates immediate instruction. + return a ^ 0xf0f0f0f0; } private static int test_xorc2(int a) { - // Generates non-immediate instruction. - return a ^ 0x123456d5; + // Generates non-immediate instruction. + return a ^ 0x123456d5; } private static void assertThat(boolean assertion) { - if (! assertion) { - throw new AssertionError(); - } + if (! assertion) { + throw new AssertionError(); + } } public static void main(String[] args) { - assertThat(test_and(0x21, 0x31) == 0x21); - assertThat(test_andc1(0xaaaaaaaa) == 0xa0a0a0a0); - assertThat(test_andc2(0xaaaaaaaa) == 0x02200280); + assertThat(test_and(0x21, 0x31) == 0x21); + assertThat(test_andc1(0xaaaaaaaa) == 0xa0a0a0a0); + assertThat(test_andc2(0xaaaaaaaa) == 0x02200280); - assertThat(test_or(0x21, 0x31) == 0x31); - assertThat(test_orc1(0xaaaaaaaa) == 0xfafafafa); - assertThat(test_orc2(0xaaaaaaaa) == 0xbabefeff); + assertThat(test_or(0x21, 0x31) == 0x31); + assertThat(test_orc1(0xaaaaaaaa) == 0xfafafafa); + assertThat(test_orc2(0xaaaaaaaa) == 0xbabefeff); - assertThat(test_xor(0x21, 0x31) == 16); - assertThat(test_xorc1(0xaaaaaaaa) == 0x5a5a5a5a); - assertThat(test_xorc2(0xaaaaaaaa) == 0xb89efc7f); + assertThat(test_xor(0x21, 0x31) == 16); + assertThat(test_xorc1(0xaaaaaaaa) == 0x5a5a5a5a); + assertThat(test_xorc2(0xaaaaaaaa) == 0xb89efc7f); } } -
--- a/test/aarch64/IntShiftTests.java Fri Feb 05 20:19:33 2021 +0000 +++ b/test/aarch64/IntShiftTests.java Thu Apr 22 01:38:42 2021 +0100 @@ -1,78 +1,77 @@ public class IntShiftTests { private static int test_shl(int a, int b) { - return a << b; + return a << b; } private static int test_shlc1(int a) { - return a << 1; + return a << 1; } private static int test_shlc33(int a) { - return a << 33; + return a << 33; } private static int test_shr(int a, int b) { - return a >> b; + return a >> b; } private static int test_shrc1(int a) { - return a >> 1; + return a >> 1; } private static int test_shrc33(int a) { - return a >> 33; + return a >> 33; } private static int test_ushr(int a, int b) { - return a >>> b; + return a >>> b; } private static int test_ushrc1(int a) { - return a >>> 1; + return a >>> 1; } private static int test_ushrc33(int a) { - return a >>> 33; + return a >>> 33; } private static void assertThat(boolean assertion) { - if (! assertion) { - throw new AssertionError(); - } + if (! assertion) { + throw new AssertionError(); + } } public static void main(String[] args) { - assertThat(test_shl(32, 2) == 128); - assertThat(test_shl(0x80000000, 1) == 0); - assertThat(test_shl(0x40000000, 1) == 0x80000000); - assertThat(test_shl(0x40000000, 33) == 0x80000000); - - assertThat(test_shr(32, 2) == 8); - assertThat(test_shr(1, 1) == 0); - assertThat(test_shr(0x80000000, 1) == 0xc0000000); - assertThat(test_shr(0x40000000, 33) == 0x20000000); + assertThat(test_shl(32, 2) == 128); + assertThat(test_shl(0x80000000, 1) == 0); + assertThat(test_shl(0x40000000, 1) == 0x80000000); + assertThat(test_shl(0x40000000, 33) == 0x80000000); - assertThat(test_ushr(32, 2) == 8); - assertThat(test_ushr(1, 1) == 0); - assertThat(test_ushr(0x80000000, 1) == 0x40000000); - assertThat(test_ushr(0x40000000, 33) == 0x20000000); + assertThat(test_shr(32, 2) == 8); + assertThat(test_shr(1, 1) == 0); + assertThat(test_shr(0x80000000, 1) == 0xc0000000); + assertThat(test_shr(0x40000000, 33) == 0x20000000); + + assertThat(test_ushr(32, 2) == 8); + assertThat(test_ushr(1, 1) == 0); + assertThat(test_ushr(0x80000000, 1) == 0x40000000); + assertThat(test_ushr(0x40000000, 33) == 0x20000000); - assertThat(test_shlc1(32) == 64); - assertThat(test_shlc1(0x80000000) == 0); - assertThat(test_shlc1(0x40000000) == 0x80000000); - assertThat(test_shlc33(0x40000000) == 0x80000000); - - assertThat(test_shrc1(32) == 16); - assertThat(test_shrc1(1) == 0); - assertThat(test_shrc1(0x80000000) == 0xc0000000); - assertThat(test_shrc33(0x40000000) == 0x20000000); + assertThat(test_shlc1(32) == 64); + assertThat(test_shlc1(0x80000000) == 0); + assertThat(test_shlc1(0x40000000) == 0x80000000); + assertThat(test_shlc33(0x40000000) == 0x80000000); - assertThat(test_ushrc1(32) == 16); - assertThat(test_ushrc1(1) == 0); - assertThat(test_ushrc1(0x80000000) == 0x40000000); - assertThat(test_ushrc33(0x40000000) == 0x20000000); + assertThat(test_shrc1(32) == 16); + assertThat(test_shrc1(1) == 0); + assertThat(test_shrc1(0x80000000) == 0xc0000000); + assertThat(test_shrc33(0x40000000) == 0x20000000); + + assertThat(test_ushrc1(32) == 16); + assertThat(test_ushrc1(1) == 0); + assertThat(test_ushrc1(0x80000000) == 0x40000000); + assertThat(test_ushrc33(0x40000000) == 0x20000000); } } -
--- a/test/aarch64/LongArithTests.java Fri Feb 05 20:19:33 2021 +0000 +++ b/test/aarch64/LongArithTests.java Thu Apr 22 01:38:42 2021 +0100 @@ -9,124 +9,124 @@ private static final long IIMM24_5 = 0x1001000; // Should not encode as imm private static long test_neg(long a) { - return -a; + return -a; } private static long test_add(long a, long b) { - return a + b; + return a + b; } private static long test_addc0(long a) { - return a + IIMM12_0; + return a + IIMM12_0; } private static long test_addc1(long a) { - return a + IIMM12_1; + return a + IIMM12_1; } private static long test_addc2(long a) { - return a + IIMM12_2; + return a + IIMM12_2; } private static long test_addc3(long a) { - return a + IIMM24_3; + return a + IIMM24_3; } private static long test_addc4(long a) { - return a + IIMM24_4; + return a + IIMM24_4; } private static long test_addc5(long a) { - return a + IIMM24_5; + return a + IIMM24_5; } private static long test_sub(long a, long b) { - return a - b; + return a - b; } private static long test_subc1(long a) { - return a - 11; + return a - 11; } private static long test_mulc1(long a) { - // Generates shl. - return a * 8; + // Generates shl. + return a * 8; } private static long test_mulc2(long a) { - // Generates shl followed by add. - return a * 9; + // Generates shl followed by add. + return a * 9; } private static long test_mulc3(long a) { - // Generates shl followed by sub. - return a * 7; + // Generates shl followed by sub. + return a * 7; } private static long test_mulc4(long a) { - // Generates normal mul. - return a * 10; + // Generates normal mul. + return a * 10; } private static long test_mul(long a, long b) { - // Generates normal mul. - return a * b; + // Generates normal mul. + return a * b; } private static long test_div(long a, long b) { - return a / b; + return a / b; } private static long test_rem(long a, long b) { - return a % b; + return a % b; } private static void assertThat(boolean assertion) { - if (! assertion) { - throw new AssertionError(); - } + if (! assertion) { + throw new AssertionError(); + } } public static void main(String[] args) { - assertThat(test_neg(10) == -10); - assertThat(test_add(3, 2) == 5); - assertThat(test_add(Long.MAX_VALUE, 1) == Long.MIN_VALUE); - assertThat(test_addc0(3) == 4); - assertThat(test_addc1(3) == 0x1002); - assertThat(test_addc2(3) == 0x1004); - assertThat(test_addc3(3) == 0x1003); - assertThat(test_addc4(3) == 0xfff003); - assertThat(test_addc5(3) == 0x1001003); + assertThat(test_neg(10) == -10); + assertThat(test_add(3, 2) == 5); + assertThat(test_add(Long.MAX_VALUE, 1) == Long.MIN_VALUE); + assertThat(test_addc0(3) == 4); + assertThat(test_addc1(3) == 0x1002); + assertThat(test_addc2(3) == 0x1004); + assertThat(test_addc3(3) == 0x1003); + assertThat(test_addc4(3) == 0xfff003); + assertThat(test_addc5(3) == 0x1001003); - assertThat(test_sub(40, 13) == 27); - assertThat(test_sub(Long.MIN_VALUE, 1) == Long.MAX_VALUE); - assertThat(test_subc1(40) == 29); + assertThat(test_sub(40, 13) == 27); + assertThat(test_sub(Long.MIN_VALUE, 1) == Long.MAX_VALUE); + assertThat(test_subc1(40) == 29); - assertThat(test_mulc1(5) == 40); - assertThat(test_mulc2(5) == 45); - assertThat(test_mulc3(5) == 35); - assertThat(test_mulc4(5) == 50); - assertThat(test_mul(5, 200) == 1000); + assertThat(test_mulc1(5) == 40); + assertThat(test_mulc2(5) == 45); + assertThat(test_mulc3(5) == 35); + assertThat(test_mulc4(5) == 50); + assertThat(test_mul(5, 200) == 1000); - assertThat(test_div(30, 3) == 10); - assertThat(test_div(29, 3) == 9); - assertThat(test_div(Long.MIN_VALUE, -1) == Long.MIN_VALUE); - try { - test_div(30, 0); - throw new AssertionError(); - } catch (ArithmeticException ex) { - // Pass. - } + assertThat(test_div(30, 3) == 10); + assertThat(test_div(29, 3) == 9); + assertThat(test_div(Long.MIN_VALUE, -1) == Long.MIN_VALUE); + try { + test_div(30, 0); + throw new AssertionError(); + } catch (ArithmeticException ex) { + // Pass. + } - assertThat(test_rem(30, 3) == 0); - assertThat(test_rem(29, 3) == 2); - assertThat(test_rem(Long.MIN_VALUE, -1) == 0); - try { - test_rem(30, 0); - throw new AssertionError(); - } catch (ArithmeticException ex) { - // Pass. - } + assertThat(test_rem(30, 3) == 0); + assertThat(test_rem(29, 3) == 2); + assertThat(test_rem(Long.MIN_VALUE, -1) == 0); + try { + test_rem(30, 0); + throw new AssertionError(); + } catch (ArithmeticException ex) { + // Pass. + } } }
--- a/test/aarch64/LongCmpTests.java Fri Feb 05 20:19:33 2021 +0000 +++ b/test/aarch64/LongCmpTests.java Thu Apr 22 01:38:42 2021 +0100 @@ -2,101 +2,101 @@ public class LongCmpTests { private static boolean test_isEq(long a, long b) { - return a == b; + return a == b; } private static boolean test_isNe(long a, long b) { - return a != b; + return a != b; } private static boolean test_isLt(long a, long b) { - return a < b; + return a < b; } private static boolean test_isLe(long a, long b) { - return a <= b; + return a <= b; } private static boolean test_isGe(long a, long b) { - return a >= b; + return a >= b; } private static boolean test_isGt(long a, long b) { - return a > b; + return a > b; } private static boolean test_isEqC(long a) { - return a == 7L; + return a == 7L; } private static boolean test_isNeC(long a) { - return a != 7L; + return a != 7L; } private static boolean test_isLtC(long a) { - return a < 7L; + return a < 7L; } private static boolean test_isLeC(long a) { - return a <= 7L; + return a <= 7L; } private static boolean test_isGeC(long a) { - return a >= 7L; + return a >= 7L; } private static boolean test_isGtC(long a) { - return a > 7L; + return a > 7L; } private static void assertThat(boolean assertion) { - if (! assertion) { - throw new AssertionError(); - } + if (! assertion) { + throw new AssertionError(); + } } public static void main(String[] args) { - assertThat(test_isEq(7L, 7L)); - assertThat(! test_isEq(70L, 7L)); - assertThat(! test_isNe(7L, 7L)); - assertThat(test_isNe(70L, 7L)); + assertThat(test_isEq(7L, 7L)); + assertThat(! test_isEq(70L, 7L)); + assertThat(! test_isNe(7L, 7L)); + assertThat(test_isNe(70L, 7L)); - assertThat(test_isLt(7L, 70L)); - assertThat(! test_isLt(70L, 7L)); - assertThat(! test_isLt(7L, 7L)); + assertThat(test_isLt(7L, 70L)); + assertThat(! test_isLt(70L, 7L)); + assertThat(! test_isLt(7L, 7L)); - assertThat(test_isLe(7L, 70L)); - assertThat(! test_isLe(70L, 7L)); - assertThat(test_isLe(7L, 7L)); + assertThat(test_isLe(7L, 70L)); + assertThat(! test_isLe(70L, 7L)); + assertThat(test_isLe(7L, 7L)); - assertThat(!test_isGe(7L, 70L)); - assertThat(test_isGe(70L, 7L)); - assertThat(test_isGe(7L, 7L)); + assertThat(!test_isGe(7L, 70L)); + assertThat(test_isGe(70L, 7L)); + assertThat(test_isGe(7L, 7L)); - assertThat(!test_isGt(7L, 70L)); - assertThat(test_isGt(70L, 7L)); - assertThat(! test_isGt(7L, 7L)); + assertThat(!test_isGt(7L, 70L)); + assertThat(test_isGt(70L, 7L)); + assertThat(! test_isGt(7L, 7L)); - assertThat(test_isEqC(7L)); - assertThat(! test_isEqC(70L)); - assertThat(! test_isNeC(7L)); - assertThat(test_isNeC(70L)); + assertThat(test_isEqC(7L)); + assertThat(! test_isEqC(70L)); + assertThat(! test_isNeC(7L)); + assertThat(test_isNeC(70L)); - assertThat(test_isLtC(6L)); - assertThat(! test_isLtC(70L)); - assertThat(! test_isLtC(7L)); + assertThat(test_isLtC(6L)); + assertThat(! test_isLtC(70L)); + assertThat(! test_isLtC(7L)); - assertThat(test_isLeC(6L)); - assertThat(! test_isLeC(70L)); - assertThat(test_isLeC(7L)); + assertThat(test_isLeC(6L)); + assertThat(! test_isLeC(70L)); + assertThat(test_isLeC(7L)); - assertThat(!test_isGeC(6L)); - assertThat(test_isGeC(70L)); - assertThat(test_isGeC(7L)); + assertThat(!test_isGeC(6L)); + assertThat(test_isGeC(70L)); + assertThat(test_isGeC(7L)); - assertThat(!test_isGtC(6L)); - assertThat(test_isGtC(70L)); - assertThat(! test_isGtC(7L)); + assertThat(!test_isGtC(6L)); + assertThat(test_isGtC(70L)); + assertThat(! test_isGtC(7L)); } }
--- a/test/aarch64/LongLogicTests.java Fri Feb 05 20:19:33 2021 +0000 +++ b/test/aarch64/LongLogicTests.java Thu Apr 22 01:38:42 2021 +0100 @@ -3,66 +3,65 @@ private static final long IMM = 0xf0f0f0f0f0f0f0f0L; private static final long NO_IMM = 0x123456d5123456d5L; private static long test_and(long a, long b) { - return a & b; + return a & b; } private static long test_andc1(long a) { - // Generates immediate instruction. - return a & IMM; + // Generates immediate instruction. + return a & IMM; } private static long test_andc2(long a) { - // Generates non-immediate instruction. - return a & NO_IMM; + // Generates non-immediate instruction. + return a & NO_IMM; } private static long test_or(long a, long b) { - return a | b; + return a | b; } private static long test_orc1(long a) { - // Generates immediate instruction. - return a | IMM; + // Generates immediate instruction. + return a | IMM; } private static long test_orc2(long a) { - // Generates non-immediate instruction. - return a | NO_IMM; + // Generates non-immediate instruction. + return a | NO_IMM; } private static long test_xor(long a, long b) { - return a ^ b; + return a ^ b; } private static long test_xorc1(long a) { - // Generates immediate instruction. - return a ^ IMM; + // Generates immediate instruction. + return a ^ IMM; } private static long test_xorc2(long a) { - // Generates non-immediate instruction. - return a ^ NO_IMM; + // Generates non-immediate instruction. + return a ^ NO_IMM; } private static void assertThat(boolean assertion) { - if (! assertion) { - throw new AssertionError(); - } + if (! assertion) { + throw new AssertionError(); + } } public static void main(String[] args) { - assertThat(test_and(0x21, 0x31) == 0x21); - assertThat(test_andc1(0xaaaaaaaaaaaaaaaaL) == 0xa0a0a0a0a0a0a0a0L); - assertThat(test_andc2(0xaaaaaaaaaaaaaaaaL) == 0x0220028002200280L); + assertThat(test_and(0x21, 0x31) == 0x21); + assertThat(test_andc1(0xaaaaaaaaaaaaaaaaL) == 0xa0a0a0a0a0a0a0a0L); + assertThat(test_andc2(0xaaaaaaaaaaaaaaaaL) == 0x0220028002200280L); - assertThat(test_or(0x21, 0x31) == 0x31); - assertThat(test_orc1(0xaaaaaaaaaaaaaaaaL) == 0xfafafafafafafafaL); - assertThat(test_orc2(0xaaaaaaaaaaaaaaaaL) == 0xbabefeffbabefeffL); + assertThat(test_or(0x21, 0x31) == 0x31); + assertThat(test_orc1(0xaaaaaaaaaaaaaaaaL) == 0xfafafafafafafafaL); + assertThat(test_orc2(0xaaaaaaaaaaaaaaaaL) == 0xbabefeffbabefeffL); - assertThat(test_xor(0x21, 0x31) == 16); - assertThat(test_xorc1(0xaaaaaaaaaaaaaaaaL) == 0x5a5a5a5a5a5a5a5aL); - assertThat(test_xorc2(0xaaaaaaaaaaaaaaaaL) == 0xb89efc7fb89efc7fL); + assertThat(test_xor(0x21, 0x31) == 16); + assertThat(test_xorc1(0xaaaaaaaaaaaaaaaaL) == 0x5a5a5a5a5a5a5a5aL); + assertThat(test_xorc2(0xaaaaaaaaaaaaaaaaL) == 0xb89efc7fb89efc7fL); } } -
--- a/test/aarch64/LongShiftTests.java Fri Feb 05 20:19:33 2021 +0000 +++ b/test/aarch64/LongShiftTests.java Thu Apr 22 01:38:42 2021 +0100 @@ -1,77 +1,77 @@ public class LongShiftTests { private static long test_shl(long a, long b) { - return a << b; + return a << b; } private static long test_shlc1(long a) { - return a << 1; + return a << 1; } private static long test_shlc65(long a) { - return a << 65; + return a << 65; } private static long test_shr(long a, long b) { - return a >> b; + return a >> b; } private static long test_shrc1(long a) { - return a >> 1; + return a >> 1; } private static long test_shrc65(long a) { - return a >> 65; + return a >> 65; } private static long test_ushr(long a, long b) { - return a >>> b; + return a >>> b; } private static long test_ushrc1(long a) { - return a >>> 1; + return a >>> 1; } private static long test_ushrc65(long a) { - return a >>> 65; + return a >>> 65; } private static void assertThat(boolean assertion) { - if (! assertion) { - throw new AssertionError(); - } + if (! assertion) { + throw new AssertionError(); + } } public static void main(String[] args) { - assertThat(test_shl(32, 2) == 128); - assertThat(test_shl(0x8000000000000000L, 1) == 0); - assertThat(test_shl(0x4000000000000000L, 1) == 0x8000000000000000L); - assertThat(test_shl(0x4000000000000000L, 65) == 0x8000000000000000L); - - assertThat(test_shr(32, 2) == 8); - assertThat(test_shr(1, 1) == 0); - assertThat(test_shr(0x8000000000000000L, 1) == 0xc000000000000000L); - assertThat(test_shr(0x4000000000000000L, 65) == 0x2000000000000000L); + assertThat(test_shl(32, 2) == 128); + assertThat(test_shl(0x8000000000000000L, 1) == 0); + assertThat(test_shl(0x4000000000000000L, 1) == 0x8000000000000000L); + assertThat(test_shl(0x4000000000000000L, 65) == 0x8000000000000000L); - assertThat(test_ushr(32, 2) == 8); - assertThat(test_ushr(1, 1) == 0); - assertThat(test_ushr(0x8000000000000000L, 1) == 0x4000000000000000L); - assertThat(test_ushr(0x4000000000000000L, 65) == 0x2000000000000000L); + assertThat(test_shr(32, 2) == 8); + assertThat(test_shr(1, 1) == 0); + assertThat(test_shr(0x8000000000000000L, 1) == 0xc000000000000000L); + assertThat(test_shr(0x4000000000000000L, 65) == 0x2000000000000000L); + + assertThat(test_ushr(32, 2) == 8); + assertThat(test_ushr(1, 1) == 0); + assertThat(test_ushr(0x8000000000000000L, 1) == 0x4000000000000000L); + assertThat(test_ushr(0x4000000000000000L, 65) == 0x2000000000000000L); - assertThat(test_shlc1(32) == 64); - assertThat(test_shlc1(0x8000000000000000L) == 0); - assertThat(test_shlc1(0x4000000000000000L) == 0x8000000000000000L); - assertThat(test_shlc65(0x4000000000000000L) == 0x8000000000000000L); - - assertThat(test_shrc1(32) == 16); - assertThat(test_shrc1(1) == 0); - assertThat(test_shrc1(0x8000000000000000L) == 0xc000000000000000L); - assertThat(test_shrc65(0x4000000000000000L) == 0x2000000000000000L); + assertThat(test_shlc1(32) == 64); + assertThat(test_shlc1(0x8000000000000000L) == 0); + assertThat(test_shlc1(0x4000000000000000L) == 0x8000000000000000L); + assertThat(test_shlc65(0x4000000000000000L) == 0x8000000000000000L); - assertThat(test_ushrc1(32) == 16); - assertThat(test_ushrc1(1) == 0); - assertThat(test_ushrc1(0x8000000000000000L) == 0x4000000000000000L); - assertThat(test_ushrc65(0x4000000000000000L) == 0x2000000000000000L); + assertThat(test_shrc1(32) == 16); + assertThat(test_shrc1(1) == 0); + assertThat(test_shrc1(0x8000000000000000L) == 0xc000000000000000L); + assertThat(test_shrc65(0x4000000000000000L) == 0x2000000000000000L); + + assertThat(test_ushrc1(32) == 16); + assertThat(test_ushrc1(1) == 0); + assertThat(test_ushrc1(0x8000000000000000L) == 0x4000000000000000L); + assertThat(test_ushrc65(0x4000000000000000L) == 0x2000000000000000L); } }