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changeset 5691:80e04c4cd4b2

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Add support for pipeline scheduling
author adinn
date Tue, 25 Nov 2014 17:36:55 +0000
parents 56958c314918
children 205e1ae8868b
files src/cpu/aarch64/vm/aarch64.ad src/cpu/aarch64/vm/aarch64_ad.m4 src/cpu/aarch64/vm/vm_version_aarch64.cpp
diffstat 3 files changed, 767 insertions(+), 367 deletions(-) [+]
line wrap: on
line diff
--- a/src/cpu/aarch64/vm/aarch64.ad	Tue Nov 25 11:10:14 2014 +0000
+++ b/src/cpu/aarch64/vm/aarch64.ad	Tue Nov 25 17:36:55 2014 +0000
@@ -4697,17 +4697,14 @@
 attributes %{
   // ARM instructions are of fixed length
   fixed_size_instructions;        // Fixed size instructions TODO does
-  // TODO does this relate to how many instructions can be scheduled
-  // at once? just guess 8 for now
-  max_instructions_per_bundle = 8;   // Up to 8 instructions per bundle
+  max_instructions_per_bundle = 2;   // A53 = 2, A57 = 4
   // ARM instructions come in 32-bit word units
   instruction_unit_size = 4;         // An instruction is 4 bytes long
-  // TODO identify correct cache line size  just guess 64 for now
   instruction_fetch_unit_size = 64;  // The processor fetches one line
   instruction_fetch_units = 1;       // of 64 bytes
 
   // List of nop instructions
-  //nops( MachNop );
+  nops( MachNop );
 %}
 
 // We don't use an actual pipeline model so don't care about resources
@@ -4717,21 +4714,387 @@
 //----------RESOURCES----------------------------------------------------------
 // Resources are the functional units available to the machine
 
-resources( D0, D1, D2, DECODE = D0 | D1 | D2,
-           MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
-           BR, FPU,
-           ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
+resources( INS0, INS1, INS01 = INS0 | INS1,
+           ALU0, ALU1, ALU = ALU0 | ALU1,
+           MAC,
+           DIV,
+           BRANCH,
+           LDST,
+           NEON_FP);
 
 //----------PIPELINE DESCRIPTION-----------------------------------------------
 // Pipeline Description specifies the stages in the machine's pipeline
 
 // Generic P2/P3 pipeline
-pipe_desc(S0, S1, S2, S3, S4, S5);
+pipe_desc(ISS, EX1, EX2, WR);
 
 //----------PIPELINE CLASSES---------------------------------------------------
 // Pipeline Classes describe the stages in which input and output are
 // referenced by the hardware pipeline.
 
+//------- Integer ALU operations --------------------------
+
+// Integer ALU reg-reg operation
+// Operands needed in EX1, result generated in EX2
+// Eg.	ADD	x0, x1, x2
+pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
+%{
+  single_instruction;
+  dst    : EX2(write);
+  src1   : EX1(read);
+  src2   : EX1(read);
+  INS01  : ISS; // Dual issue as instruction 0 or 1
+  ALU    : EX2;
+%}
+
+// Integer ALU reg-reg operation with constant shift
+// Shifted register must be available in LATE_ISS instead of EX1
+// Eg.	ADD	x0, x1, x2, LSL #2
+pipe_class ialu_reg_reg_shift(iRegI dst, iRegI src1, iRegI src2, immI shift)
+%{
+  single_instruction;
+  dst    : EX2(write);
+  src1   : EX1(read);
+  src2   : ISS(read);
+  INS01  : ISS;
+  ALU    : EX2;
+%}
+
+// Integer ALU reg operation with constant shift
+// Eg.	LSL	x0, x1, #shift
+pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
+%{
+  single_instruction;
+  dst    : EX2(write);
+  src1   : ISS(read);
+  INS01  : ISS;
+  ALU    : EX2;
+%}
+
+// Integer ALU reg-reg operation with variable shift
+// Both operands must be available in LATE_ISS instead of EX1
+// Result is available in EX1 instead of EX2
+// Eg.	LSLV	x0, x1, x2
+pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
+%{
+  single_instruction;
+  dst    : EX1(write);
+  src1   : ISS(read);
+  src2   : ISS(read);
+  INS01  : ISS;
+  ALU    : EX1;
+%}
+
+// Integer ALU reg-reg operation with extract
+// As for _vshift above, but result generated in EX2
+// Eg.	EXTR	x0, x1, x2, #N
+pipe_class ialu_reg_reg_extr(iRegI dst, iRegI src1, iRegI src2)
+%{
+  single_instruction;
+  dst    : EX2(write);
+  src1   : ISS(read);
+  src2   : ISS(read);
+  INS1   : ISS; // Can only dual issue as Instruction 1
+  ALU    : EX1;
+%}
+
+// Integer ALU reg operation
+// Eg.	NEG	x0, x1
+pipe_class ialu_reg(iRegI dst, iRegI src)
+%{
+  single_instruction;
+  dst    : EX2(write);
+  src    : EX1(read);
+  INS01  : ISS;
+  ALU    : EX2;
+%}
+
+// Integer ALU reg mmediate operation
+// Eg.	ADD	x0, x1, #N
+pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
+%{
+  single_instruction;
+  dst    : EX2(write);
+  src1   : EX1(read);
+  INS01  : ISS;
+  ALU    : EX2;
+%}
+
+// Integer ALU immediate operation (no source operands)
+// Eg.	MOV	x0, #N
+pipe_class ialu_imm(iRegI dst)
+%{
+  single_instruction;
+  dst    : EX1(write);
+  INS01  : ISS;
+  ALU    : EX1;
+%}
+
+//------- Compare operation -------------------------------
+
+// Compare reg-reg
+// Eg.	CMP	x0, x1
+pipe_class icmp_reg_reg(rFlagsReg cr, iRegI op1, iRegI op2)
+%{
+  single_instruction;
+//  fixed_latency(16);
+  cr     : EX2(write);
+  op1    : EX1(read);
+  op2    : EX1(read);
+  INS01  : ISS;
+  ALU    : EX2;
+%}
+
+// Compare reg-reg
+// Eg.	CMP	x0, #N
+pipe_class icmp_reg_imm(rFlagsReg cr, iRegI op1)
+%{
+  single_instruction;
+//  fixed_latency(16);
+  cr     : EX2(write);
+  op1    : EX1(read);
+  INS01  : ISS;
+  ALU    : EX2;
+%}
+
+//------- Conditional instructions ------------------------
+
+// Conditional no operands
+// Eg.	CSINC	x0, zr, zr, <cond>
+pipe_class icond_none(iRegI dst, rFlagsReg cr)
+%{
+  single_instruction;
+  cr     : EX1(read);
+  dst    : EX2(write);
+  INS01  : ISS;
+  ALU    : EX2;
+%}
+
+// Conditional 2 operand
+// EG.	CSEL	X0, X1, X2, <cond>
+pipe_class icond_reg_reg(iRegI dst, iRegI src1, iRegI src2, rFlagsReg cr)
+%{
+  single_instruction;
+  cr     : EX1(read);
+  src1   : EX1(read);
+  src2   : EX1(read);
+  dst    : EX2(write);
+  INS01  : ISS;
+  ALU    : EX2;
+%}
+
+// Conditional 2 operand
+// EG.	CSEL	X0, X1, X2, <cond>
+pipe_class icond_reg(iRegI dst, iRegI src, rFlagsReg cr)
+%{
+  single_instruction;
+  cr     : EX1(read);
+  src    : EX1(read);
+  dst    : EX2(write);
+  INS01  : ISS;
+  ALU    : EX2;
+%}
+
+//------- Multiply pipeline operations --------------------
+
+// Multiply reg-reg
+// Eg.	MUL	w0, w1, w2
+pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
+%{
+  single_instruction;
+  dst    : WR(write);
+  src1   : ISS(read);
+  src2   : ISS(read);
+  INS01  : ISS;
+  MAC    : WR;
+%}
+
+// Multiply accumulate
+// Eg.	MADD	w0, w1, w2, w3
+pipe_class imac_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3)
+%{
+  single_instruction;
+  dst    : WR(write);
+  src1   : ISS(read);
+  src2   : ISS(read);
+  src3   : ISS(read);
+  INS01  : ISS;
+  MAC    : WR;
+%}
+
+// Eg.	MUL	w0, w1, w2
+pipe_class lmul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
+%{
+  single_instruction;
+  fixed_latency(3); // Maximum latency for 64 bit mul
+  dst    : WR(write);
+  src1   : ISS(read);
+  src2   : ISS(read);
+  INS01  : ISS;
+  MAC    : WR;
+%}
+
+// Multiply accumulate
+// Eg.	MADD	w0, w1, w2, w3
+pipe_class lmac_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3)
+%{
+  single_instruction;
+  fixed_latency(3); // Maximum latency for 64 bit mul
+  dst    : WR(write);
+  src1   : ISS(read);
+  src2   : ISS(read);
+  src3   : ISS(read);
+  INS01  : ISS;
+  MAC    : WR;
+%}
+
+//------- Divide pipeline operations --------------------
+
+// Eg.	SDIV	w0, w1, w2
+pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
+%{
+  single_instruction;
+  fixed_latency(8); // Maximum latency for 32 bit divide
+  dst    : WR(write);
+  src1   : ISS(read);
+  src2   : ISS(read);
+  INS0   : ISS; // Can only dual issue as instruction 0
+  DIV    : WR;
+%}
+
+// Eg.	SDIV	x0, x1, x2
+pipe_class ldiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
+%{
+  single_instruction;
+  fixed_latency(16); // Maximum latency for 64 bit divide
+  dst    : WR(write);
+  src1   : ISS(read);
+  src2   : ISS(read);
+  INS0   : ISS; // Can only dual issue as instruction 0
+  DIV    : WR;
+%}
+
+//------- Load pipeline operations ------------------------
+
+// Load - prefetch
+// Eg.	PFRM	<mem>
+pipe_class iload_prefetch(memory mem)
+%{
+  single_instruction;
+  mem    : ISS(read);
+  INS01  : ISS;
+  LDST   : WR;
+%}
+
+// Load - reg, mem
+// Eg.	LDR	x0, <mem>
+pipe_class iload_reg_mem(iRegI dst, memory mem)
+%{
+  single_instruction;
+  dst    : WR(write);
+  mem    : ISS(read);
+  INS01  : ISS;
+  LDST   : WR;
+%}
+
+// Load - reg, reg
+// Eg.	LDR	x0, [sp, x1]
+pipe_class iload_reg_reg(iRegI dst, iRegI src)
+%{
+  single_instruction;
+  dst    : WR(write);
+  src    : ISS(read);
+  INS01  : ISS;
+  LDST   : WR;
+%}
+
+//------- Store pipeline operations -----------------------
+
+// Store - zr, mem
+// Eg.	STR	zr, <mem>
+pipe_class istore_mem(memory mem)
+%{
+  single_instruction;
+  mem    : ISS(read);
+  INS01  : ISS;
+  LDST   : WR;
+%}
+
+// Store - reg, mem
+// Eg.	STR	x0, <mem>
+pipe_class istore_reg_mem(iRegI src, memory mem)
+%{
+  single_instruction;
+  mem    : ISS(read);
+  src    : EX2(read);
+  INS01  : ISS;
+  LDST   : WR;
+%}
+
+// Store - reg, reg
+// Eg. STR	x0, [sp, x1]
+pipe_class istore_reg_reg(iRegI dst, iRegI src)
+%{
+  single_instruction;
+  dst    : ISS(read);
+  src    : EX2(read);
+  INS01  : ISS;
+  LDST   : WR;
+%}
+
+//------- Store pipeline operations -----------------------
+
+// Branch
+pipe_class pipe_branch()
+%{
+  single_instruction;
+  INS01  : ISS;
+  BRANCH : EX1;
+%}
+
+// Conditional branch
+pipe_class pipe_branch_cond(rFlagsReg cr)
+%{
+  single_instruction;
+  cr     : EX1(read);
+  INS01  : ISS;
+  BRANCH : EX1;
+%}
+
+// Compare & Branch
+// EG.	CBZ/CBNZ
+pipe_class pipe_cmp_branch(iRegI op1)
+%{
+  single_instruction;
+  op1    : EX1(read);
+  INS01  : ISS;
+  BRANCH : EX1;
+%}
+
+//------- Synchronisation operations ----------------------
+
+// Any operation requiring serialization.
+// EG.	DMB/Atomic Ops/Load Acquire/Str Release
+pipe_class pipe_serial()
+%{
+  single_instruction;
+  force_serialization;
+  fixed_latency(16);
+  INS01  : ISS(2); // Cannot dual issue with any other instruction
+  LDST   : WR;
+%}
+
+// Generic big/slow expanded idiom - also serialized
+pipe_class pipe_slow()
+%{
+  instruction_count(10);
+  multiple_bundles;
+  force_serialization;
+  fixed_latency(16);
+  INS01  : ISS(2); // Cannot dual issue with any other instruction
+  LDST   : WR;
+%}
+
 // Empty pipeline class
 pipe_class pipe_class_empty()
 %{
@@ -4753,13 +5116,6 @@
   fixed_latency(16);
 %}
 
-// Pipeline class for traps.
-pipe_class pipe_class_trap()
-%{
-  single_instruction;
-  fixed_latency(100);
-%}
-
 // Pipeline class for memory operations.
 pipe_class pipe_class_memory()
 %{
@@ -4776,7 +5132,7 @@
 
 // Define the class for the Nop node.
 define %{
-   MachNop = pipe_class_default;
+  MachNop = pipe_class_empty;
 %}
 
 %}
@@ -4816,7 +5172,7 @@
 
   ins_encode(aarch64_enc_ldrsbw(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Byte (8 bit signed) into long
@@ -4829,7 +5185,7 @@
 
   ins_encode(aarch64_enc_ldrsb(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Byte (8 bit unsigned)
@@ -4842,7 +5198,7 @@
 
   ins_encode(aarch64_enc_ldrb(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Byte (8 bit unsigned) into long
@@ -4855,7 +5211,7 @@
 
   ins_encode(aarch64_enc_ldrb(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Short (16 bit signed)
@@ -4868,7 +5224,7 @@
 
   ins_encode(aarch64_enc_ldrshw(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Short (16 bit signed) into long
@@ -4881,7 +5237,7 @@
 
   ins_encode(aarch64_enc_ldrsh(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Char (16 bit unsigned)
@@ -4894,7 +5250,7 @@
 
   ins_encode(aarch64_enc_ldrh(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Short/Char (16 bit unsigned) into long
@@ -4907,7 +5263,7 @@
 
   ins_encode(aarch64_enc_ldrh(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Integer (32 bit signed)
@@ -4920,7 +5276,7 @@
 
   ins_encode(aarch64_enc_ldrw(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Integer (32 bit signed) into long
@@ -4933,7 +5289,7 @@
 
   ins_encode(aarch64_enc_ldrsw(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Integer (32 bit unsigned) into long
@@ -4946,7 +5302,7 @@
 
   ins_encode(aarch64_enc_ldrw(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Long (64 bit signed)
@@ -4959,7 +5315,7 @@
 
   ins_encode(aarch64_enc_ldr(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Range
@@ -4972,7 +5328,7 @@
 
   ins_encode(aarch64_enc_ldrw(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Pointer
@@ -4985,7 +5341,7 @@
 
   ins_encode(aarch64_enc_ldr(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Compressed Pointer
@@ -4998,7 +5354,7 @@
 
   ins_encode(aarch64_enc_ldrw(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Klass Pointer
@@ -5011,7 +5367,7 @@
 
   ins_encode(aarch64_enc_ldr(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Narrow Klass Pointer
@@ -5024,7 +5380,7 @@
 
   ins_encode(aarch64_enc_ldrw(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_mem);
 %}
 
 // Load Float
@@ -5064,7 +5420,7 @@
 
   ins_encode( aarch64_enc_movw_imm(dst, src) );
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_imm);
 %}
 
 // Load Long Constant
@@ -5077,7 +5433,7 @@
 
   ins_encode( aarch64_enc_mov_imm(dst, src) );
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_imm);
 %}
 
 // Load Pointer Constant
@@ -5093,7 +5449,7 @@
 
   ins_encode(aarch64_enc_mov_p(dst, con));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_imm);
 %}
 
 // Load Null Pointer Constant
@@ -5107,7 +5463,7 @@
 
   ins_encode(aarch64_enc_mov_p0(dst, con));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_imm);
 %}
 
 // Load Pointer Constant One
@@ -5121,7 +5477,7 @@
 
   ins_encode(aarch64_enc_mov_p1(dst, con));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_imm);
 %}
 
 // Load Poll Page Constant
@@ -5135,7 +5491,7 @@
 
   ins_encode(aarch64_enc_mov_poll_page(dst, con));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_imm);
 %}
 
 // Load Byte Map Base Constant
@@ -5149,7 +5505,7 @@
 
   ins_encode(aarch64_enc_mov_byte_map_base(dst, con));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_imm);
 %}
 
 // Load Narrow Pointer Constant
@@ -5163,7 +5519,7 @@
 
   ins_encode(aarch64_enc_mov_n(dst, con));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_imm);
 %}
 
 // Load Narrow Null Pointer Constant
@@ -5177,7 +5533,7 @@
 
   ins_encode(aarch64_enc_mov_n0(dst, con));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_imm);
 %}
 
 // Load Packed Float Constant
@@ -5253,7 +5609,7 @@
 
   ins_encode(aarch64_enc_strb0(mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(istore_mem);
 %}
 
 // Store Byte
@@ -5266,7 +5622,7 @@
 
   ins_encode(aarch64_enc_strb(src, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(istore_reg_mem);
 %}
 
 
@@ -5279,7 +5635,7 @@
 
   ins_encode(aarch64_enc_strb0(mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(istore_mem);
 %}
 
 // Store Char/Short
@@ -5292,7 +5648,7 @@
 
   ins_encode(aarch64_enc_strh(src, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(istore_reg_mem);
 %}
 
 instruct storeimmC0(immI0 zero, memory mem)
@@ -5304,7 +5660,7 @@
 
   ins_encode(aarch64_enc_strh0(mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(istore_mem);
 %}
 
 // Store Integer
@@ -5318,7 +5674,7 @@
 
   ins_encode(aarch64_enc_strw(src, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(istore_reg_mem);
 %}
 
 instruct storeimmI0(immI0 zero, memory mem)
@@ -5330,7 +5686,7 @@
 
   ins_encode(aarch64_enc_strw0(mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(istore_mem);
 %}
 
 // Store Long (64 bit signed)
@@ -5343,7 +5699,7 @@
 
   ins_encode(aarch64_enc_str(src, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(istore_reg_mem);
 %}
 
 // Store Long (64 bit signed)
@@ -5356,7 +5712,7 @@
 
   ins_encode(aarch64_enc_str0(mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(istore_mem);
 %}
 
 // Store Pointer
@@ -5369,7 +5725,7 @@
 
   ins_encode(aarch64_enc_str(src, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(istore_reg_mem);
 %}
 
 // Store Pointer
@@ -5382,7 +5738,7 @@
 
   ins_encode(aarch64_enc_str0(mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(istore_mem);
 %}
 
 // Save last Java PC to thread anchor
@@ -5499,7 +5855,7 @@
 
   ins_encode( aarch64_enc_prefetchr(mem) );
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_prefetch);
 %}
 
 instruct prefetchw( memory mem ) %{
@@ -5510,7 +5866,7 @@
 
   ins_encode( aarch64_enc_prefetchw(mem) );
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_prefetch);
 %}
 
 instruct prefetchnta( memory mem ) %{
@@ -5521,64 +5877,64 @@
 
   ins_encode( aarch64_enc_prefetchnta(mem) );
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_prefetch);
 %}
 
 // ============================================================================
 // BSWAP Instructions
 
-instruct bytes_reverse_int(iRegINoSp dst) %{
-  match(Set dst (ReverseBytesI dst));
-
-  ins_cost(INSN_COST);
-  format %{ "revw  $dst, $dst" %}
-
-  ins_encode %{
-    __ revw(as_Register($dst$$reg), as_Register($dst$$reg));
-  %}
-
-  ins_pipe( pipe_class_default );
-%}
-
-instruct bytes_reverse_long(iRegLNoSp dst) %{
-  match(Set dst (ReverseBytesL dst));
-
-  ins_cost(INSN_COST);
-  format %{ "rev  $dst, $dst" %}
-
-  ins_encode %{
-    __ rev(as_Register($dst$$reg), as_Register($dst$$reg));
-  %}
-
-  ins_pipe( pipe_class_default );
-%}
-
-instruct bytes_reverse_unsigned_short(iRegINoSp dst) %{
-  match(Set dst (ReverseBytesUS dst));
-
-  ins_cost(INSN_COST);
-  format %{ "rev16w  $dst, $dst" %}
-
-  ins_encode %{
-    __ rev16w(as_Register($dst$$reg), as_Register($dst$$reg));
-  %}
-
-  ins_pipe( pipe_class_default );
-%}
-
-instruct bytes_reverse_short(iRegINoSp dst) %{
-  match(Set dst (ReverseBytesS dst));
-
-  ins_cost(INSN_COST);
-  format %{ "rev16w  $dst, $dst\n\t"
+instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src) %{
+  match(Set dst (ReverseBytesI src));
+
+  ins_cost(INSN_COST);
+  format %{ "revw  $dst, $src" %}
+
+  ins_encode %{
+    __ revw(as_Register($dst$$reg), as_Register($src$$reg));
+  %}
+
+  ins_pipe(ialu_reg);
+%}
+
+instruct bytes_reverse_long(iRegLNoSp dst, iRegL src) %{
+  match(Set dst (ReverseBytesL src));
+
+  ins_cost(INSN_COST);
+  format %{ "rev  $dst, $src" %}
+
+  ins_encode %{
+    __ rev(as_Register($dst$$reg), as_Register($src$$reg));
+  %}
+
+  ins_pipe(ialu_reg);
+%}
+
+instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
+  match(Set dst (ReverseBytesUS src));
+
+  ins_cost(INSN_COST);
+  format %{ "rev16w  $dst, $src" %}
+
+  ins_encode %{
+    __ rev16w(as_Register($dst$$reg), as_Register($src$$reg));
+  %}
+
+  ins_pipe(ialu_reg);
+%}
+
+instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
+  match(Set dst (ReverseBytesS src));
+
+  ins_cost(INSN_COST);
+  format %{ "rev16w  $dst, $src\n\t"
             "sbfmw $dst, $dst, #0, #15" %}
 
   ins_encode %{
-    __ rev16w(as_Register($dst$$reg), as_Register($dst$$reg));
+    __ rev16w(as_Register($dst$$reg), as_Register($src$$reg));
     __ sbfmw(as_Register($dst$$reg), as_Register($dst$$reg), 0U, 15U);
   %}
 
-  ins_pipe( pipe_class_default );
+  ins_pipe(ialu_reg);
 %}
 
 // ============================================================================
@@ -5593,7 +5949,7 @@
     __ clzw(as_Register($dst$$reg), as_Register($src$$reg));
   %}
 
-  ins_pipe( pipe_class_default );
+  ins_pipe( ialu_reg );
 %}
 
 instruct countLeadingZerosL(iRegI dst, iRegL src) %{
@@ -5605,7 +5961,7 @@
     __ clz(as_Register($dst$$reg), as_Register($src$$reg));
   %}
 
-  ins_pipe( pipe_class_default );
+  ins_pipe( ialu_reg );
 %}
 
 instruct countTrailingZerosI(iRegI dst, iRegI src) %{
@@ -5619,7 +5975,7 @@
     __ clzw(as_Register($dst$$reg), as_Register($dst$$reg));
   %}
 
-  ins_pipe( pipe_class_default );
+  ins_pipe(ialu_reg );
 %}
 
 instruct countTrailingZerosL(iRegI dst, iRegL src) %{
@@ -5633,7 +5989,7 @@
     __ clz(as_Register($dst$$reg), as_Register($dst$$reg));
   %}
 
-  ins_pipe( pipe_class_default );
+  ins_pipe( pipe_serial );
 %}
 
 // ============================================================================
@@ -5650,7 +6006,7 @@
     __ membar(Assembler::Membar_mask_bits(Assembler::LoadLoad|Assembler::LoadStore));
   %}
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct membar_release()
@@ -5662,7 +6018,7 @@
   ins_encode %{
   __ membar(Assembler::AnyAny);
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct membar_volatile() %{
@@ -5675,7 +6031,7 @@
     __ membar(Assembler::AnyAny);
   %}
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct unnecessary_membar_volatile() %{
@@ -5697,7 +6053,7 @@
     __ membar(Assembler::StoreStore);
   %}
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct membar_acquire_lock() %{
@@ -5710,7 +6066,7 @@
     __ membar(Assembler::Membar_mask_bits(Assembler::LoadLoad|Assembler::LoadStore));
   %}
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct membar_release_lock() %{
@@ -5723,7 +6079,7 @@
     __ membar(Assembler::AnyAny);
   %}
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 // ============================================================================
@@ -5741,7 +6097,7 @@
     }
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 instruct castP2X(iRegLNoSp dst, iRegP src) %{
@@ -5756,7 +6112,7 @@
     }
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 // Convert oop into int for vectors alignment masking
@@ -5769,7 +6125,7 @@
     __ movw($dst$$Register, $src$$Register);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 // Convert compressed oop into int for vectors alignment masking
@@ -5785,7 +6141,7 @@
     __ movw($dst$$Register, $src$$Register);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 
@@ -5801,7 +6157,7 @@
     Register d = $dst$$Register;
     __ encode_heap_oop(d, s);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src, rFlagsReg cr) %{
@@ -5812,7 +6168,7 @@
   ins_encode %{
     __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 instruct decodeHeapOop(iRegPNoSp dst, iRegN src, rFlagsReg cr) %{
@@ -5826,7 +6182,7 @@
     Register d = $dst$$Register;
     __ decode_heap_oop(d, s);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src, rFlagsReg cr) %{
@@ -5840,7 +6196,7 @@
     Register d = $dst$$Register;
     __ decode_heap_oop_not_null(d, s);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 instruct checkCastPP(iRegPNoSp dst)
@@ -5912,7 +6268,7 @@
 
   ins_encode(aarch64_enc_ldaxr(dst, mem));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 // Conditional-store of the updated heap-top.
@@ -5937,7 +6293,7 @@
 
   ins_encode(aarch64_enc_stlxr(newval, heap_top_ptr));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 // this has to be implemented as a CAS
@@ -5954,7 +6310,7 @@
 
   ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_slow);
 %}
 
 // this has to be implemented as a CAS
@@ -5971,7 +6327,7 @@
 
   ins_encode(aarch64_enc_cmpxchgw(mem, oldval, newval));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_slow);
 %}
 
 // XXX No flag versions for CompareAndSwap{I,L,P,N} because matcher
@@ -5991,7 +6347,7 @@
  ins_encode(aarch64_enc_cmpxchgw(mem, oldval, newval),
             aarch64_enc_cset_eq(res));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_slow);
 %}
 
 instruct compareAndSwapL(iRegINoSp res, memory mem, iRegLNoSp oldval, iRegLNoSp newval, rFlagsReg cr) %{
@@ -6008,7 +6364,7 @@
  ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval),
             aarch64_enc_cset_eq(res));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_slow);
 %}
 
 instruct compareAndSwapP(iRegINoSp res, memory mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
@@ -6025,7 +6381,7 @@
  ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval),
             aarch64_enc_cset_eq(res));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_slow);
 %}
 
 instruct compareAndSwapN(iRegINoSp res, memory mem, iRegNNoSp oldval, iRegNNoSp newval, rFlagsReg cr) %{
@@ -6042,7 +6398,7 @@
  ins_encode(aarch64_enc_cmpxchgw(mem, oldval, newval),
             aarch64_enc_cset_eq(res));
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_slow);
 %}
 
 
@@ -6052,7 +6408,7 @@
   ins_encode %{
     __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct get_and_setL(indirect mem, iRegLNoSp newv, iRegL prev) %{
@@ -6061,7 +6417,7 @@
   ins_encode %{
     __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct get_and_setN(indirect mem, iRegNNoSp newv, iRegI prev) %{
@@ -6070,7 +6426,7 @@
   ins_encode %{
     __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct get_and_setP(indirect mem, iRegPNoSp newv, iRegP prev) %{
@@ -6079,7 +6435,7 @@
   ins_encode %{
     __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 
@@ -6090,7 +6446,7 @@
   ins_encode %{
     __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr) %{
@@ -6101,7 +6457,7 @@
   ins_encode %{
     __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAddSub incr) %{
@@ -6111,7 +6467,7 @@
   ins_encode %{
     __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAddSub incr) %{
@@ -6122,7 +6478,7 @@
   ins_encode %{
     __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr) %{
@@ -6132,7 +6488,7 @@
   ins_encode %{
     __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr) %{
@@ -6143,7 +6499,7 @@
   ins_encode %{
     __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAddSub incr) %{
@@ -6153,7 +6509,7 @@
   ins_encode %{
     __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAddSub incr) %{
@@ -6164,7 +6520,7 @@
   ins_encode %{
     __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 // ============================================================================
@@ -6193,7 +6549,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg_reg);
 %}
 
 instruct cmovUI_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegI src1, iRegI src2) %{
@@ -6209,7 +6565,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg_reg);
 %}
 
 // special cases where one arg is zero
@@ -6234,7 +6590,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovUI_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, iRegI src2) %{
@@ -6250,7 +6606,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovI_reg_zero(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegI src1, immI0 zero) %{
@@ -6266,7 +6622,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovUI_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegI src1, immI0 zero) %{
@@ -6282,7 +6638,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 // special case for creating a boolean 0 or 1
@@ -6306,7 +6662,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_none);
 %}
 
 instruct cmovUI_reg_zero_one(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, immI_1 one) %{
@@ -6325,7 +6681,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_none);
 %}
 
 instruct cmovL_reg_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
@@ -6341,7 +6697,7 @@
             (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg_reg);
 %}
 
 instruct cmovUL_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
@@ -6357,7 +6713,7 @@
             (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg_reg);
 %}
 
 // special cases where one arg is zero
@@ -6375,7 +6731,7 @@
             (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovUL_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src1, immL0 zero) %{
@@ -6391,7 +6747,7 @@
             (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovL_zero_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, immL0 zero, iRegL src2) %{
@@ -6407,7 +6763,7 @@
             (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovUL_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, immL0 zero, iRegL src2) %{
@@ -6439,7 +6795,7 @@
             (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg_reg);
 %}
 
 instruct cmovUP_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, iRegP src1, iRegP src2) %{
@@ -6455,7 +6811,7 @@
             (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg_reg);
 %}
 
 // special cases where one arg is zero
@@ -6473,7 +6829,7 @@
             (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovUP_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, iRegP src1, immP0 zero) %{
@@ -6489,7 +6845,7 @@
             (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovP_zero_reg(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, immP0 zero, iRegP src2) %{
@@ -6505,7 +6861,7 @@
             (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovUP_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, immP0 zero, iRegP src2) %{
@@ -6521,7 +6877,7 @@
             (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovN_reg_reg(cmpOp cmp, rFlagsReg cr, iRegNNoSp dst, iRegN src1, iRegN src2) %{
@@ -6537,7 +6893,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg_reg);
 %}
 
 instruct cmovUN_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegNNoSp dst, iRegN src1, iRegN src2) %{
@@ -6553,7 +6909,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg_reg);
 %}
 
 // special cases where one arg is zero
@@ -6571,7 +6927,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovUN_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegNNoSp dst, iRegN src1, immN0 zero) %{
@@ -6587,7 +6943,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovN_zero_reg(cmpOp cmp, rFlagsReg cr, iRegNNoSp dst, immN0 zero, iRegN src2) %{
@@ -6603,7 +6959,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovUN_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegNNoSp dst, immN0 zero, iRegN src2) %{
@@ -6619,7 +6975,7 @@
              (Assembler::Condition)$cmp$$cmpcode);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(icond_reg);
 %}
 
 instruct cmovF_reg(cmpOp cmp, rFlagsReg cr, vRegF dst, vRegF src1,  vRegF src2)
@@ -6718,7 +7074,7 @@
             as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct addI_reg_imm(iRegINoSp dst, iRegI src1, immIAddSub src2) %{
@@ -6732,7 +7088,7 @@
 
   ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_imm);
 %}
 
 instruct addI_reg_imm_i2l(iRegINoSp dst, iRegL src1, immIAddSub src2) %{
@@ -6746,7 +7102,7 @@
 
   ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_imm);
 %}
 
 // Pointer Addition
@@ -6762,7 +7118,7 @@
            as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct addP_reg_reg_ext(iRegPNoSp dst, iRegP src1, iRegIorL2I src2) %{
@@ -6777,7 +7133,7 @@
            as_Register($src2$$reg), ext::sxtw);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct addP_reg_reg_lsl(iRegPNoSp dst, iRegP src1, iRegL src2, immIScale scale) %{
@@ -6792,7 +7148,7 @@
 		   Address::lsl($scale$$constant)));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct addP_reg_reg_ext_shift(iRegPNoSp dst, iRegP src1, iRegIorL2I src2, immIScale scale) %{
@@ -6807,7 +7163,7 @@
 		   Address::sxtw($scale$$constant)));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct lshift_ext(iRegLNoSp dst, iRegIorL2I src, immI scale, rFlagsReg cr) %{
@@ -6822,7 +7178,7 @@
           $scale$$constant & 63, MIN(32, (-$scale$$constant) & 63));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // Pointer Immediate Addition
@@ -6839,7 +7195,7 @@
 
   ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_imm);
 %}
 
 // Long Addition
@@ -6856,7 +7212,7 @@
            as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 // No constant pool entries requiredLong Immediate Addition.
@@ -6871,7 +7227,7 @@
 
   ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_imm);
 %}
 
 // Integer Subtraction
@@ -6887,7 +7243,7 @@
             as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 // Immediate Subtraction
@@ -6902,7 +7258,7 @@
 
   ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_imm);
 %}
 
 // Long Subtraction
@@ -6919,7 +7275,7 @@
            as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 // No constant pool entries requiredLong Immediate Subtraction.
@@ -6934,7 +7290,7 @@
 
   ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_imm);
 %}
 
 // Integer Negation (special case for sub)
@@ -6950,7 +7306,7 @@
              as_Register($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 // Long Negation
@@ -6966,7 +7322,7 @@
 	   as_Register($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 // Integer Multiply
@@ -6983,7 +7339,7 @@
             as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(imul_reg_reg);
 %}
 
 instruct smulI(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
@@ -6998,7 +7354,7 @@
 	     as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(imul_reg_reg);
 %}
 
 // Long Multiply
@@ -7015,7 +7371,7 @@
            as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(lmul_reg_reg);
 %}
 
 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2, rFlagsReg cr)
@@ -7031,7 +7387,7 @@
 	     as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(lmul_reg_reg);
 %}
 
 // Combined Integer Multiply & Add/Sub
@@ -7049,7 +7405,7 @@
              as_Register($src3$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(imac_reg_reg);
 %}
 
 instruct msubI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
@@ -7065,7 +7421,7 @@
              as_Register($src3$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(imac_reg_reg);
 %}
 
 // Combined Long Multiply & Add/Sub
@@ -7083,7 +7439,7 @@
             as_Register($src3$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(lmac_reg_reg);
 %}
 
 instruct msubL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
@@ -7099,7 +7455,7 @@
             as_Register($src3$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(lmac_reg_reg);
 %}
 
 // Integer Divide
@@ -7111,7 +7467,7 @@
   format %{ "sdivw  $dst, $src1, $src2" %}
 
   ins_encode(aarch64_enc_divw(dst, src1, src2));
-  ins_pipe(pipe_class_default);
+  ins_pipe(idiv_reg_reg);
 %}
 
 instruct signExtract(iRegINoSp dst, iRegI src, immI_31 div1, immI_31 div2) %{
@@ -7121,7 +7477,7 @@
   ins_encode %{
     __ lsrw(as_Register($dst$$reg), as_Register($src$$reg), 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 instruct div2Round(iRegINoSp dst, iRegI src, immI_31 div1, immI_31 div2) %{
@@ -7135,7 +7491,7 @@
 	      as_Register($src$$reg),
 	      Assembler::LSR, 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 // Long Divide
@@ -7147,7 +7503,7 @@
   format %{ "sdiv   $dst, $src1, $src2" %}
 
   ins_encode(aarch64_enc_div(dst, src1, src2));
-  ins_pipe(pipe_class_default);
+  ins_pipe(ldiv_reg_reg);
 %}
 
 instruct signExtractL(iRegLNoSp dst, iRegL src, immL_63 div1, immL_63 div2) %{
@@ -7157,7 +7513,7 @@
   ins_encode %{
     __ lsr(as_Register($dst$$reg), as_Register($src$$reg), 63);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 instruct div2RoundL(iRegLNoSp dst, iRegL src, immL_63 div1, immL_63 div2) %{
@@ -7171,7 +7527,7 @@
 	      as_Register($src$$reg),
 	      Assembler::LSR, 63);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 // Integer Remainder
@@ -7184,7 +7540,7 @@
             "msubw($dst, rscratch1, $src2, $src1" %}
 
   ins_encode(aarch64_enc_modw(dst, src1, src2));
-  ins_pipe(pipe_class_default);
+  ins_pipe(idiv_reg_reg);
 %}
 
 // Long Remainder
@@ -7197,7 +7553,7 @@
             "msub($dst, rscratch1, $src2, $src1" %}
 
   ins_encode(aarch64_enc_mod(dst, src1, src2));
-  ins_pipe(pipe_class_default);
+  ins_pipe(ldiv_reg_reg);
 %}
 
 // Integer Shifts
@@ -7215,7 +7571,7 @@
              as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_vshift);
 %}
 
 // Shift Left Immediate
@@ -7231,7 +7587,7 @@
             $src2$$constant & 0x1f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // Shift Right Logical Register
@@ -7263,7 +7619,7 @@
             $src2$$constant & 0x1f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // Shift Right Arithmetic Register
@@ -7279,7 +7635,7 @@
              as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_vshift);
 %}
 
 // Shift Right Arithmetic Immediate
@@ -7295,7 +7651,7 @@
             $src2$$constant & 0x1f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // Combined Int Mask and Right Shift (using UBFM)
@@ -7316,7 +7672,7 @@
             as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_vshift);
 %}
 
 // Shift Left Immediate
@@ -7332,7 +7688,7 @@
             $src2$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // Shift Right Logical Register
@@ -7348,7 +7704,7 @@
             as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_vshift);
 %}
 
 // Shift Right Logical Immediate
@@ -7364,7 +7720,23 @@
            $src2$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
+%}
+
+// A special-case pattern for card table stores.
+instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
+  match(Set dst (URShiftL (CastP2X src1) src2));
+
+  ins_cost(INSN_COST);
+  format %{ "lsr $dst, p2x($src1), ($src2 & 0x3f)" %}
+
+  ins_encode %{
+    __ lsr(as_Register($dst$$reg),
+           as_Register($src1$$reg),
+           $src2$$constant & 0x3f);
+  %}
+
+  ins_pipe(ialu_reg_shift);
 %}
 
 // Shift Right Arithmetic Register
@@ -7380,7 +7752,7 @@
             as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_vshift);
 %}
 
 // Shift Right Arithmetic Immediate
@@ -7396,7 +7768,7 @@
            $src2$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // BEGIN This section of the file is automatically generated. Do not edit --------------
@@ -7415,7 +7787,7 @@
               Assembler::LSL, 0);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 instruct regI_not_reg(iRegINoSp dst,
                          iRegI src1, immI_M1 m1,
@@ -7431,7 +7803,7 @@
               Assembler::LSL, 0);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 instruct AndI_reg_not_reg(iRegINoSp dst,
@@ -7448,7 +7820,7 @@
               Assembler::LSL, 0);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct AndL_reg_not_reg(iRegLNoSp dst,
@@ -7465,7 +7837,7 @@
               Assembler::LSL, 0);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct OrI_reg_not_reg(iRegINoSp dst,
@@ -7482,7 +7854,7 @@
               Assembler::LSL, 0);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct OrL_reg_not_reg(iRegLNoSp dst,
@@ -7499,7 +7871,7 @@
               Assembler::LSL, 0);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct XorI_reg_not_reg(iRegINoSp dst,
@@ -7516,7 +7888,7 @@
               Assembler::LSL, 0);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct XorL_reg_not_reg(iRegLNoSp dst,
@@ -7533,7 +7905,7 @@
               Assembler::LSL, 0);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct AndI_reg_URShift_not_reg(iRegINoSp dst,
@@ -7551,7 +7923,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AndL_reg_URShift_not_reg(iRegLNoSp dst,
@@ -7569,7 +7941,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AndI_reg_RShift_not_reg(iRegINoSp dst,
@@ -7587,7 +7959,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AndL_reg_RShift_not_reg(iRegLNoSp dst,
@@ -7605,7 +7977,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AndI_reg_LShift_not_reg(iRegINoSp dst,
@@ -7623,7 +7995,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AndL_reg_LShift_not_reg(iRegLNoSp dst,
@@ -7641,7 +8013,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct XorI_reg_URShift_not_reg(iRegINoSp dst,
@@ -7659,7 +8031,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct XorL_reg_URShift_not_reg(iRegLNoSp dst,
@@ -7677,7 +8049,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct XorI_reg_RShift_not_reg(iRegINoSp dst,
@@ -7695,7 +8067,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct XorL_reg_RShift_not_reg(iRegLNoSp dst,
@@ -7713,7 +8085,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct XorI_reg_LShift_not_reg(iRegINoSp dst,
@@ -7731,7 +8103,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct XorL_reg_LShift_not_reg(iRegLNoSp dst,
@@ -7749,7 +8121,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct OrI_reg_URShift_not_reg(iRegINoSp dst,
@@ -7767,7 +8139,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct OrL_reg_URShift_not_reg(iRegLNoSp dst,
@@ -7785,7 +8157,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct OrI_reg_RShift_not_reg(iRegINoSp dst,
@@ -7803,7 +8175,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct OrL_reg_RShift_not_reg(iRegLNoSp dst,
@@ -7821,7 +8193,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct OrI_reg_LShift_not_reg(iRegINoSp dst,
@@ -7839,7 +8211,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct OrL_reg_LShift_not_reg(iRegLNoSp dst,
@@ -7857,7 +8229,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AndI_reg_URShift_reg(iRegINoSp dst,
@@ -7876,7 +8248,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AndL_reg_URShift_reg(iRegLNoSp dst,
@@ -7895,7 +8267,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AndI_reg_RShift_reg(iRegINoSp dst,
@@ -7914,7 +8286,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AndL_reg_RShift_reg(iRegLNoSp dst,
@@ -7933,7 +8305,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AndI_reg_LShift_reg(iRegINoSp dst,
@@ -7952,7 +8324,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AndL_reg_LShift_reg(iRegLNoSp dst,
@@ -7971,7 +8343,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct XorI_reg_URShift_reg(iRegINoSp dst,
@@ -7990,7 +8362,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct XorL_reg_URShift_reg(iRegLNoSp dst,
@@ -8009,7 +8381,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct XorI_reg_RShift_reg(iRegINoSp dst,
@@ -8028,7 +8400,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct XorL_reg_RShift_reg(iRegLNoSp dst,
@@ -8047,7 +8419,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct XorI_reg_LShift_reg(iRegINoSp dst,
@@ -8066,7 +8438,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct XorL_reg_LShift_reg(iRegLNoSp dst,
@@ -8085,7 +8457,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct OrI_reg_URShift_reg(iRegINoSp dst,
@@ -8104,7 +8476,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct OrL_reg_URShift_reg(iRegLNoSp dst,
@@ -8123,7 +8495,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct OrI_reg_RShift_reg(iRegINoSp dst,
@@ -8142,7 +8514,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct OrL_reg_RShift_reg(iRegLNoSp dst,
@@ -8161,7 +8533,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct OrI_reg_LShift_reg(iRegINoSp dst,
@@ -8180,7 +8552,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct OrL_reg_LShift_reg(iRegLNoSp dst,
@@ -8199,7 +8571,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AddI_reg_URShift_reg(iRegINoSp dst,
@@ -8218,7 +8590,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AddL_reg_URShift_reg(iRegLNoSp dst,
@@ -8237,7 +8609,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AddI_reg_RShift_reg(iRegINoSp dst,
@@ -8256,7 +8628,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AddL_reg_RShift_reg(iRegLNoSp dst,
@@ -8275,7 +8647,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AddI_reg_LShift_reg(iRegINoSp dst,
@@ -8294,7 +8666,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct AddL_reg_LShift_reg(iRegLNoSp dst,
@@ -8313,7 +8685,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct SubI_reg_URShift_reg(iRegINoSp dst,
@@ -8332,7 +8704,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct SubL_reg_URShift_reg(iRegLNoSp dst,
@@ -8351,7 +8723,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct SubI_reg_RShift_reg(iRegINoSp dst,
@@ -8370,7 +8742,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct SubL_reg_RShift_reg(iRegLNoSp dst,
@@ -8389,7 +8761,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct SubI_reg_LShift_reg(iRegINoSp dst,
@@ -8408,7 +8780,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 instruct SubL_reg_LShift_reg(iRegLNoSp dst,
@@ -8427,7 +8799,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}
 
 
@@ -8452,7 +8824,7 @@
 	    r, s);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // Shift Left followed by Shift Right.
@@ -8475,7 +8847,7 @@
 	    r, s);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // Shift Left followed by Shift Right.
@@ -8498,7 +8870,7 @@
 	    r, s);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // Shift Left followed by Shift Right.
@@ -8521,7 +8893,7 @@
 	    r, s);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 // Bitfield extract with shift & mask
 
@@ -8538,7 +8910,7 @@
     __ ubfxw(as_Register($dst$$reg),
 	    as_Register($src$$reg), rshift, width);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 instruct ubfxL(iRegLNoSp dst, iRegL src, immI rshift, immL_bitmask mask)
 %{
@@ -8553,7 +8925,7 @@
     __ ubfx(as_Register($dst$$reg),
 	    as_Register($src$$reg), rshift, width);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // We can use ubfx when extending an And with a mask when we know mask
@@ -8571,7 +8943,7 @@
     __ ubfx(as_Register($dst$$reg),
 	    as_Register($src$$reg), rshift, width);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // Rotations
@@ -8588,7 +8960,7 @@
     __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
             $rshift$$constant & 63);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_extr);
 %}
 
 instruct extrOrI(iRegINoSp dst, iRegI src1, iRegI src2, immI lshift, immI rshift, rFlagsReg cr)
@@ -8603,7 +8975,7 @@
     __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
             $rshift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_extr);
 %}
 
 instruct extrAddL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
@@ -8618,7 +8990,7 @@
     __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
             $rshift$$constant & 63);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_extr);
 %}
 
 instruct extrAddI(iRegINoSp dst, iRegI src1, iRegI src2, immI lshift, immI rshift, rFlagsReg cr)
@@ -8633,7 +9005,7 @@
     __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
             $rshift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_extr);
 %}
 
 
@@ -8650,7 +9022,7 @@
     __ rorv(as_Register($dst$$reg), as_Register($src$$reg),
 	    rscratch1);
     %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_vshift);
 %}
 
 // rol expander
@@ -8666,7 +9038,7 @@
     __ rorvw(as_Register($dst$$reg), as_Register($src$$reg),
 	    rscratch1);
     %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_vshift);
 %}
 
 instruct rolL_rReg_Var_C_64(iRegL dst, iRegL src, iRegI shift, immI_64 c_64, rFlagsReg cr)
@@ -8717,7 +9089,7 @@
     __ rorv(as_Register($dst$$reg), as_Register($src$$reg),
 	    as_Register($shift$$reg));
     %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_vshift);
 %}
 
 // ror expander
@@ -8732,7 +9104,7 @@
     __ rorvw(as_Register($dst$$reg), as_Register($src$$reg),
 	    as_Register($shift$$reg));
     %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_vshift);
 %}
 
 instruct rorL_rReg_Var_C_64(iRegL dst, iRegL src, iRegI shift, immI_64 c_64, rFlagsReg cr)
@@ -8783,7 +9155,7 @@
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::sxtw);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %};
 
 instruct SubExtI(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, rFlagsReg cr)
@@ -8796,7 +9168,7 @@
      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::sxtw);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %};
 
 
@@ -8810,7 +9182,7 @@
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::sxth);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct AddExtI_sxtb(iRegINoSp dst, iRegI src1, iRegI src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
@@ -8823,7 +9195,7 @@
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::sxtb);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct AddExtI_uxtb(iRegINoSp dst, iRegI src1, iRegI src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
@@ -8836,7 +9208,7 @@
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::uxtb);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct AddExtL_sxth(iRegLNoSp dst, iRegL src1, iRegL src2, immI_48 lshift, immI_48 rshift, rFlagsReg cr)
@@ -8849,7 +9221,7 @@
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::sxth);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct AddExtL_sxtw(iRegLNoSp dst, iRegL src1, iRegL src2, immI_32 lshift, immI_32 rshift, rFlagsReg cr)
@@ -8862,7 +9234,7 @@
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::sxtw);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct AddExtL_sxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr)
@@ -8875,7 +9247,7 @@
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::sxtb);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct AddExtL_uxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr)
@@ -8888,7 +9260,7 @@
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::uxtb);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 
@@ -8902,7 +9274,7 @@
      __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::uxtb);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct AddExtI_uxth_and(iRegINoSp dst, iRegI src1, iRegI src2, immI_65535 mask, rFlagsReg cr)
@@ -8915,7 +9287,7 @@
      __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::uxth);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct AddExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr)
@@ -8928,7 +9300,7 @@
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::uxtb);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct AddExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr)
@@ -8941,7 +9313,7 @@
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::uxth);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct AddExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr)
@@ -8954,7 +9326,7 @@
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::uxtw);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct SubExtI_uxtb_and(iRegINoSp dst, iRegI src1, iRegI src2, immI_255 mask, rFlagsReg cr)
@@ -8967,7 +9339,7 @@
      __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::uxtb);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct SubExtI_uxth_and(iRegINoSp dst, iRegI src1, iRegI src2, immI_65535 mask, rFlagsReg cr)
@@ -8980,7 +9352,7 @@
      __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::uxth);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct SubExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr)
@@ -8993,7 +9365,7 @@
      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::uxtb);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct SubExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr)
@@ -9006,7 +9378,7 @@
      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::uxth);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct SubExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr)
@@ -9019,7 +9391,7 @@
      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::uxtw);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 // END This section of the file is automatically generated. Do not edit --------------
@@ -9381,7 +9753,7 @@
 	    as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct andI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immILog src2, rFlagsReg cr) %{
@@ -9396,7 +9768,7 @@
 	    (unsigned long)($src2$$constant));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_imm);
 %}
 
 // Or Instructions
@@ -9413,7 +9785,7 @@
             as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct orI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immILog src2) %{
@@ -9428,7 +9800,7 @@
             (unsigned long)($src2$$constant));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_imm);
 %}
 
 // Xor Instructions
@@ -9445,7 +9817,7 @@
             as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct xorI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immILog src2) %{
@@ -9460,7 +9832,7 @@
             (unsigned long)($src2$$constant));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_imm);
 %}
 
 // Long Logical Instructions
@@ -9478,7 +9850,7 @@
 	    as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLLog src2, rFlagsReg cr) %{
@@ -9493,7 +9865,7 @@
             (unsigned long)($src2$$constant));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_imm);
 %}
 
 // Or Instructions
@@ -9510,7 +9882,7 @@
            as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLLog src2) %{
@@ -9525,7 +9897,7 @@
            (unsigned long)($src2$$constant));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_imm);
 %}
 
 // Xor Instructions
@@ -9542,7 +9914,7 @@
            as_Register($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLLog src2) %{
@@ -9557,7 +9929,7 @@
            (unsigned long)($src2$$constant));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_imm);
 %}
 
 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
@@ -9569,7 +9941,7 @@
   ins_encode %{
     __ sbfm($dst$$Register, $src$$Register, 0, 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // this pattern occurs in bigmath arithmetic
@@ -9583,7 +9955,7 @@
     __ ubfm($dst$$Register, $src$$Register, 0, 31);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
@@ -9596,7 +9968,7 @@
     __ movw(as_Register($dst$$reg), as_Register($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 instruct convI2B(iRegINoSp dst, iRegI src, rFlagsReg cr)
@@ -9614,7 +9986,7 @@
     __ cset(as_Register($dst$$reg), Assembler::NE);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 instruct convP2B(iRegINoSp dst, iRegP src, rFlagsReg cr)
@@ -9632,7 +10004,7 @@
     __ cset(as_Register($dst$$reg), Assembler::NE);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}
 
 instruct convD2F_reg(vRegF dst, vRegD src) %{
@@ -9781,7 +10153,7 @@
     __ ldrw($dst$$Register, Address(sp, $src$$disp));
   %}
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_reg);
 
 %}
 
@@ -9817,7 +10189,7 @@
     __ ldr($dst$$Register, Address(sp, $src$$disp));
   %}
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(iload_reg_reg);
 
 %}
 
@@ -9871,7 +10243,7 @@
     __ strw($src$$Register, Address(sp, $dst$$disp));
   %}
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(istore_reg_reg);
 
 %}
 
@@ -9907,7 +10279,7 @@
     __ str($src$$Register, Address(sp, $dst$$disp));
   %}
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(istore_reg_reg);
 
 %}
 
@@ -10013,7 +10385,7 @@
 
   ins_encode(aarch64_enc_cmpw(op1, op2));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_reg);
 %}
 
 instruct compI_reg_immI0(rFlagsReg cr, iRegI op1, immI0 zero)
@@ -10027,7 +10399,7 @@
 
   ins_encode(aarch64_enc_cmpw_imm_addsub(op1, zero));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_imm);
 %}
 
 instruct compI_reg_immIAddSub(rFlagsReg cr, iRegI op1, immIAddSub op2)
@@ -10041,7 +10413,7 @@
 
   ins_encode(aarch64_enc_cmpw_imm_addsub(op1, op2));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_imm);
 %}
 
 instruct compI_reg_immI(rFlagsReg cr, iRegI op1, immI op2)
@@ -10055,7 +10427,7 @@
 
   ins_encode(aarch64_enc_cmpw_imm(op1, op2));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_imm);
 %}
 
 // Unsigned compare Instructions; really, same as signed compare
@@ -10073,7 +10445,7 @@
 
   ins_encode(aarch64_enc_cmpw(op1, op2));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_reg);
 %}
 
 instruct compU_reg_immI0(rFlagsRegU cr, iRegI op1, immI0 zero)
@@ -10087,7 +10459,7 @@
 
   ins_encode(aarch64_enc_cmpw_imm_addsub(op1, zero));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_imm);
 %}
 
 instruct compU_reg_immIAddSub(rFlagsRegU cr, iRegI op1, immIAddSub op2)
@@ -10101,7 +10473,7 @@
 
   ins_encode(aarch64_enc_cmpw_imm_addsub(op1, op2));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_imm);
 %}
 
 instruct compU_reg_immI(rFlagsRegU cr, iRegI op1, immI op2)
@@ -10129,7 +10501,7 @@
 
   ins_encode(aarch64_enc_cmp(op1, op2));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_reg);
 %}
 
 instruct compL_reg_immI0(rFlagsReg cr, iRegL op1, immI0 zero)
@@ -10143,7 +10515,7 @@
 
   ins_encode(aarch64_enc_cmp_imm_addsub(op1, zero));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_imm);
 %}
 
 instruct compL_reg_immLAddSub(rFlagsReg cr, iRegL op1, immLAddSub op2)
@@ -10157,7 +10529,7 @@
 
   ins_encode(aarch64_enc_cmp_imm_addsub(op1, op2));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_imm);
 %}
 
 instruct compL_reg_immL(rFlagsReg cr, iRegL op1, immL op2)
@@ -10171,7 +10543,7 @@
 
   ins_encode(aarch64_enc_cmp_imm(op1, op2));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_imm);
 %}
 
 instruct compP_reg_reg(rFlagsRegU cr, iRegP op1, iRegP op2)
@@ -10185,7 +10557,7 @@
 
   ins_encode(aarch64_enc_cmpp(op1, op2));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_reg);
 %}
 
 instruct compN_reg_reg(rFlagsRegU cr, iRegN op1, iRegN op2)
@@ -10199,7 +10571,7 @@
 
   ins_encode(aarch64_enc_cmpn(op1, op2));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_reg);
 %}
 
 instruct testP_reg(rFlagsRegU cr, iRegP op1, immP0 zero)
@@ -10213,7 +10585,7 @@
 
   ins_encode(aarch64_enc_testp(op1));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_imm);
 %}
 
 instruct testN_reg(rFlagsRegU cr, iRegN op1, immN0 zero)
@@ -10227,7 +10599,7 @@
 
   ins_encode(aarch64_enc_testn(op1));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(icmp_reg_imm);
 %}
 
 // FP comparisons
@@ -10399,6 +10771,29 @@
 
 %}
 
+// Manifest a CmpL result in an integer register.
+// (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
+instruct cmpL3_reg_reg(iRegINoSp dst, iRegL src1, iRegL src2, rFlagsReg flags)
+%{
+  match(Set dst (CmpL3 src1 src2));
+  effect(KILL flags);
+
+  ins_cost(INSN_COST * 6);
+  format %{
+      "cmp $src1, $src2"
+      "csetw $dst, ne"
+      "cnegw $dst, lt"
+  %}
+  // format %{ "CmpL3 $dst, $src1, $src2" %}
+  ins_encode %{
+    __ cmp($src1$$Register, $src2$$Register);
+    __ csetw($dst$$Register, Assembler::NE);
+    __ cnegw($dst$$Register, $dst$$Register, Assembler::LT);
+  %}
+
+  ins_pipe(ialu_reg_reg);
+%}
+
 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q, rFlagsReg cr)
 %{
   match(Set dst (CmpLTMask p q));
@@ -10417,7 +10812,7 @@
     __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegI src, immI0 zero, rFlagsReg cr)
@@ -10433,7 +10828,7 @@
     __ asrw(as_Register($dst$$reg), as_Register($src$$reg), 31);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // ============================================================================
@@ -10461,7 +10856,7 @@
              Assembler::LT);
   %}
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(ialu_reg_reg);
 %}
 
 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
@@ -10486,7 +10881,7 @@
              Assembler::GT);
   %}
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(ialu_reg_reg);
 %}
 
 // ============================================================================
@@ -10504,7 +10899,7 @@
 
   ins_encode(aarch64_enc_b(lbl));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(pipe_branch);
 %}
 
 // Conditional Near Branch
@@ -10525,7 +10920,7 @@
 
   ins_encode(aarch64_enc_br_con(cmp, lbl));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(pipe_branch_cond);
 %}
 
 // Conditional Near Branch Unsigned
@@ -10546,7 +10941,7 @@
 
   ins_encode(aarch64_enc_br_conU(cmp, lbl));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(pipe_branch_cond);
 %}
 
 // Make use of CBZ and CBNZ.  These instructions, as well as being
@@ -10569,7 +10964,7 @@
     else
       __ cbnzw($op1$$Register, *L);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(pipe_cmp_branch);
 %}
 
 instruct cmpL_imm0_branch(cmpOp cmp, iRegL op1, immL0 op2, label labl, rFlagsReg cr) %{
@@ -10588,7 +10983,7 @@
     else
       __ cbnz($op1$$Register, *L);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(pipe_cmp_branch);
 %}
 
 instruct cmpP_imm0_branch(cmpOp cmp, iRegP op1, immP0 op2, label labl, rFlagsReg cr) %{
@@ -10607,7 +11002,7 @@
     else
       __ cbnz($op1$$Register, *L);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(pipe_cmp_branch);
 %}
 
 // Conditional Far Branch
@@ -10628,7 +11023,7 @@
 
   ins_encode(aarch64_enc_br_con(cmp, lbl));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(pipe_branch);
 %}
 
 // counted loop end branch near Unsigned
@@ -10645,7 +11040,7 @@
 
   ins_encode(aarch64_enc_br_conU(cmp, lbl));
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(pipe_branch);
 %}
 
 // counted loop end branch far
@@ -10667,7 +11062,7 @@
 
   ins_encode(aarch64_enc_fast_lock(object, box, tmp, tmp2));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(pipe_serial);
 %}
 
 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2)
@@ -10680,7 +11075,7 @@
 
   ins_encode(aarch64_enc_fast_unlock(object, box, tmp, tmp2));
 
-  ins_pipe(pipe_class_compare);
+  ins_pipe(pipe_serial);
 %}
 
 
@@ -10700,7 +11095,7 @@
   ins_encode %{
     __ read_polling_page(as_Register($poll$$reg), relocInfo::poll_type);
   %}
-  ins_pipe(pipe_class_memory);
+  ins_pipe(pipe_serial);
 %}
 
 
@@ -10860,7 +11255,7 @@
 
   ins_encode( /*empty*/ );
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(pipe_class_empty);
 %}
 
 // Rethrow exception: The exception oop will come in the first
@@ -10887,7 +11282,7 @@
 
   ins_encode( aarch64_enc_ret() );
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(pipe_branch);
 %}
 
 // Die now.
--- a/src/cpu/aarch64/vm/aarch64_ad.m4	Tue Nov 25 11:10:14 2014 +0000
+++ b/src/cpu/aarch64/vm/aarch64_ad.m4	Tue Nov 25 17:36:55 2014 +0000
@@ -18,7 +18,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}')dnl
 define(`BASE_INVERTED_INSN',
 `
@@ -40,7 +40,7 @@
               Assembler::LSL, 0);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}')dnl
 define(`INVERTED_SHIFT_INSN',
 `
@@ -63,7 +63,7 @@
               $src3$$constant & 0x3f);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_shift);
 %}')dnl
 define(`NOT_INSN',
 `instruct reg$1_not_reg(iReg$1NoSp dst,
@@ -80,7 +80,7 @@
               Assembler::LSL, 0);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg);
 %}')dnl
 dnl
 define(`BOTH_SHIFT_INSNS',
@@ -142,7 +142,7 @@
 	    r, s);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}')
 BFM_INSN(L, 63, RShift, sbfm)
 BFM_INSN(I, 31, RShift, sbfmw)
@@ -164,7 +164,7 @@
     __ $3(as_Register($dst$$reg),
 	    as_Register($src$$reg), rshift, width);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}')
 BFX_INSN(I,URShift,ubfxw)
 BFX_INSN(L,URShift,ubfx)
@@ -184,7 +184,7 @@
     __ ubfx(as_Register($dst$$reg),
 	    as_Register($src$$reg), rshift, width);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_shift);
 %}
 
 // Rotations
@@ -202,7 +202,7 @@
     __ $4(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
             $rshift$$constant & $2);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_extr);
 %}
 ')dnl
 EXTRACT_INSN(L, 63, Or, extr)
@@ -223,7 +223,7 @@
     __ $3(as_Register($dst$$reg), as_Register($src$$reg),
 	    rscratch1);
     %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_vshift);
 %}')dnl
 define(`ROR_EXPAND', `
 // $2 expander
@@ -238,7 +238,7 @@
     __ $3(as_Register($dst$$reg), as_Register($src$$reg),
 	    as_Register($shift$$reg));
     %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg_vshift);
 %}')dnl
 define(ROL_INSN, `
 instruct $3$1_rReg_Var_C$2(iRegL dst, iRegL src, iRegI shift, immI$2 c$2, rFlagsReg cr)
@@ -284,7 +284,7 @@
      __ $4(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::$5);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}')dnl
 ADD_SUB_CONV(I,L,Add,add,sxtw);
 ADD_SUB_CONV(I,L,Sub,sub,sxtw);
@@ -300,7 +300,7 @@
      __ $5(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::$6);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}')
 ADD_SUB_EXTENDED(I,16,Add,RShift,add,sxth,32)
 ADD_SUB_EXTENDED(I,8,Add,RShift,add,sxtb,32)
@@ -322,7 +322,7 @@
      __ $4(as_Register($dst$$reg), as_Register($src1$$reg),
             as_Register($src2$$reg), ext::$5);
    %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(ialu_reg_reg);
 %}')
 dnl
 ADD_SUB_ZERO_EXTEND(I,255,Add,addw,uxtb)
--- a/src/cpu/aarch64/vm/vm_version_aarch64.cpp	Tue Nov 25 11:10:14 2014 +0000
+++ b/src/cpu/aarch64/vm/vm_version_aarch64.cpp	Tue Nov 25 17:36:55 2014 +0000
@@ -147,6 +147,11 @@
   if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
     UseCRC32Intrinsics = true;
   }
+#ifdef COMPILER2
+  if (FLAG_IS_DEFAULT(OptoScheduling)) {
+    OptoScheduling = true;
+  }
+#endif
 }
 
 void VM_Version::initialize() {