--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Tue Nov 04 04:04:35 2014 -0500
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Wed Nov 05 08:54:45 2014 -0500
@@ -65,7 +65,8 @@
 
 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
 
-void MacroAssembler::pd_patch_instruction(address branch, address target) {
+int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
+  int size = 1;
   assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant");
   long offset = (target - branch) >> 2;
   unsigned insn = *(unsigned*)branch;
@@ -119,12 +120,14 @@
 	Instruction_aarch64::patch(branch + sizeof (unsigned),
 				    21, 10, offset_lo >> size);
 	guarantee(((dest >> size) << size) == dest, "misaligned target");
+	size = 2;
       } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
 		Instruction_aarch64::extract(insn, 4, 0) ==
 			Instruction_aarch64::extract(insn2, 4, 0)) {
 	// add (immediate)
 	Instruction_aarch64::patch(branch + sizeof (unsigned),
 				   21, 10, offset_lo);
+	size = 2;
       } else {
 	assert((jbyte *)target ==
 		((CardTableModRefBS*)(Universe::heap()->barrier_set()))->byte_map_base ||
@@ -147,6 +150,7 @@
     Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff);
     Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff);
     assert(pd_call_destination(branch) == target, "should be");
+    size = 3;
   } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
              Instruction_aarch64::extract(insn, 4, 0) == 0b11111) {
     // nothing to do
@@ -154,6 +158,7 @@
   } else {
     ShouldNotReachHere();
   }
+  return size;
 }
 
 void MacroAssembler::patch_oop(address insn_addr, address o) {

--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Tue Nov 04 04:04:35 2014 -0500
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Wed Nov 05 08:54:45 2014 -0500
@@ -497,7 +497,10 @@
 
   // Required platform-specific helpers for Label::patch_instructions.
   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
-  static void pd_patch_instruction(address branch, address target);
+  static int pd_patch_instruction_size(address branch, address target);
+  static void pd_patch_instruction(address branch, address target) {
+    pd_patch_instruction_size(branch, target);
+  }
   static address pd_call_destination(address branch) {
     unsigned insn = *(unsigned*)branch;
     return target_addr_for_insn(branch, insn);

--- a/src/cpu/aarch64/vm/relocInfo_aarch64.cpp	Tue Nov 04 04:04:35 2014 -0500
+++ b/src/cpu/aarch64/vm/relocInfo_aarch64.cpp	Wed Nov 05 08:54:45 2014 -0500
@@ -33,23 +33,30 @@
 
 
 void Relocation::pd_set_data_value(address x, intptr_t o, bool verify_only) {
+  if (verify_only)
+    return;
+
+  int size;
+
   switch(type()) {
   case relocInfo::oop_type:
     {
       oop_Relocation *reloc = (oop_Relocation *)this;
       if (NativeInstruction::is_ldr_literal_at(addr())) {
 	address constptr = (address)code()->oop_addr_at(reloc->oop_index());
-	MacroAssembler::pd_patch_instruction(addr(), constptr);
+	size = MacroAssembler::pd_patch_instruction_size(addr(), constptr);
 	assert(*(address*)constptr == x, "error in oop relocation");
       } else{
 	MacroAssembler::patch_oop(addr(), x);
+	size = NativeMovConstReg::instruction_size;
       }
     }
     break;
   default:
-    MacroAssembler::pd_patch_instruction(addr(), x);
+    int size = MacroAssembler::pd_patch_instruction_size(addr(), x);
     break;
   }
+  ICache::invalidate_range(addr(), size);
 }
 
 address Relocation::pd_call_destination(address orig_addr) {