Mercurial > hg > release > icedtea6-1.6
changeset 1660:234dd693b3ec
2009-08-18 Edward Nevill <ed@camswl.com>
Added ARM assembler interpreter
* openjdk/hotspot/src/share/vm/interpreter.hpp
Allow ARM interpreter to notice safepoints
Changed via patches/icedtea-notice-safepoints.patch
* ports/hotspot/build/linux/makefiles/zero.make
Add cppInterpreter_arm
Add CFLAGS for ARM asm interpreter
Add rules to build .o from .S
* ports/hotspot/src/cpu/zero/vm/bytecodes_zero.cpp
Add initialisation of new bytecodes for asm interpreter
* ports/hotspot/src/cpu/zero/vm/bytecodes_zero.hpp
Add definitions of new bytecodes for asm interpreter
* ports/hotspot/src/cpu/zero/vm/cppInterpreter_zero.cpp
Add hooks to call asm interpreter
* ports/hotspot/src/os_cpu/linux_zero/vm/os_linux_zero.cpp
Add hooks to allow HW null pointer detection
[ NEW FILES ]
* ports/hotspot/src/cpu/zero/vm/bc.def
Bytecode templates
* ports/hotspot/src/cpu/zero/vm/bytecodes.s
Bytecode implementations (manually generated from bc.def)
* ports/hotspot/src/cpu/zero/vm/cppInterpreter_asm.S
Complex bytecode implementations, entry points and support code
* ports/hotspot/src/cpu/zero/vm/mkbc.c
Bytecode generator, use to generate bytecodes.s from bc.def
| author | doko@ubuntu.com |
|---|---|
| date | Fri, 21 Aug 2009 13:35:04 +0200 |
| parents | bd60280483e5 |
| children | caf6aebb73ca |
| files | ChangeLog Makefile.am mkbc.c patches/icedtea-notice-safepoints.patch ports/hotspot/build/linux/makefiles/zero.make ports/hotspot/src/cpu/zero/vm/bc.def ports/hotspot/src/cpu/zero/vm/bytecodes.s ports/hotspot/src/cpu/zero/vm/bytecodes_zero.cpp ports/hotspot/src/cpu/zero/vm/bytecodes_zero.hpp ports/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S ports/hotspot/src/cpu/zero/vm/cppInterpreter_zero.cpp ports/hotspot/src/os_cpu/linux_zero/vm/os_linux_zero.cpp |
| diffstat | 12 files changed, 27198 insertions(+), 1 deletions(-) [+] |
line wrap: on
line diff
--- a/ChangeLog Thu Aug 13 15:48:51 2009 +0100 +++ b/ChangeLog Fri Aug 21 13:35:04 2009 +0200 @@ -1,3 +1,38 @@ +2009-08-18 Edward Nevill <ed@camswl.com> + + Added ARM assembler interpreter + + * openjdk/hotspot/src/share/vm/interpreter.hpp + Allow ARM interpreter to notice safepoints + Changed via patches/icedtea-notice-safepoints.patch + + * ports/hotspot/build/linux/makefiles/zero.make + Add cppInterpreter_arm + Add CFLAGS for ARM asm interpreter + Add rules to build .o from .S + + * ports/hotspot/src/cpu/zero/vm/bytecodes_zero.cpp + Add initialisation of new bytecodes for asm interpreter + + * ports/hotspot/src/cpu/zero/vm/bytecodes_zero.hpp + Add definitions of new bytecodes for asm interpreter + + * ports/hotspot/src/cpu/zero/vm/cppInterpreter_zero.cpp + Add hooks to call asm interpreter + + * ports/hotspot/src/os_cpu/linux_zero/vm/os_linux_zero.cpp + Add hooks to allow HW null pointer detection + + [ NEW FILES ] + * ports/hotspot/src/cpu/zero/vm/bc.def + Bytecode templates + * ports/hotspot/src/cpu/zero/vm/bytecodes.s + Bytecode implementations (manually generated from bc.def) + * ports/hotspot/src/cpu/zero/vm/cppInterpreter_asm.S + Complex bytecode implementations, entry points and support code + * ports/hotspot/src/cpu/zero/vm/mkbc.c + Bytecode generator, use to generate bytecodes.s from bc.def + 2009-08-07 Matthias Klose <doko@ubuntu.com> * Makefile.am (ADD_ZERO_CONFIGURE_ARGS): Add configure options
--- a/Makefile.am Thu Aug 13 15:48:51 2009 +0100 +++ b/Makefile.am Fri Aug 21 13:35:04 2009 +0200 @@ -503,6 +503,7 @@ ICEDTEA_FSG_PATCHES = ICEDTEA_PATCHES = \ + patches/icedtea-notice-safepoints.patch \ patches/hotspot/$(HSBUILD)/icedtea-bytecodeInterpreter.patch \ patches/icedtea-signature-iterator.patch \ patches/icedtea-test-atomic-operations.patch \
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mkbc.c Fri Aug 21 13:35:04 2009 +0200 @@ -0,0 +1,581 @@ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <ctype.h> + +#define DEFAULT_PREFIX "do_" + +static char *prefix = DEFAULT_PREFIX; + +#define ISALPHA(c) (isalpha(c) || (c) == '_') +#define ISALNUM(c) (isalnum(c) || (c) == '_') + +FILE *source_f, *bci_f, *bci_f; + +typedef struct Bytecode { + char *name; + int len; +} Bytecode; + +typedef struct StringList { + struct StringList *next; + char *line; +} StringList; + +typedef struct OpcodeList { + struct OpcodeList *next; + long opcode; +} OpcodeList; + +typedef struct OpcodeSequence { + struct OpcodeSequence *next; + OpcodeList *opcode_list; +} OpcodeSequence; + +typedef struct BytecodeImpl { + struct BytecodeImpl *next; + OpcodeSequence *opcode_seq; + StringList *macro_impl; + StringList *direct_impl; + int len; + char *name; + char *do_name; +} BytecodeImpl; + +Bytecode bytecodes[256]; + +BytecodeImpl *the_impl = 0; +BytecodeImpl **the_impl_ptr = &the_impl; + +#define BUFLEN 1024 + +static int lineno = 1; + +void fatal(const char *s) +{ + fputs(s, stderr); + fputc('\n', stderr); + exit(1); +} + +void outmem(void) +{ + fprintf(stderr, "Out of memory\n"); + exit(1); +} + +void synerr(void) +{ + fprintf(stderr, "Syntax error at line %d\n", lineno); + exit(1); +} + +int readchar() +{ + int c; + + c = getc(source_f); + if (c == '\n') lineno++; + return c; +} + +int readwhitespace(int c, char *buf, int len) +{ + int i = 0; + + while ((isspace)(c)) { + if (buf && i < len-1) buf[i++] = c; + c = (readchar)(); + } + if (buf && i < len) buf[i] = 0; + return c; +} + +int skipwhitespace(int c) +{ + while ((isspace)(c)) { + c = (readchar)(); + } + return c; +} + +int readeol(int c, char *buf, int len) +{ + int i = 0; + + while (c != '\n' && c != EOF) { + if (buf && i < len-1) buf[i++] = c; + c = (readchar)(); + } + if (buf && i < len) buf[i] = 0; + if (c == '\n') c = (readchar)(); + return c; +} + +int skipeol(int c) +{ + while (c != '\n' && c != EOF) c = (readchar)(); + if (c == '\n') c = (readchar)(); + return c; +} + +int readsymbol(int c, char *buf, int len) +{ + int i = 0; + + while (ISALNUM(c)) { + if (buf && i < len-1) buf[i++] = c; + c = (readchar)(); + } + if (buf && i < len) buf[i] = 0; + return c; +} + +int bcdef(int c, char *buf, int len) +{ + BytecodeImpl *def; + OpcodeSequence *seq; + OpcodeSequence **seqp; + OpcodeList *opc; + OpcodeList **opcp; + StringList *macro, **macrop; + StringList *direct, **directp; + char *name; + char *line; + int i; + int length, overall_len; + + def = malloc(sizeof(BytecodeImpl)); + if (!def) outmem(); + def->next = 0; + def->opcode_seq = 0; + def->macro_impl = 0; + def->direct_impl = 0; + def->len = -1; + *the_impl_ptr = def; + the_impl_ptr = &(def->next); + seqp = &(def->opcode_seq); + overall_len = 0; + do { + seq = malloc(sizeof(OpcodeSequence)); + if (!seq) outmem(); + seq->next = 0; + seq->opcode_list = 0; + *seqp = seq; + seqp = &(seq->next); + opcp = &(seq->opcode_list); + length = -2; + do { + c = (readchar)(); + c = skipwhitespace(c); + if (!ISALPHA(c)) synerr(); + c = readsymbol(c, buf, len); + c = skipwhitespace(c); + opc = malloc(sizeof(OpcodeList)); + if (!opc) outmem(); + opc->next = 0; + opc->opcode = -1; + *opcp = opc; + opcp = &(opc->next); + name = strdup(buf); + if (!name) outmem(); + for (i = 0; i < 256; i++) { + if (strcmp(name, bytecodes[i].name) == 0) { + opc->opcode = i; + break; + } + } + if (i == 256) { + fprintf(stderr, "No such opcode '%s'\n", name); + exit(1); + } + if (length == -2) length = bytecodes[i].len; + } while (c == ','); + overall_len += length; + if (c != ')') synerr(); + c = (readchar)(); + c = skipwhitespace(c); + } while (c == '('); +// strcpy(buf, "do_"); + *buf = 0; + if (ISALPHA(c)) { + c = readsymbol(c, buf, len); + c = skipwhitespace(c); + } else { + seq = def->opcode_seq; +// strcat(buf, "bytecode"); + while (seq) { + opc = seq->opcode_list; + if (*buf) strcat(buf, "_"); + strcat(buf, bytecodes[opc->opcode].name); +// sprintf(buf+strlen(buf), "_%ld", opc->opcode); + seq = seq->next; + } + } + name = strdup(buf); + if (!name) outmem(); + def->name = name; + def->do_name = name; + def->len = overall_len; + if (c != '{') synerr(); + c = (readchar)(); + while (c != '\n' && isspace(c)) c = (readchar)(); + if (c != '\n') synerr(); + c = (readchar)(); + c = readwhitespace(c, buf, len); + macrop = &(def->macro_impl); + while (c != '}' && c != EOF) { + c = readeol(c, buf + strlen(buf), len - strlen(buf)); + line = strdup(buf); + if (!line) outmem(); + macro = malloc(sizeof(StringList)); + if (!macro) outmem(); + *macrop = macro; + macrop = &(macro->next); + macro->next = 0; + macro->line = line; + c = readwhitespace(c, buf, len); + } + if (c != '}') synerr(); + c = (readchar)(); + c = skipwhitespace(c); + if (ISALPHA(c)) { + c = readsymbol(c, buf, len); + c = skipwhitespace(c); + name = strdup(buf); + if (!name) outmem(); + def->do_name = name; + } + if (c == '[') { + c = (readchar)(); + while (c != '\n' && isspace(c)) c = (readchar)(); + if (c != '\n') synerr(); + c = (readchar)(); + c = readwhitespace(c, buf, len); + directp = &(def->direct_impl); + while (c != ']' && c != EOF) { + c = readeol(c, buf + strlen(buf), len - strlen(buf)); + line = strdup(buf); + if (!line) outmem(); + direct = malloc(sizeof(StringList)); + if (!direct) outmem(); + *directp = direct; + directp = &(direct->next); + direct->next = 0; + direct->line = line; + c = readwhitespace(c, buf, len); + } + if (c != ']') synerr(); + c = (readchar)(); + } + return c; +} + +void mkbc(void) +{ + char buf[BUFLEN]; + char *endptr; + int c; + char *name; + long opcode, len; + + c = (readchar)(); + c = skipwhitespace(c); + while (c != EOF) { + if (c == '#') { + c = skipeol(c); + } else if (ISALPHA(c)) { + c = readsymbol(c, buf, BUFLEN); + c = skipwhitespace(c); + if (c == '=') { + name = strdup(buf); + if (!name) outmem(); + c = (readchar)(); + c = skipwhitespace(c); + if (!(isdigit)(c)) synerr(); + c = readsymbol(c, buf, BUFLEN); + opcode = strtol(buf, &endptr, 0); + if (*endptr != 0) synerr(); + c = skipwhitespace(c); + if (c != ',') synerr(); + c = (readchar)(); + c = skipwhitespace(c); + if (!(isdigit)(c)) synerr(); + c = readsymbol(c, buf, BUFLEN); + len = strtol(buf, &endptr, 0); + if (*endptr != 0) synerr(); + bytecodes[opcode].name = name; + bytecodes[opcode].len = len; + } + } else if (c == '(') { + c = bcdef(c, buf, BUFLEN); + } else synerr(); + c = skipwhitespace(c); + } +} + +typedef struct TableEntry { + BytecodeImpl *impl; + char *impl_name; + char *def_name; + struct TableEntry *subtable; +} TableEntry; + +TableEntry *the_table; + +int is_duplicate(TableEntry *a, TableEntry *b) +{ + int i; + char buf[256]; + + for (i = 0; i < 256; i++) { + if (a[i].subtable || b[i].subtable) { + if (!(a[i].subtable) || !(b[i].subtable)) return 0; + if (!is_duplicate(a[i].subtable, b[i].subtable)) return 0; + } else if (a[i].impl_name && b[i].impl_name) { + if (strcmp(a[i].impl_name, b[i].impl_name) != 0) + return 0; + } else if (a[i].def_name && b[i].def_name) { + if (strcmp(a[i].def_name, b[i].def_name) != 0) + return 0; + } else return 0; + } + return 1; +} + +void remove_duplicates(TableEntry *table, int start, int *table_indices, int depth) +{ + TableEntry *start_entry = table[start].subtable; + int i, j; + + if (!start_entry) fatal("Subtable is NULL in remove_duplicates!!!"); + for (i = start+1; i < 256; i++) { + if (table[i].subtable) { + if (is_duplicate(start_entry, table[i].subtable)) { + fputs("dispatch", bci_f); + for (j = 0; j < depth; j++) { + fputc('_', bci_f); + fputs(bytecodes[table_indices[j]].name, bci_f); + } + fputc('_', bci_f); + fputs(bytecodes[i].name, bci_f); + fputs(":\n", bci_f); + free(table[i].subtable); + table[i].subtable = 0; + } + } + } +} + +void writeouttable(TableEntry *table, int *table_indices, int depth) +{ + int i, j; + int len; + + for (i = 0; i < 256; i++) { + if (table[i].subtable) { + len = 0; + fputs("\t.word\tdispatch", bci_f); + table_indices[depth] = i; + for (j = 0; j <= depth; j++) { + fputc('_', bci_f); + fputs(bytecodes[table_indices[j]].name, bci_f); + len += bytecodes[table_indices[j]].len; + } + fprintf(bci_f, "+%d\n", len); + } else { + if (table[i].impl_name) + fprintf(bci_f, "\t.word\t%s%s\n", prefix, table[i].impl_name); + else + fprintf(bci_f, "\t.word\t%s%s\n", prefix, table[i].def_name); + } + } + if (depth == 0) { + fputs("\t.endm\n", bci_f); + fputs("\t.macro\tSUB_DISPATCH_TABLES\n", bci_f); + } + for (i = 0; i < 256; i++) { + if (table[i].subtable) { + fputs("dispatch", bci_f); + table_indices[depth] = i; + for (j = 0; j <= depth; j++) { + fputc('_', bci_f); + fputs(bytecodes[table_indices[j]].name, bci_f); + } + fputs(":\n", bci_f); + remove_duplicates(table, i, table_indices, depth); + writeouttable(table[i].subtable, table_indices, depth+1); + } + } +} + +void do_tableentry(BytecodeImpl *impl, TableEntry **tablep, int *table_indices, int depth) +{ + TableEntry *table; + char *def = "undefined"; + int i,j; + + if (depth == 0) fatal("Depth = 0 for tableentry\n"); + for (i = 0; i < depth; i++) { + table = *tablep; + if (!table) { + table = malloc(sizeof(TableEntry) * 256); + if (!table) outmem(); + *tablep = table; + def = strdup(def); + if (!def) outmem(); + for (j = 0; j < 256; j++) { + table[j].impl_name = 0; + table[j].def_name = def; + table[j].subtable = 0; + } + } + table = &table[table_indices[i]]; + tablep = &(table->subtable); + if (table->impl_name) def = table->def_name; + } + if (!table->impl_name) + table->impl_name = impl->do_name; + table->def_name = impl->do_name; +} + +void dumpseq(BytecodeImpl *impl, OpcodeSequence *seq, int *table_indices, int depth) +{ + OpcodeList *opc; + + opc = seq->opcode_list; + while (opc) { + table_indices[depth++] = opc->opcode; + if (seq->next != NULL) { + dumpseq(impl, seq->next, table_indices, depth); + } else { + do_tableentry(impl, &the_table, table_indices, depth); + } + depth--; + opc = opc->next; + } +} + +void dumptable(void) +{ + BytecodeImpl *impl = the_impl; + int table_indices[256]; + int j; + char buf[256]; + char *def; + + the_table = malloc(sizeof(TableEntry) * 256); + if (!the_table) outmem(); + for (j = 0; j < 256; j++) { + sprintf(buf, "%s", bytecodes[j].name); + def = strdup(buf); + if (!def) outmem(); + the_table[j].impl_name = 0; + the_table[j].def_name = def; + the_table[j].subtable = 0; + } + while (impl) { + dumpseq(impl, impl->opcode_seq, table_indices, 0); + impl = impl->next; + } + fputs("\t.macro\tMAIN_DISPATCH_TABLE\n", bci_f); + writeouttable(the_table, table_indices, 0); + fputs("\t.endm\n", bci_f); +} + +void dumpimpl(void) +{ + BytecodeImpl *impl = the_impl; + OpcodeList *opc; + StringList *code; + StringList *sl; + char buf[BUFLEN]; + char macro[BUFLEN]; + + while (impl) { + buf[0] = 0; + fprintf(bci_f, "@-----------------------------------------------------------------------------\n"); + fprintf(bci_f, "\t.macro\t%s\tjpc_off=0, seq_len=%d\n", impl->name, impl->len); + sl = impl->macro_impl; + while (sl) { + fputs(sl->line, bci_f); + fputc('\n', bci_f); + sl = sl->next; + } + fprintf(bci_f, "\t.endm\n\n"); + sl = impl->direct_impl; + if (sl) { + do { + fputs(sl->line, bci_f); + fputc('\n', bci_f); + sl = sl->next; + } while (sl); + } else { + fprintf(bci_f, "\tOpcode\t%s\n", impl->do_name); +// fprintf(bci_f, "%s:\n", impl->do_name); + fprintf(bci_f, "\t%s\n", impl->name); +// fprintf(bci_f, "\tDISPATCH\t%d\n", impl->len); + } + impl = impl->next; + } +} + +void dumpbc() +{ + int i; + + for (i = 0; i < 256; i++) { + if (strcmp(bytecodes[i].name, "undefined") != 0) + fprintf(bci_f, "#define opc_%s\t\t0x%02x\n", bytecodes[i].name, i); + } + fputc('\n', bci_f); + dumpimpl(); + dumptable(); +} + +void usage(void) +{ + fatal("Usage: mkbc <bytecode definition file> <asm output file>"); +} + +int main(int argc, char **argv) +{ + int i; + char *source, *bci; + char *s; + + source = bci = 0; + while (s = *++argv) { + if (*s == '-') { + if (s[1] == 'P') { + prefix = s+2; + } else { + fprintf(stderr, "Unrecognized option %s\n", s); + usage(); + } + } else { + if (!source) source = s; + else if (!bci) bci = s; + else { + fprintf(stderr, "Too many arguments\n"); + usage(); + } + } + } + if (!bci) { + fprintf(stderr, "Too few arguments\n"); + usage(); + } + source_f = fopen(source, "r"); + if (!source_f) fatal("Error opening source file"); + bci_f = fopen(bci, "w"); + if (!bci_f) fatal("Error opening bci file for write"); + for (i = 0; i < 256; i++) { + bytecodes[i].name = "undefined"; + bytecodes[i].len = -1; + } + mkbc(); + dumpbc(); + if (fclose(source_f)) fatal("Error reading source"); + if (fclose(bci_f)) fatal("Error writing bci"); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/patches/icedtea-notice-safepoints.patch Fri Aug 21 13:35:04 2009 +0200 @@ -0,0 +1,16 @@ +--- openjdk/hotspot/src/share/vm/interpreter/cppInterpreter.hpp 2009-04-30 23:21:47.000000000 +0000 ++++ openjdk/hotspot/src/share/vm/interpreter/cppInterpreter.hpp 2009-06-29 12:30:31.000000000 +0000 +@@ -60,8 +60,13 @@ + + + // No displatch table to switch so no need for these to do anything special ++#if defined(PRODUCT) && defined(HOTSPOT_ASM) ++ static void notice_safepoints(); ++ static void ignore_safepoints(); ++#else + static void notice_safepoints() {} + static void ignore_safepoints() {} ++#endif + + static address native_result_to_tosca() { return (address)_native_abi_to_tosca; } // aka result handler + static address tosca_result_to_stack() { return (address)_tosca_to_stack; }
--- a/ports/hotspot/build/linux/makefiles/zero.make Thu Aug 13 15:48:51 2009 +0100 +++ b/ports/hotspot/build/linux/makefiles/zero.make Fri Aug 21 13:35:04 2009 +0200 @@ -23,6 +23,15 @@ # # +ifeq ($(ZERO_LIBARCH),arm) +Obj_Files += cppInterpreter_arm.o +CFLAGS += -DHOTSPOT_ASM -DHW_NULL_PTR_CHECK +%.o: %.S + @echo Assembling $< + $(QUIETLY) $(REMOVE_TARGET) + $(COMPILE.CC) -o $@ $< $(COMPILE_DONE) +endif + # The copied fdlibm routines in sharedRuntimeTrig.o must not be optimized OPT_CFLAGS/sharedRuntimeTrig.o = $(OPT_CFLAGS/NOOPT) # The copied fdlibm routines in sharedRuntimeTrans.o must not be optimized
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ports/hotspot/src/cpu/zero/vm/bc.def Fri Aug 21 13:35:04 2009 +0200 @@ -0,0 +1,7863 @@ +nop = 0x00, 1 +aconst_null = 0x01, 1 +iconst_m1 = 0x02, 1 +iconst_0 = 0x03, 1 +iconst_1 = 0x04, 1 +iconst_2 = 0x05, 1 +iconst_3 = 0x06, 1 +iconst_4 = 0x07, 1 +iconst_5 = 0x08, 1 +lconst_0 = 0x09, 1 +lconst_1 = 0x0a, 1 +fconst_0 = 0x0b, 1 +fconst_1 = 0x0c, 1 +fconst_2 = 0x0d, 1 +dconst_0 = 0x0e, 1 +dconst_1 = 0x0f, 1 +bipush = 0x10, 2 +sipush = 0x11, 3 +ldc = 0x12, 2 +ldc_w = 0x13, 3 +ldc2_w = 0x14, 3 +iload = 0x15, 2 +lload = 0x16, 2 +fload = 0x17, 2 +dload = 0x18, 2 +aload = 0x19, 2 +iload_0 = 0x1a, 1 +iload_1 = 0x1b, 1 +iload_2 = 0x1c, 1 +iload_3 = 0x1d, 1 +lload_0 = 0x1e, 1 +lload_1 = 0x1f, 1 +lload_2 = 0x20, 1 +lload_3 = 0x21, 1 +fload_0 = 0x22, 1 +fload_1 = 0x23, 1 +fload_2 = 0x24, 1 +fload_3 = 0x25, 1 +dload_0 = 0x26, 1 +dload_1 = 0x27, 1 +dload_2 = 0x28, 1 +dload_3 = 0x29, 1 +aload_0 = 0x2a, 1 +aload_1 = 0x2b, 1 +aload_2 = 0x2c, 1 +aload_3 = 0x2d, 1 +iaload = 0x2e, 1 +laload = 0x2f, 1 +faload = 0x30, 1 +daload = 0x31, 1 +aaload = 0x32, 1 +baload = 0x33, 1 +caload = 0x34, 1 +saload = 0x35, 1 +istore = 0x36, 2 +lstore = 0x37, 2 +fstore = 0x38, 2 +dstore = 0x39, 2 +astore = 0x3a, 2 +istore_0 = 0x3b, 1 +istore_1 = 0x3c, 1 +istore_2 = 0x3d, 1 +istore_3 = 0x3e, 1 +lstore_0 = 0x3f, 1 +lstore_1 = 0x40, 1 +lstore_2 = 0x41, 1 +lstore_3 = 0x42, 1 +fstore_0 = 0x43, 1 +fstore_1 = 0x44, 1 +fstore_2 = 0x45, 1 +fstore_3 = 0x46, 1 +dstore_0 = 0x47, 1 +dstore_1 = 0x48, 1 +dstore_2 = 0x49, 1 +dstore_3 = 0x4a, 1 +astore_0 = 0x4b, 1 +astore_1 = 0x4c, 1 +astore_2 = 0x4d, 1 +astore_3 = 0x4e, 1 +iastore = 0x4f, 1 +lastore = 0x50, 1 +fastore = 0x51, 1 +dastore = 0x52, 1 +aastore = 0x53, 1 +bastore = 0x54, 1 +castore = 0x55, 1 +sastore = 0x56, 1 +pop = 0x57, 1 +pop2 = 0x58, 1 +dup = 0x59, 1 +dup_x1 = 0x5a, 1 +dup_x2 = 0x5b, 1 +dup2 = 0x5c, 1 +dup2_x1 = 0x5d, 1 +dup2_x2 = 0x5e, 1 +swap = 0x5f, 1 +iadd = 0x60, 1 +ladd = 0x61, 1 +fadd = 0x62, 1 +dadd = 0x63, 1 +isub = 0x64, 1 +lsub = 0x65, 1 +fsub = 0x66, 1 +dsub = 0x67, 1 +imul = 0x68, 1 +lmul = 0x69, 1 +fmul = 0x6a, 1 +dmul = 0x6b, 1 +idiv = 0x6c, 1 +ldiv = 0x6d, 1 +fdiv = 0x6e, 1 +ddiv = 0x6f, 1 +irem = 0x70, 1 +lrem = 0x71, 1 +frem = 0x72, 1 +drem = 0x73, 1 +ineg = 0x74, 1 +lneg = 0x75, 1 +fneg = 0x76, 1 +dneg = 0x77, 1 +ishl = 0x78, 1 +lshl = 0x79, 1 +ishr = 0x7a, 1 +lshr = 0x7b, 1 +iushr = 0x7c, 1 +lushr = 0x7d, 1 +iand = 0x7e, 1 +land = 0x7f, 1 +ior = 0x80, 1 +lor = 0x81, 1 +ixor = 0x82, 1 +lxor = 0x83, 1 +iinc = 0x84, 3 +i2l = 0x85, 1 +i2f = 0x86, 1 +i2d = 0x87, 1 +l2i = 0x88, 1 +l2f = 0x89, 1 +l2d = 0x8a, 1 +f2i = 0x8b, 1 +f2l = 0x8c, 1 +f2d = 0x8d, 1 +d2i = 0x8e, 1 +d2l = 0x8f, 1 +d2f = 0x90, 1 +i2b = 0x91, 1 +i2c = 0x92, 1 +i2s = 0x93, 1 +lcmp = 0x94, 1 +fcmpl = 0x95, 1 +fcmpg = 0x96, 1 +dcmpl = 0x97, 1 +dcmpg = 0x98, 1 +ifeq = 0x99, 0 +ifne = 0x9a, 0 +iflt = 0x9b, 0 +ifge = 0x9c, 0 +ifgt = 0x9d, 0 +ifle = 0x9e, 0 +if_icmpeq = 0x9f, 0 +if_icmpne = 0xa0, 0 +if_icmplt = 0xa1, 0 +if_icmpge = 0xa2, 0 +if_icmpgt = 0xa3, 0 +if_icmple = 0xa4, 0 +if_acmpeq = 0xa5, 0 +if_acmpne = 0xa6, 0 +goto = 0xa7, 0 +jsr = 0xa8, 0 +ret = 0xa9, 0 +tableswitch = 0xaa, 0 +lookupswitch = 0xab, 0 +ireturn = 0xac, 0 +lreturn = 0xad, 0 +freturn = 0xae, 0 +dreturn = 0xaf, 0 +areturn = 0xb0, 0 +return = 0xb1, 0 +getstatic = 0xb2, 3 +putstatic = 0xb3, 3 +getfield = 0xb4, 3 +putfield = 0xb5, 3 +invokevirtual = 0xb6, 3 +invokespecial = 0xb7, 3 +invokestatic = 0xb8, 3 +invokeinterface = 0xb9, 0 +new = 0xbb, 3 +newarray = 0xbc, 2 +anewarray = 0xbd, 3 +arraylength = 0xbe, 1 +athrow = 0xbf, 0 +checkcast = 0xc0, 3 +instanceof = 0xc1, 3 +monitorenter = 0xc2, 1 +monitorexit = 0xc3, 1 +wide = 0xc4, 1 +multianewarray = 0xc5, 4 +ifnull = 0xc6, 0 +ifnonnull = 0xc7, 0 +goto_w = 0xc8, 0 +jsr_w = 0xc9, 0 +breakpoint = 0xca, 0 + +#agetfield = 0xcb, 3 +bgetfield = 0xcc, 3 +cgetfield = 0xcd, 3 +#dgetfield = 0xce, 3 +#fgetfield = 0xcf, 3 +igetfield = 0xd0, 3 +lgetfield = 0xd1, 3 +sgetfield = 0xd2, 3 + +aputfield = 0xd3, 3 +bputfield = 0xd4, 3 +cputfield = 0xd5, 3 +#dputfield = 0xd6, 3 +#fputfield = 0xd7, 3 +iputfield = 0xd8, 3 +lputfield = 0xd9, 3 +#sputfield = 0xda, 3 + +iaccess_0 = 0xdb, 4 +iaccess_1 = 0xdc, 4 +iaccess_2 = 0xdd, 4 +iaccess_3 = 0xde, 4 + +#fast_iload = 0xdf, 2 +#fast_iload2 = 0xe0, 4 +#fast_icaload = 0xe1, 3 + +invokevfinal = 0xe2, 3 +#linearswitch = 0xe3, 0 +#binaryswitch = 0xe4, 0 + +iload_0_iconst_N = 231, 2 +iload_1_iconst_N = 232, 2 +iload_2_iconst_N = 233, 2 +iload_3_iconst_N = 234, 2 +iload_iconst_N = 235, 3 +invokeresolved = 236, 3 +iadd_istore_N = 237, 2 +isub_istore_N = 238, 2 +iand_istore_N = 239, 2 +ior_istore_N = 240, 2 +ixor_istore_N = 241, 2 +iadd_u4store = 242, 3 +isub_u4store = 243, 3 +iand_u4store = 244, 3 +ior_u4store = 245, 3 +ixor_u4store = 246, 3 +invokespecialresolved = 247, 3 +invokestaticresolved = 248, 3 + +return_register_finalizer = 229, 0 + +(nop) { + DISPATCH \seq_len +} + +(aconst_null,fconst_0) u4const_0 { + DISPATCH_START \seq_len + mov lr, #0 + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5) iconst_N { + sub lr, r0, #opc_iconst_0 + DISPATCH_START \seq_len + PUSH lr + DISPATCH_FINISH +} + +(lconst_0,dconst_0) u8const_0 { + DISPATCH_START \seq_len + mov tmp1, #0 + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(lconst_1) lconst_1 { + DISPATCH_START \seq_len + mov tmp2, #1 + DISPATCH_NEXT + mov tmp1, #0 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +(fconst_1) fconst_1 { + DISPATCH_START \seq_len + mov tmp1, #0x3f800000 + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(fconst_2) fconst_2 { + DISPATCH_START \seq_len + mov r2, #0x40000000 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(dconst_1) dconst_1 { + DISPATCH_START \seq_len + mov tmp1, #0x3f000000 + DISPATCH_NEXT + orr tmp1, tmp1, #0x00f00000 + DISPATCH_NEXT + mov tmp2, #0 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +(bipush) bipush { + DISPATCH_START \seq_len + mov tmp1, r2, lsl #24 + DISPATCH_NEXT + mov tmp1, tmp1, asr #24 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +# r1 = [jpc, #2] +(sipush) sipush { + DISPATCH_START \seq_len + mov tmp1, r1 + DISPATCH_NEXT + mov r2, r2, lsl #24 + DISPATCH_NEXT + orr tmp1, tmp1, r2, asr #16 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload,fload,aload) u4load { + DISPATCH_START \seq_len + rsb tmp1, r2, #0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(lload,dload) u8load { + DISPATCH_START \seq_len + sub r3, locals, r2, lsl #2 + DISPATCH_NEXT + ldmda r3, {tmp2, tmp1} + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +(aload_0,aload_1,aload_2,aload_3) { + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) { + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(fload_0,fload_1,fload_2,fload_3) { + rsb tmp1, r0, #opc_fload_0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(lload_0,dload_0) u8load_0 { + DISPATCH_START \seq_len + ldmda locals, {tmp2-tmp1} + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(lload_1,dload_1) u8load_1 { + DISPATCH_START \seq_len + ldmdb locals, {tmp2-tmp1} + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(lload_2,dload_2) u8load_2 { + DISPATCH_START \seq_len + ldr tmp2, [locals, #-12] + DISPATCH_NEXT + ldr tmp1, [locals, #-8] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +(lload_3,dload_3) u8load_3 { + DISPATCH_START \seq_len + ldr tmp2, [locals, #-16] + DISPATCH_NEXT + ldr tmp1, [locals, #-12] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +(iaload,faload,aaload) u4aload { + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry5: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + DISPATCH_NEXT + ldr tmp1, [r3, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(laload,daload) u8aload { + POP2 r2, r3 + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry6: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #3 + ldr tmp2, [r3, #16] + DISPATCH_NEXT + ldr tmp1, [r3, #20] + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +(baload) baload { + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry7: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2 + DISPATCH_NEXT + ldrsb tmp1, [r3, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(caload) caload { + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry8: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #1 + DISPATCH_NEXT + ldrh tmp1, [r3, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(saload) saload { + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry9: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #1 + DISPATCH_NEXT + ldrsh tmp1, [r3, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(astore,istore,fstore) u4store { + DISPATCH_START \seq_len + rsb tmp1, r2, #0 + DISPATCH_NEXT + POP r3 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(lstore,dstore) u8store { + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + sub r3, locals, r2, lsl #2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + stmda r3, {tmp2, tmp1} + DISPATCH_FINISH +} + +(astore_0,istore_0,fstore_0) u4store_0 { + DISPATCH_START \seq_len + DISPATCH_NEXT + POP tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, #0] + DISPATCH_FINISH +} + +(astore_1,istore_1,fstore_1) u4store_1 { + DISPATCH_START \seq_len + DISPATCH_NEXT + POP tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, #-4] + DISPATCH_FINISH +} + +(astore_2,istore_2,fstore_2) u4store_2 { + DISPATCH_START \seq_len + DISPATCH_NEXT + POP tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, #-8] + DISPATCH_FINISH +} + +(astore_3,istore_3,fstore_3) u4store_3 { + DISPATCH_START \seq_len + DISPATCH_NEXT + POP tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, #-12] + DISPATCH_FINISH +} + +(lstore_0,dstore_0) u8store_0 { + DISPATCH_START \seq_len + DISPATCH_NEXT + POP2 tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + stmda locals, {tmp2, tmp1} + DISPATCH_FINISH +} + +(lstore_1,dstore_1) u8store_1 { + DISPATCH_START \seq_len + DISPATCH_NEXT + POP2 tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + stmdb locals, {tmp2, tmp1} + DISPATCH_FINISH +} + +(lstore_2,dstore_2) u8store_2 { + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + str tmp2, [locals, #-12] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, #-8] + DISPATCH_FINISH +} + +(lstore_3,dstore_3) u8store_3 { + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + str tmp2, [locals, #-16] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, #-12] + DISPATCH_FINISH +} + +(iastore,fastore) u4astore { + POP3 r3, tmp2, tmp1 @ r3 = value, tmp2 = index, tmp1 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry10: + ldr lr, [tmp1, #8] @ lr = limit + DISPATCH_NEXT + cmp tmp2, lr + bcs array_bound_exception_jpc_1_tmp2 + DISPATCH_NEXT + add tmp1, tmp1, tmp2, lsl #2 + DISPATCH_NEXT + str r3, [tmp1, #12] + DISPATCH_FINISH +} + +(lastore,dastore) u8astore { + POP4 r2, r3, tmp2, tmp1 @ r2,r3 = value, tmp2 = index, tmp1 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry11: + ldr ip, [tmp1, #8] @ ip = limit + cmp tmp2, ip + DISPATCH_NEXT + bcs array_bound_exception_jpc_1_tmp2 + DISPATCH_NEXT + add tmp2, tmp1, tmp2, lsl #3 + str r2, [tmp2, #16] + DISPATCH_NEXT + DISPATCH_NEXT + str r3, [tmp2, #20] + DISPATCH_FINISH +} + +(bastore) bastore { + POP3 r3, tmp2, tmp1 @ r3 = value, tmp2 = index, tmp1 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry12: + ldr lr, [tmp1, #8] @ lr = limit + DISPATCH_NEXT + cmp tmp2, lr + bcs array_bound_exception_jpc_1_tmp2 + DISPATCH_NEXT + add tmp1, tmp1, tmp2 + DISPATCH_NEXT + strb r3, [tmp1, #12] + DISPATCH_FINISH +} + +(castore,sastore) u2astore { + POP3 r3, tmp2, tmp1 @ r3 = value, tmp2 = index, tmp1 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry13: + ldr lr, [tmp1, #8] @ lr = limit + DISPATCH_NEXT + cmp tmp2, lr + bcs array_bound_exception_jpc_1_tmp2 + DISPATCH_NEXT + add tmp1, tmp1, tmp2, lsl #1 + DISPATCH_NEXT + strh r3, [tmp1, #12] + DISPATCH_FINISH +} + +(pop) jpop { + DISPATCH_START \seq_len + add stack, stack, #4 + DISPATCH_FINISH +} + +(pop2) jpop2 { + DISPATCH_START \seq_len + add stack, stack, #8 + DISPATCH_FINISH +} + +(dup) dup { + DISPATCH_START \seq_len + ldr lr, [stack, #4] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +(dup_x1) dup_x1 { + DISPATCH_START \seq_len + POP2 r2, r3 + DISPATCH_NEXT + PUSH r2 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(dup_x2) dup_x2 { + DISPATCH_START \seq_len + POP3 r2, r3, lr + DISPATCH_NEXT + PUSH r2 + DISPATCH_NEXT + PUSH3 r2, r3, lr + DISPATCH_FINISH +} + +(dup2) dup2 { + DISPATCH_START \seq_len + ldmib stack, {r2, r3} + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(dup2_x1) dup2_x1 { + DISPATCH_START \seq_len + POP3 r2, r3, lr + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_NEXT + PUSH3 r2, r3, lr + DISPATCH_FINISH +} + +(dup2_x2) dup2_x2 { + DISPATCH_START \seq_len + POP4 r2, r3, tmp1, lr + DISPATCH_NEXT + PUSH2 r2, r3 + PUSH4 r2, r3, tmp1, lr + DISPATCH_FINISH +} + +(swap) swap { + DISPATCH_START \seq_len + POP2 r2, r3 + DISPATCH_NEXT + PUSH r2 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + + +(iadd) iadd { + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + add tmp2, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(ladd) ladd { + DISPATCH_START \seq_len + POP4 r2, r3, tmp1, lr + DISPATCH_NEXT + adds r2, r2, tmp1 + adc r3, r3, lr + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(fadd) fadd { + POP2 r0, r1 + bl __aeabi_fadd + PUSH r0 + DISPATCH \seq_len +} + +(isub) isub { + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(lsub) lsub { + DISPATCH_START \seq_len + POP4 r2, r3, tmp1, lr + DISPATCH_NEXT + subs r2, tmp1, r2 + sbc r3, lr, r3 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(fsub) fsub { + POP r1 + POP r0 + bl __aeabi_fsub + PUSH r0 + DISPATCH \seq_len +} + +(imul) imul { + DISPATCH_START \seq_len + POP2 r2, tmp1 + DISPATCH_NEXT + mul tmp2, r2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(lmul) lmul { + POP4 r2, tmp1, ip, lr + umull r3, r0, ip, r2 + mla tmp1, ip, tmp1, r0 + DISPATCH_START \seq_len + mla tmp1, lr, r2, tmp1 + DISPATCH_NEXT + PUSH2 r3, tmp1 + DISPATCH_FINISH +} + +(fmul) fmul { + POP2 r0, r1 + bl __aeabi_fmul + PUSH r0 + DISPATCH \seq_len +} + +(ldiv) ldiv { + POP2 r2, r3 + POP2 r0, r1 + orrs lr, r2, r3 + beq .ldiv_0 + bl __aeabi_ldivmod + PUSH2 r0, r1 + DISPATCH \seq_len +} + +(fdiv) fdiv { + POP r1 + POP r0 + bl __aeabi_fdiv + PUSH r0 + DISPATCH \seq_len +} + +(ddiv) ddiv { + POP2 r2, r3 + POP2 r0, r1 + bl __aeabi_ddiv + PUSH2 r0, r1 + DISPATCH \seq_len +} + +(lrem) lrem { + POP2 r2, r3 + POP2 r0, r1 + orrs lr, r2, r3 + beq .lrem_0 + bl __aeabi_ldivmod + PUSH2 r2, r3 + DISPATCH \seq_len +} + +(frem) frem { +@ ECN: It must be possible to do better than this + POP r0 + bl __aeabi_f2d + PUSH2 r0, r1 + GET_STACK 2, r0 + bl __aeabi_f2d + POP2 r2, r3 + bl fmod + bl __aeabi_d2f + PUT_STACK 0, r0 + DISPATCH \seq_len +} + +(drem) drem { + POP2 r2, r3 + POP2 r0, r1 + bl fmod + PUSH2 r0, r1 + DISPATCH \seq_len +} + +(ineg) ineg { + DISPATCH_START \seq_len + POP tmp1 + DISPATCH_NEXT + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(lneg) lneg { + DISPATCH_START \seq_len + POP2 r2, r3 + DISPATCH_NEXT + rsbs r2, r2, #0 + rsc r3, r3, #0 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(fneg) fneg { + DISPATCH_START \seq_len + POP r2 + DISPATCH_NEXT + eor r2, r2, #0x80000000 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(dneg) dneg { + DISPATCH_START \seq_len + GET_STACK 1, r2 + DISPATCH_NEXT + eor r2, r2, #0x80000000 + DISPATCH_NEXT + PUT_STACK 1, r2 + DISPATCH_FINISH +} + +(ishl) ishl { + DISPATCH_START \seq_len + POP2 r2, r3 + DISPATCH_NEXT + and r2, r2, #31 + mov r2, r3, lsl r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(lshl) lshl { + DISPATCH_START \seq_len + POP3 r2, r3, lr + DISPATCH_NEXT + tst r2, #32 + and r2, r2, #31 + movne tmp1, #0 + movne lr, r3, lsl r2 + moveq tmp1, r3, lsl r2 + moveq lr, lr, lsl r2 + rsbeq r2, r2, #32 + orreq lr, lr, r3, lsr r2 + PUSH2 tmp1, lr + DISPATCH_FINISH +} + +(ishr) ishr { + DISPATCH_START \seq_len + POP2 r2, r3 + DISPATCH_NEXT + and r2, r2, #31 + mov r2, r3, asr r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(lshr) lshr { + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + tst r2, #32 + and r2, r2, #31 + movne lr, tmp1, asr #31 + movne r3, tmp1, asr r2 + moveq lr, tmp1, asr r2 + moveq r3, r3, lsr r2 + rsbeq r2, r2, #32 + orreq r3, r3, tmp1, lsl r2 + PUSH2 r3, lr + DISPATCH_FINISH +} + +(iushr) iushr { + DISPATCH_START \seq_len + POP2 r2, r3 + DISPATCH_NEXT + and r2, r2, #31 + mov r2, r3, lsr r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(lushr) lushr { + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + tst r2, #32 + and r2, r2, #31 + movne lr, #0 + movne r3, tmp1, lsr r2 + moveq lr, tmp1, lsr r2 + moveq r3, r3, lsr r2 + rsbeq r2, r2, #32 + orreq r3, r3, tmp1, lsl r2 + PUSH2 r3, lr + DISPATCH_FINISH +} + +(iand) iand { + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + and tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(land) land { + DISPATCH_START \seq_len + POP4 r2, r3, tmp1, lr + DISPATCH_NEXT + and r2, tmp1, r2 + and r3, lr, r3 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(ior) ior { + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + orr tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(lor) lor { + DISPATCH_START \seq_len + POP4 r2, r3, tmp1, lr + DISPATCH_NEXT + orr r2, tmp1, r2 + orr r3, lr, r3 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(ixor) ixor { + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + eor tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(lxor) lxor { + DISPATCH_START \seq_len + POP4 r2, r3, tmp1, lr + DISPATCH_NEXT + eor r2, tmp1, r2 + eor r3, lr, r3 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iinc) iinc { + ldrsb lr, [jpc, #2] + DISPATCH_START \seq_len + rsb tmp1, r2, #0 + DISPATCH_NEXT + ldr r3, [locals, tmp1, lsl #2] + DISPATCH_NEXT + add r3, r3, lr + DISPATCH_NEXT + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +(i2l) i2l { + DISPATCH_START \seq_len + POP r2 + DISPATCH_NEXT + mov r3, r2, asr #31 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(i2f) i2f { + POP r0 + bl __aeabi_i2f + PUSH r0 + DISPATCH \seq_len +} + +(i2d) i2d { + POP r0 + bl __aeabi_i2d + PUSH2 r0, r1 + DISPATCH \seq_len +} + +(l2i) l2i { + DISPATCH_START \seq_len + POP r3 + DISPATCH_NEXT + PUT_STACK 0, r3 + DISPATCH_FINISH +} + +(l2f) l2f { + POP2 r0, r1 + bl __aeabi_l2f + PUSH r0 + DISPATCH \seq_len +} + +(l2d) l2d { + POP2 r0, r1 + bl __aeabi_l2d + PUSH2 r0, r1 + DISPATCH \seq_len +} + +(f2i) f2i { + POP r0 + bl _ZN13SharedRuntime3f2iEf + PUSH r0 + DISPATCH \seq_len +} + +(f2l) f2l { + POP r0 + bl _ZN13SharedRuntime3f2lEf + PUSH2 r0, r1 + DISPATCH \seq_len +} + +(f2d) f2d { + POP r0 + bl __aeabi_f2d + PUSH2 r0, r1 + DISPATCH \seq_len +} + +(d2i) d2i { + POP2 r0, r1 + bl _ZN13SharedRuntime3d2iEd + PUSH r0 + DISPATCH \seq_len +} + +(d2l) d2l { + POP2 r0, r1 + bl _ZN13SharedRuntime3d2lEd + PUSH2 r0, r1 + DISPATCH \seq_len +} + +(d2f) d2f { + POP2 r0, r1 + bl __aeabi_d2f + PUSH r0 + DISPATCH \seq_len +} + +(i2b) i2b { + DISPATCH_START \seq_len + POP r3 + DISPATCH_NEXT + mov r3, r3, asl #24 + mov r3, r3, asr #24 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +(i2c) i2c { + DISPATCH_START \seq_len + POP r3 + DISPATCH_NEXT + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +(i2s) i2s { + DISPATCH_START \seq_len + POP r3 + DISPATCH_NEXT + mov r3, r3, asl #16 + mov r3, r3, asr #16 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +(lcmp) lcmp { + POP4 r2, r3, tmp1, lr + DISPATCH_START \seq_len + subs r2, tmp1, r2 + movne r2, #1 + sbcs lr, lr, r3 + DISPATCH_NEXT + movne r2, #1 + rsblt r2, r2, #0 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(fcmpl) fcmpl { + ldmib stack, {r0, r1} + bl __aeabi_fcmpgt + cmp r0, #0 + movne r3, #-1 + bne 3f + ldmib stack, {r0, r1} + bl __aeabi_fcmplt + cmp r0, #0 + movne r3, #1 + bne 3f + ldmib stack, {r0, r1} + bl __aeabi_fcmpeq + cmp r0, #0 + movne r3, #0 + moveq r3, #-1 +3: + DISPATCH_START \seq_len + add stack, stack, #8 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +(fcmpg) fcmpg { + ldmib stack, {r0, r1} + bl __aeabi_fcmpgt + cmp r0, #0 + movne r3, #-1 + bne 4f + ldmib stack, {r0, r1} + bl __aeabi_fcmplt + cmp r0, #0 + movne r3, #1 + bne 4f + ldmib stack, {r0, r1} + bl __aeabi_fcmpeq + cmp r0, #0 + movne r3, #0 + moveq r3, #1 +4: + DISPATCH_START \seq_len + add stack, stack, #8 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +(dcmpl) dcmpl { + ldmib stack, {r0, r1, r2, r3} + bl __aeabi_dcmpgt + cmp r0, #0 + movne r3, #-1 + bne 5f + ldmib stack, {r0, r1, r2, r3} + bl __aeabi_dcmplt + cmp r0, #0 + movne r3, #1 + bne 5f + ldmib stack, {r0, r1, r2, r3} + bl __aeabi_dcmpeq + cmp r0, #0 + movne r3, #0 + moveq r3, #-1 +5: + DISPATCH_START \seq_len + add stack, stack, #16 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +(dcmpg) dcmpg { + ldmib stack, {r0, r1, r2, r3} + bl __aeabi_dcmpgt + cmp r0, #0 + movne r3, #-1 + bne 6f + ldmib stack, {r0, r1, r2, r3} + bl __aeabi_dcmplt + cmp r0, #0 + movne r3, #1 + bne 6f + ldmib stack, {r0, r1, r2, r3} + bl __aeabi_dcmpeq + cmp r0, #0 + movne r3, #0 + moveq r3, #1 +6: + DISPATCH_START \seq_len + add stack, stack, #16 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +# r1 = [jpc, #2] +(ifeq,ifnull) ifeq_unsafe { + POP r3 + mov r2, r2, lsl #24 + cmp r3, #0 + orr ip, r1, r2, asr #16 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ifne,ifnonnull) ifne_unsafe { + POP r3 + mov r2, r2, lsl #24 + cmp r3, #0 + orr ip, r1, r2, asr #16 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iflt) iflt_unsafe { + POP r3 + mov r2, r2, lsl #24 + cmp r3, #0 + orr ip, r1, r2, asr #16 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ifge) ifge_unsafe { + POP r3 + mov r2, r2, lsl #24 + cmp r3, #0 + orr ip, r1, r2, asr #16 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ifgt) ifgt_unsafe { + POP r3 + mov r2, r2, lsl #24 + cmp r3, #0 + orr ip, r1, r2, asr #16 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ifle) ifle_unsafe { + POP r3 + mov r2, r2, lsl #24 + cmp r3, #0 + orr ip, r1, r2, asr #16 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(if_icmpeq,if_acmpeq) if_icmpeq_unsafe { + POP2 r3, tmp1 + mov r2, r2, lsl #24 + cmp tmp1, r3 + orr ip, r1, r2, asr #16 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(if_icmpne,if_acmpne) if_icmpne_unsafe { + POP2 r3, tmp1 + mov r2, r2, lsl #24 + cmp tmp1, r3 + orr ip, r1, r2, asr #16 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(if_icmplt) if_icmplt_unsafe { + POP2 r3, tmp1 + mov r2, r2, lsl #24 + cmp tmp1, r3 + orr ip, r1, r2, asr #16 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(if_icmpge) if_icmpge_unsafe { + POP2 r3, tmp1 + mov r2, r2, lsl #24 + cmp tmp1, r3 + orr ip, r1, r2, asr #16 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(if_icmpgt) if_icmpgt_unsafe { + POP2 r3, tmp1 + mov r2, r2, lsl #24 + cmp tmp1, r3 + orr ip, r1, r2, asr #16 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(if_icmple) if_icmple_unsafe { + POP2 r3, tmp1 + mov r2, r2, lsl #24 + cmp tmp1, r3 + orr ip, r1, r2, asr #16 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(goto) goto_unsafe { + mov r2, r2, lsl #24 + orr ip, r1, r2, asr #16 + DISPATCH_START_REG ip + DISPATCH_BYTECODE +} + +(jsr) jsr { + ldr r3, [istate, #ISTATE_METHOD] + ldr r1, [r3, #8] + rsb r2, r1, jpc + sub r2, r2, #45 + PUSH r2 + b do_goto_safe +} + +# r2 = [jpc, #1] +# r1 = [jpc, #2] +(ret) ret { + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [r0, #8] + ldr r1, [locals, -r2, lsl #2] + add jpc, r3, r1 + DISPATCH 48 +} + +# ECN: We dont do safe and unsafe versions of tableswitch and lookupswitch +(tableswitch) tableswitch { + POP a2 + bic a1, jpc, #3 + ldr a4,[a1,#8] +@ BYTESEX_REVERSE a3, a4, a3 + + eor a3, a4, a4, ror #16 + bic a3, a3, #0xff0000 + mov a4, a4, ror #8 + eor a3, a4, a3, lsr #8 + + ldr a4,[a1,#12] +@ BYTESEX_REVERSE a4, a4, ip + + eor ip, a4, a4, ror #16 + bic ip, ip, #0xff0000 + mov a4, a4, ror #8 + eor a4, a4, ip, lsr #8 + + sub a2,a2,a3 + sub a4,a4,a3 + cmp a4,a2 + ldrcc a1,[a1,#4] + addcs a1,a1,a2,LSL #2 + ldrcs a1,[a1,#16] +@ BYTESEX_REVERSE a1, a1, a4 + + eor a4, a1, a1, ror #16 + bic a4, a4, #0xff0000 + mov a1, a1, ror #8 + eors ip, a1, a4, lsr #8 + + DISPATCH_START_REG ip + DISPATCH_BYTECODE +} + +(lookupswitch) lookupswitch { + POP a2 + bic a1, jpc, #3 +@ BYTESEX_REVERSE a2, a2, ip + + eor ip, a2, a2, ror #16 + bic ip, ip, #0xff0000 + mov a2, a2, ror #8 + eor a2, a2, ip, lsr #8 + + ldr a3,[a1,#8] +@ BYTESEX_REVERSE a3, a3, ip + + eor ip, a3, a3, ror #16 + bic ip, ip, #0xff0000 + mov a3, a3, ror #8 + eor a3, a3, ip, lsr #8 + + subs a4,a3,#1 + bmi 1f + add a1, a1, #4 +0: + ldr a3,[a1,#8]! + cmp a3,a2 + beq 2f + subs a4,a4,#1 + bpl 0b +1: + bic a1, jpc, #3 +2: + ldr a2,[a1,#4] +@ BYTESEX_REVERSE a2, a2, ip + + eor ip, a2, a2, ror #16 + bic ip, ip, #0xff0000 + mov a2, a2, ror #8 + eors ip, a2, ip, lsr #8 + + DISPATCH_START_REG ip + DISPATCH_BYTECODE +} + +(igetfield) igetfield { + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP tmp1 + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry78: + ldr tmp2, [tmp1, tmp2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(bgetfield) bgetfield { + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP tmp1 + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry79: + ldrsb tmp2, [tmp1, tmp2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(cgetfield) cgetfield { + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP tmp1 + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry80: + ldrh tmp2, [tmp1, tmp2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(sgetfield) sgetfield { + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP tmp1 + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry81: + ldrsh tmp2, [tmp1, tmp2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(lgetfield) lgetfield { + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP tmp1 + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT +.abortentry82: + ldmia tmp2, {tmp2, tmp1} + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +(iputfield) iputfield { + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP2 r3, tmp1 @ r3 = value, tmp1 = object + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT +.abortentry83: + str r3, [tmp1, tmp2] + DISPATCH_FINISH +} + +(cputfield) cputfield { + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP2 r3, tmp1 @ r3 = value, tmp1 = object + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT +.abortentry84: + strh r3, [tmp1, tmp2] + DISPATCH_FINISH +} + +(bputfield) bputfield { + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP2 r3, tmp1 @ r3 = value, tmp1 = object + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT +.abortentry85: + strb r3, [tmp1, tmp2] + DISPATCH_FINISH +} + +(aputfield) aputfield { + GET_STACK 1, r0 @ r0 = object + add tmp2, constpool, r1, lsl #12 + POP r1 @ r1 = value + add tmp2, tmp2, r2, lsl #4 + ldr tmp2, [tmp2, #8] + cmp r0, #0 + beq null_ptr_exception + add r0, r0, tmp2 + bl oop_store + ldr r3, [dispatch, #Universe_collectedHeap_Address-XXX] + DISPATCH_START 3 + POP r2 + ldr r3, [r3, #0] + DISPATCH_NEXT + ldr r3, [r3, #12] + DISPATCH_NEXT + ldr r3, [r3, #76] + mov tmp2, #0 + strb tmp2, [r3, r2, lsr #9] + DISPATCH_FINISH +} + +(lputfield) lputfield { + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP3 r3, tmp1, lr @ r3, tmp1 = value, lr = object + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + add tmp2, lr, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT +.abortentry86: + stm tmp2, {r3, tmp1} + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +# r1 = [jpc, #2] +(getstatic) getstatic { + DISPATCH_START \seq_len + add tmp2, constpool, r1, lsl #12 + ldr r3, [tmp2, r2, lsl #4]! @ tmp2 = cache, r3 = flags + DISPATCH_NEXT + and r3, r3, #0x00ff0000 + cmp r3, #178 << 16 + bne resolve_getstatic + ldr r3, [tmp2, #4] + ldr r2, [tmp2, #12] + ldr lr, [tmp2, #8] + movs r2, r2, lsr #29 + bhi getstatic_w @ C = 1, Z = 0 => R2 == 3, 5, 7 + bcs getstatic_h @ C = 1 => R2 = 1 + beq getstatic_sb @ Z = 1 => R2 = 0 + tst r2, #2 + bne getstatic_dw + b getstatic_sh +} + +# r2 = [jpc, #1] +# r1 = [jpc, #2] +(putstatic) putstatic { + DISPATCH_START \seq_len + add tmp2, constpool, r1, lsl #12 + ldr r3, [tmp2, r2, lsl #4]! @ tmp2 = cache, r3 = flags + DISPATCH_NEXT + and r3, r3, #0xff000000 + cmp r3, #179 << 24 + bne resolve_putstatic + ldr r3, [tmp2, #4] @ r3 = object + ldr lr, [tmp2, #12] @ lr = tos_type + ldr r2, [tmp2, #8] @ r2 = offset + movs lr, lr, lsr #29 + bhi putstatic_w @ C = 1, Z = 0 => R2 == 3, 5, 7 + bcs putstatic_h @ C = 1 => R2 = 1 + beq putstatic_sb @ Z = 1 => R2 = 0 + tst lr, #2 + bne putstatic_dw + b putstatic_sh +} + +(return) return_unsafe { + + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + ldr tmp_xxx, [istate, #ISTATE_THREAD] + + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + + ldr r2, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [r2, #0] + ldrh r0, [r0, #40] + add r1, r2, #4 + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + add stack, r1, r0, lsl #2 + cmp istate, #0 + beq normal_return + + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT + add r2, r2, #4 + DISPATCH_NEXT + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + bl return_check_monitors + b 2b +} + +(ireturn,areturn,freturn) ireturn_unsafe { + + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + ldr tmp_xxx, [istate, #ISTATE_THREAD] + + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + + POP r1 @ pop result before we lose stack + + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + bl return_check_monitors + b 2b +} + +(lreturn,dreturn) lreturn_unsafe { + + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + + ldr r2, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [r2, #0] + ldrh r0, [r0, #40] + add r1, r2, #4 + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + + POP2 r2, r3 + + add stack, r1, r0, lsl #2 + stmdb stack!, {r2, r3} + cmp istate, #0 + beq normal_return + + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT + add r2, r2, #4 + DISPATCH_NEXT + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + bl return_check_monitors + b 2b +} + +(ldc) ldc { + ldrb lr, [jpc, #1] + ldr r3, [istate, #ISTATE_METHOD] @ method + + DISPATCH_START \seq_len + + ldr r2, [r3, #12] @ constants + ldr r3, [r2, #8] + add r3, r3, #12 + ldrb r3, [r3, lr] + + DISPATCH_NEXT + + cmp r3, #JVM_CONSTANT_Integer + cmpne r3, #JVM_CONSTANT_Float + cmpne r3, #JVM_CONSTANT_String + bne 1f + + DISPATCH_NEXT + + add r3, r2, lr, lsl #2 + ldr lr, [r3, #32] + PUSH lr + DISPATCH_FINISH +1: + cmp r3, #JVM_CONSTANT_Class + bne 2f + add r0, r2, #32 + ldr r0, [r0, lr, lsl #2] + ldr r1, [r0, #60] + PUSH r1 + DISPATCH 0 +2: + sub jpc, jpc, #\seq_len + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + mov r1, #0 + bl _ZN18InterpreterRuntime3ldcEP10JavaThreadb + ldr r0, [istate, #ISTATE_THREAD] @ thread + ldr stack, [istate, #ISTATE_STACK] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr r1, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + add constpool, constpool, #CONST_POOL_OFFSET + cmp r1, #0 + ldr locals, [istate, #ISTATE_LOCALS] + bne handle_exception + ldr r3, [r0, #THREAD_VM_RESULT] + mov r2, #0 + PUSH r3 + str r2, [r0, #THREAD_VM_RESULT] + DISPATCH \seq_len +} + +(ldc_w) ldc_w { + ldrb lr, [jpc, #1] + + ldr r3, [istate, #ISTATE_METHOD] @ method + ldrb ip, [jpc, #2] + ldr r2, [r3, #12] @ constants + + DISPATCH_START \seq_len + + ldr r3, [r2, #8] + orr lr, ip, lr, lsl #8 + add r3, r3, #12 + ldrb r3, [r3, lr] + + DISPATCH_NEXT + + cmp r3, #JVM_CONSTANT_Integer + cmpne r3, #JVM_CONSTANT_Float + cmpne r3, #JVM_CONSTANT_String + bne 1f + + DISPATCH_NEXT + + add r3, r2, lr, lsl #2 + ldr lr, [r3, #32] + PUSH lr + DISPATCH_FINISH +1: + cmp r3, #JVM_CONSTANT_Class + bne 2f + add r0, r2, #32 + ldr r0, [r0, lr, lsl #2] + ldr r1, [r0, #60] + PUSH r1 + DISPATCH 0 +2: + sub jpc, jpc, #\seq_len + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + mov r1, #1 + bl _ZN18InterpreterRuntime3ldcEP10JavaThreadb + ldr r0, [istate, #ISTATE_THREAD] @ thread + ldr stack, [istate, #ISTATE_STACK] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr r1, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + add constpool, constpool, #CONST_POOL_OFFSET + cmp r1, #0 + ldr locals, [istate, #ISTATE_LOCALS] + bne handle_exception + ldr r3, [r0, #THREAD_VM_RESULT] + mov r2, #0 + PUSH r3 + str r2, [r0, #THREAD_VM_RESULT] + DISPATCH \seq_len +} + +(ldc2_w) ldc2_w { + ldrb r3, [jpc, #1] + + ldr tmp1, [istate, #ISTATE_METHOD] @ method + ldrb lr, [jpc, #2] + ldr r2, [tmp1, #12] @ constants + + DISPATCH_START \seq_len + + ldr tmp1, [r2, #8] + orr r3, lr, r3, lsl #8 + add tmp1, tmp1, #12 + ldrb tmp1, [tmp1, r3] + + DISPATCH_NEXT + + cmp tmp1, #JVM_CONSTANT_Long + cmpne tmp1, #JVM_CONSTANT_Double + bne vm_fatal_error + + DISPATCH_NEXT + add tmp1, r2, r3, lsl #2 + add tmp1, tmp1, #32 + ldmia tmp1, {r3, tmp1} + PUSH2 r3, tmp1 + DISPATCH_FINISH +} + +(iadd_u4store) { + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH +} + +(isub_u4store) { + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH +} + +(iand_u4store) { + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + and tmp2, tmp1, tmp2 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH +} + +(ior_u4store) { + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + orr tmp2, tmp1, tmp2 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH +} + +(ixor_u4store) { + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + eor tmp2, tmp1, tmp2 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH +} + +(iadd_istore_N) { + ldrb lr, [jpc, #1] + DISPATCH_START \seq_len + DISPATCH_NEXT + rsb r3, lr, #opc_istore_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH +} + +(isub_istore_N) { + ldrb lr, [jpc, #1] + DISPATCH_START \seq_len + DISPATCH_NEXT + rsb r3, lr, #opc_istore_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH +} + +(iand_istore_N) { + ldrb lr, [jpc, #1] + DISPATCH_START \seq_len + DISPATCH_NEXT + rsb r3, lr, #opc_istore_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + and tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH +} + +(ior_istore_N) { + ldrb lr, [jpc, #1] + DISPATCH_START \seq_len + DISPATCH_NEXT + rsb r3, lr, #opc_istore_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + orr tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH +} + +(ixor_istore_N) { + ldrb lr, [jpc, #1] + DISPATCH_START \seq_len + DISPATCH_NEXT + rsb r3, lr, #opc_istore_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + eor tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload_iconst_N) +{ + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + rsb r2, r2, #0 + DISPATCH_NEXT + sub r3, r3, #opc_iconst_0 + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp1 + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + ldrb r2, [jpc, #1-\seq_len] + DISPATCH_NEXT + ldr tmp1, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp2, r2, #opc_iconst_0 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +# (aload_N)(getfield) +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +{ + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb r3, [jpc, #2] + add tmp2, constpool, r2, lsl #12 + DISPATCH_START 4 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, r3, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + DISPATCH_NEXT + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry87: + ldr tmp2, [tmp1, tmp2] + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +############################################################################### +# ECN: Optimised bytecode pairs +############################################################################### + +# --- ECN: load; load --------------------------------------------------------- + +(aload_0,aload_1,aload_2,aload_3) +(aload_0,aload_1,aload_2,aload_3) +{ + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_aload_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +(aload_0,aload_1,aload_2,aload_3) +(iload_0,iload_1,iload_2,iload_3) +{ + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_iload_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(aload_0,aload_1,aload_2,aload_3) +{ + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_aload_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +# 7 cycles +(iload_0,iload_1,iload_2,iload_3) +(iload_0,iload_1,iload_2,iload_3) +{ + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_iload_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +(aload_0,aload_1,aload_2,aload_3) +(iload,aload,fload) +{ + ldrb r3, [jpc, #2] + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp1 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(iload,aload,fload) +{ + ldrb r3, [jpc, #2] + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp1 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload,aload,fload) +(aload_0,aload_1,aload_2,aload_3) +{ + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_aload_0 + DISPATCH_NEXT + rsb tmp1, r2, #0 + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload,aload,fload) +(iload_0,iload_1,iload_2,iload_3) +{ + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_iload_0 + DISPATCH_NEXT + rsb tmp1, r2, #0 + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload,aload,fload)(iload,aload,fload) { + ldrb tmp2, [jpc, #3] + rsb tmp1, r2, #0 + DISPATCH_START \seq_len + rsb tmp2, tmp2, #0 + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH +} + +# --- ECN: load; store -------------------------------------------------------- + +(aload_0,aload_1,aload_2,aload_3) +(astore_0,astore_1,astore_2,astore_3) +{ + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_astore_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(istore_0,istore_1,istore_2,istore_3) +{ + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_istore_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +(aload_0,aload_1,aload_2,aload_3) +(astore,istore,fstore) +{ + ldrb tmp2, [jpc, #2] + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + rsb tmp2, tmp2, #0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(astore,istore,fstore) +{ + ldrb tmp2, [jpc, #2] + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + rsb tmp2, tmp2, #0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload,aload,fload) +(astore_0,astore_1,astore_2,astore_3) +{ + DISPATCH_START \seq_len + rsb tmp1, r1, #opc_astore_0 + DISPATCH_NEXT + rsb tmp2, r2, #0 + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload,aload,fload) +(istore_0,istore_1,istore_2,istore_3) +{ + DISPATCH_START \seq_len + rsb tmp1, r1, #opc_istore_0 + DISPATCH_NEXT + rsb tmp2, r2, #0 + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload,aload,fload)(astore,istore,fstore) { + ldrb tmp1, [jpc, #3] + rsb tmp2, r2, #0 + DISPATCH_START \seq_len + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +# --- ECN: load; const ------------------------------------------------------- + +(aload_0,aload_1,aload_2,aload_3) +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5) +{ + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + sub tmp2, r1, #opc_iconst_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5) +{ + add r0, r0, #opc_iload_0_iconst_N-opc_iload_0 + strb r0, [jpc] + b do_iload_0_iconst_N +} + +# r2 = [jpc, #1] +(iload,aload,fload) +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5) +{ + cmp r0, #opc_iload + DISPATCH_START \seq_len + sub r3, r1, #opc_iconst_0 + DISPATCH_NEXT + ldr tmp2, [locals, -r2, lsl #2] + DISPATCH_NEXT + beq 1f + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +1: + mov tmp1, #opc_iload_iconst_N + strb tmp1, [jpc, #-\seq_len]! + b do_iload_iconst_N +} + +(aload_0,aload_1,aload_2,aload_3) +(bipush) +{ + ldrsb r2, [jpc, #2] + rsb r3, r0, #opc_aload_0 + DISPATCH_START \seq_len + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(bipush) +{ + ldrsb r2, [jpc, #2] + rsb r3, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(aload_0,aload_1,aload_2,aload_3) +(sipush) +{ + ldrsb r2, [jpc, #2] @ zero_extendqisi2 + ldrb lr, [jpc, #3] @ zero_extendqisi2 + rsb r3, r0, #opc_aload_0 + DISPATCH_START \seq_len + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + orr r2, lr, r2, asl #8 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(sipush) +{ + ldrsb r2, [jpc, #2] @ zero_extendqisi2 + ldrb lr, [jpc, #3] @ zero_extendqisi2 + rsb r3, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + orr r2, lr, r2, asl #8 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload,aload,fload)(bipush) { + ldrsb r3, [jpc, #3] + DISPATCH_START \seq_len + ldr lr, [locals, -r2, lsl #2] + DISPATCH_NEXT + PUSH2 r3, lr + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload,aload,fload)(sipush) { + ldrsb r3, [jpc, #3] + ldrb lr, [jpc, #4] + DISPATCH_START \seq_len + ldr tmp1, [locals, -r2, lsl #2] + orr r3, lr, r3, asl #8 + DISPATCH_NEXT + PUSH2 r3, tmp1 + DISPATCH_FINISH +} + +# --- ECN: load; Xaload ------------------------------------------------------- + +(iload_0,iload_1,iload_2,iload_3) +(iaload,aaload,faload) +{ + POP r3 + rsb r2, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr r2, [locals, r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry19: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2, lsl #2 + ldr lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload,aload,fload)(iaload,aaload,faload) { + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry20: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2, lsl #2 + ldr lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(baload) +{ + POP r3 + rsb r2, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr r2, [locals, r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry21: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2 + ldrsb lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(caload) +{ + POP r3 + rsb r2, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr r2, [locals, r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry22: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2, lsl #1 + ldrh lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(saload) +{ + POP r3 + rsb r2, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr r2, [locals, r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry23: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2, lsl #1 + ldrsh lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload,aload,fload)(baload) { + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry24: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2 + ldrsb lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload,aload,fload)(caload) { + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry25: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2, lsl #1 + ldrh lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload,aload,fload)(saload) { + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry26: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2, lsl #1 + ldrsh lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +# --- ECN: load; Xastore ------------------------------------------------------- + +(iload_0,iload_1,iload_2,iload_3) +(iastore,fastore) +{ + POP2 r2, r3 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry27: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(bastore) +{ + POP2 r2, r3 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry28: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2 + strb tmp1, [r3, #12] + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(castore,sastore) +{ + POP2 r2, r3 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry29: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #1 + strh tmp1, [r3, #12] + DISPATCH_FINISH +} + +(iload,aload,fload)(iastore,fastore) { + POP2 r3, tmp1 + DISPATCH_START \seq_len + ldr r2, [locals, -r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry30: + ldr lr, [tmp1, #8] @ lr = limit + DISPATCH_NEXT + cmp r3, lr + bcs array_bound_exception_jpc_1_r3 + DISPATCH_NEXT + add tmp1, tmp1, r3, lsl #2 + str r2, [tmp1, #12] + DISPATCH_FINISH +} + +(iload,aload,fload)(bastore) { + POP2 r3, tmp1 + DISPATCH_START \seq_len + ldr r2, [locals, -r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry31: + ldr lr, [tmp1, #8] @ lr = limit + DISPATCH_NEXT + cmp r3, lr + bcs array_bound_exception_jpc_1_r3 + DISPATCH_NEXT + add tmp1, tmp1, r3 + strb r2, [tmp1, #12] + DISPATCH_FINISH +} + +(iload,aload,fload)(castore,sastore) { + POP2 r3, tmp1 + DISPATCH_START \seq_len + ldr r2, [locals, -r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry32: + ldr lr, [tmp1, #8] @ lr = limit + DISPATCH_NEXT + cmp r3, lr + bcs array_bound_exception_jpc_1_r3 + DISPATCH_NEXT + add tmp1, tmp1, r3, lsl #1 + strh r2, [tmp1, #12] + DISPATCH_FINISH +} + +# --- ECN: load; dataop ------------------------------------------------------- + +(iload_0,iload_1,iload_2,iload_3) +(iadd) +{ + POP tmp2 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + add tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(iload,aload,fload)(iadd) { + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + POP tmp1 + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(isub) +{ + POP tmp2 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + sub tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(iload,aload,fload)(isub) { + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + POP tmp1 + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(imul) +{ + POP r2 + rsb lr, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr lr, [locals, lr, lsl #2] + DISPATCH_NEXT + mul r3, r2, lr + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +(iload,aload,fload)(imul) { + DISPATCH_START \seq_len + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_NEXT + mul lr, r3, r2 + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(idiv) +{ + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + add jpc, jpc, #1 + POP r1 + b int_div +} + +(iload,aload,fload)(idiv) { + add jpc, jpc, #2 + POP r1 + ldr r0, [locals, -r2, lsl #2] + b int_div +} + +(iload_0,iload_1,iload_2,iload_3) +(irem) +{ + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + add jpc, jpc, #1 + POP r1 + b int_rem +} + +(iload,aload,fload)(irem) { + ldr r0, [locals, -r2, lsl #2] + add jpc, jpc, #2 + POP r1 + b int_rem +} + +(iload_0,iload_1,iload_2,iload_3) +(ineg) +{ + rsb lr, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr lr, [locals, lr, lsl #2] + DISPATCH_NEXT + rsb lr, lr, #0 + PUSH lr + DISPATCH_FINISH +} + +(iload,aload,fload)(ineg) { + DISPATCH_START \seq_len + ldr r2, [locals, -r2, lsl #2] + DISPATCH_NEXT + rsb r2, r2, #0 + PUSH r2 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(ishl) +{ + POP r2 + rsb lr, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr lr, [locals, lr, lsl #2] + DISPATCH_NEXT + mov lr, r2, lsl lr + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +(iload,aload,fload)(ishl) { + DISPATCH_START \seq_len + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_NEXT + mov r2, r3, lsl r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(ishr) +{ + POP r2 + rsb lr, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr lr, [locals, lr, lsl #2] + DISPATCH_NEXT + mov lr, r2, asr lr + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +(iload,aload,fload)(ishr) { + DISPATCH_START \seq_len + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_NEXT + mov r2, r3, asr r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(iushr) +{ + POP r2 + rsb lr, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr lr, [locals, lr, lsl #2] + DISPATCH_NEXT + mov lr, r2, lsr lr + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH +} + +(iload,aload,fload)(iushr) { + ldrb r2, [jpc, #1] + DISPATCH_START \seq_len + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_NEXT + mov r2, r3, lsr r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(iand) +{ + POP tmp2 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + and tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(iload,aload,fload)(iand) { + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + POP tmp1 + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + and tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(ior) +{ + POP tmp2 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + orr tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(iload,aload,fload)(ior) { + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + POP tmp1 + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + orr tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(ixor) +{ + POP tmp2 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + eor tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(iload,aload,fload)(ixor) { + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + POP tmp1 + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + eor tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(iload_0,iload_1,iload_2,iload_3) +(i2c) +{ + rsb lr, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr lr, [locals, lr, lsl #2] + DISPATCH_NEXT + mov lr, lr, asl #16 + mov lr, lr, lsr #16 + PUSH lr + DISPATCH_FINISH +} + +(iload,aload,fload)(i2c) { + DISPATCH_START \seq_len + ldr r2, [locals, -r2, lsl #2] + DISPATCH_NEXT + mov r2, r2, asl #16 + mov r2, r2, lsr #16 + PUSH r2 + DISPATCH_FINISH +} + +# --- ECN: load; branch ------------------------------------------------------- + +(iload_0,iload_1,iload_2,iload_3) +(ifeq,ifnull) +{ + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + rsb r3, r0, #opc_iload_0 + add jpc, jpc, #1 + ldr r3, [locals, r3, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload,aload,fload)(ifeq,ifnull) { + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + add jpc, jpc, #2 + ldr r3, [locals, -r2, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload_0,iload_1,iload_2,iload_3) +(ifne,ifnonnull) +{ + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + rsb r3, r0, #opc_iload_0 + add jpc, jpc, #1 + ldr r3, [locals, r3, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload,aload,fload)(ifne,ifnonnull) { + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + add jpc, jpc, #2 + ldr r3, [locals, -r2, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload_0,iload_1,iload_2,iload_3) +(iflt) +{ + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + rsb r3, r0, #opc_iload_0 + add jpc, jpc, #1 + ldr r3, [locals, r3, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload,aload,fload)(iflt) { + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + add jpc, jpc, #2 + ldr r3, [locals, -r2, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload_0,iload_1,iload_2,iload_3) +(ifge) +{ + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + rsb r3, r0, #opc_iload_0 + add jpc, jpc, #1 + ldr r3, [locals, r3, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload,aload,fload)(ifge) { + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + add jpc, jpc, #2 + ldr r3, [locals, -r2, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload_0,iload_1,iload_2,iload_3) +(ifgt) +{ + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + rsb r3, r0, #opc_iload_0 + add jpc, jpc, #1 + ldr r3, [locals, r3, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload,aload,fload)(ifgt) { + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + add jpc, jpc, #2 + ldr r3, [locals, -r2, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload_0,iload_1,iload_2,iload_3) +(ifle) +{ + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + rsb r3, r0, #opc_iload_0 + add jpc, jpc, #1 + ldr r3, [locals, r3, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload,aload,fload)(ifle) { + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + add jpc, jpc, #2 + ldr r3, [locals, -r2, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload_0,iload_1,iload_2,iload_3) +(if_icmpeq,if_acmpeq) +{ + POP r3 + rsb r2, r0, #opc_iload_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + ldr r2, [locals, r2, lsl #2] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload,aload,fload)(if_icmpeq,if_acmpeq) { + POP r3 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + ldr r2, [locals, -r2, lsl #2] + add jpc, jpc, #2 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload_0,iload_1,iload_2,iload_3) +(if_icmpne,if_acmpne) +{ + POP r3 + rsb r2, r0, #opc_iload_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + ldr r2, [locals, r2, lsl #2] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload,aload,fload)(if_icmpne,if_acmpne) { + POP r3 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + ldr r2, [locals, -r2, lsl #2] + add jpc, jpc, #2 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload_0,iload_1,iload_2,iload_3) +(if_icmplt) +{ + POP r3 + rsb r2, r0, #opc_iload_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + ldr r2, [locals, r2, lsl #2] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload,aload,fload)(if_icmplt) { + POP r3 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + ldr r2, [locals, -r2, lsl #2] + add jpc, jpc, #2 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload_0,iload_1,iload_2,iload_3) +(if_icmpge) +{ + POP r3 + rsb r2, r0, #opc_iload_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + ldr r2, [locals, r2, lsl #2] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload,aload,fload)(if_icmpge) { + POP r3 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + ldr r2, [locals, -r2, lsl #2] + add jpc, jpc, #2 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload_0,iload_1,iload_2,iload_3) +(if_icmpgt) +{ + POP r3 + rsb r2, r0, #opc_iload_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + ldr r2, [locals, r2, lsl #2] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload,aload,fload)(if_icmpgt) { + POP r3 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + ldr r2, [locals, -r2, lsl #2] + add jpc, jpc, #2 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload_0,iload_1,iload_2,iload_3) +(if_icmple) +{ + POP r3 + rsb r2, r0, #opc_iload_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + ldr r2, [locals, r2, lsl #2] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload,aload,fload)(if_icmple) { + POP r3 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + ldr r2, [locals, -r2, lsl #2] + add jpc, jpc, #2 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +# --- ECN: load; return/invoke ------------------------------------------------- + +(iload_0,iload_1,iload_2,iload_3) +(ireturn,areturn,freturn) +{ + rsb r0, r0, #opc_iload_0 + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + ldr r1, [locals, r0, lsl #2] + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b +} + +(iload,aload,fload)(ireturn,areturn,freturn) { + + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + ldr r1, [locals, -r2, lsl #2] + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #2 + bl return_check_monitors + POP r1 + b 2b +} + +(iload_0,iload_1,iload_2,iload_3) +(invokeresolved) +{ + add jpc, jpc, #1 + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokeresolved +} + +(aload_0,aload_1,aload_2,aload_3) +(invokeresolved) +{ + add jpc, jpc, #1 + rsb r0, r0, #opc_aload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokeresolved +} + +(iload,aload,fload)(invokeresolved) { + ldr r0, [locals, -r2, lsl #2] + add jpc, jpc, #2 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokeresolved +} + +(iload_0,iload_1,iload_2,iload_3) +(invokevfinal) +{ + add jpc, jpc, #1 + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokevfinal +} + +(aload_0,aload_1,aload_2,aload_3) +(invokevfinal) +{ + add jpc, jpc, #1 + rsb r0, r0, #opc_aload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokevfinal +} + +(iload,aload,fload)(invokevfinal) { + ldr r0, [locals, -r2, lsl #2] + add jpc, jpc, #2 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokevfinal +} + +(iload_0,iload_1,iload_2,iload_3) +(invokespecialresolved) +{ + add jpc, jpc, #1 + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokespecialresolved +} + +(aload_0,aload_1,aload_2,aload_3) +(invokespecialresolved) +{ + add jpc, jpc, #1 + rsb r0, r0, #opc_aload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokespecialresolved +} + +(iload,aload,fload)(invokespecialresolved) { + ldr r0, [locals, -r2, lsl #2] + add jpc, jpc, #2 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokespecialresolved +} + +(iload_0,iload_1,iload_2,iload_3) +(invokestaticresolved) +{ + add jpc, jpc, #1 + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokestaticresolved +} + +(aload_0,aload_1,aload_2,aload_3) +(invokestaticresolved) +{ + add jpc, jpc, #1 + rsb r0, r0, #opc_aload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokestaticresolved +} + +(iload,aload,fload)(invokestaticresolved) { + ldr r0, [locals, -r2, lsl #2] + add jpc, jpc, #2 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokestaticresolved +} + +(iload_0,iload_1,iload_2,iload_3) +(invokeinterface) +{ + add jpc, jpc, #1 + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + PUSH r0 + b do_invokeinterface +} + +(aload_0,aload_1,aload_2,aload_3) +(invokeinterface) +{ + add jpc, jpc, #1 + rsb r0, r0, #opc_aload_0 + ldr r0, [locals, r0, lsl #2] + PUSH r0 + b do_invokeinterface +} + +(iload,aload,fload)(invokeinterface) { + ldr r0, [locals, -r2, lsl #2] + add jpc, jpc, #2 + PUSH r0 + b do_invokeinterface +} + +(aload_0,aload_1,aload_2,aload_3) +(igetfield) +{ + add r0, r0, #opc_iaccess_0-opc_aload_0 + strb r0, [jpc] + DISPATCH_BYTECODE +} + +# 13 cycles +(iload,aload,fload)(igetfield) { + ldrb ip, [jpc, #4] + rsb tmp1, r2, #0 + ldrb r3, [jpc, #3] + add tmp2, constpool, ip, lsl #12 + DISPATCH_START 5 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, r3, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + DISPATCH_NEXT + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry88: + ldr tmp2, [tmp1, tmp2] + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +# --- ECN: iconst; store ------------------------------------------------- + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5) +(istore_0,istore_1,istore_2,istore_3) +{ + sub r3, r0, #opc_iconst_0 + DISPATCH_START \seq_len + rsb r2, r1, #opc_istore_0 + str r3, [locals, r2, lsl #2] + DISPATCH_BYTECODE +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(astore,istore,fstore) { + ldrb r2, [jpc, #2] + sub r3, r0, #opc_iconst_0 + DISPATCH_START \seq_len + str r3, [locals, -r2, lsl #2] + DISPATCH_BYTECODE +} + +# --- ECN: iconst; dataop ------------------------------------------------- + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(iadd) { + sub tmp1, r0, #opc_iconst_0 + DISPATCH_START \seq_len + POP tmp2 + DISPATCH_NEXT + add tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(isub) { + sub tmp1, r0, #opc_iconst_0 + DISPATCH_START \seq_len + POP tmp2 + DISPATCH_NEXT + sub tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(idiv) { + subs lr, r0, #opc_iconst_2 + DISPATCH_START \seq_len + POP tmp1 + DISPATCH_NEXT + beq 5f + bcc 3f + cmp lr, #(opc_iconst_4-opc_iconst_2) + beq 4f + bcc 2f +@ divide by 5 +1: + mvn lr, #0x198 @ Form 0x66666667 in lr + bic lr, lr, #0x9800 + add lr, lr, lr, lsl #16 + smull a3, a4, tmp1, lr + mov a3, tmp1, asr #31 + rsb tmp1, a3, a4, asr #1 + b 6f +@ divide by 3 +2: + mvn lr, #0xa9 @ Form 0x55555556 in lr + bic lr, lr, #0xaa00 + add lr, lr, lr, lsl #16 + smull a3, a4, tmp1, lr + sub tmp1, a4, tmp1, asr #31 + b 6f +3: + cmp lr, #(opc_iconst_0-opc_iconst_2) + beq .iconst_div_rem_0 + rsbcc tmp1, tmp1, #0 @ Divide by -1 or 1 + b 6f +@ divide by 4 +4: movs a4, tmp1 + addmi a4, a4, #3 + mov tmp1, a4, asr #2 + b 6f +@ divide by 2 +5: + add tmp1, tmp1, tmp1, lsr #31 + mov tmp1, tmp1, asr #1 +6: + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(ishl) { + sub tmp1, r0, #opc_iconst_0 + DISPATCH_START \seq_len + POP r2 + DISPATCH_NEXT + mov tmp1, r2, lsl tmp1 + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +# --- ECN: iconst; branch ------------------------------------------------- + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(if_icmpeq) { + POP r3 + sub r2, r0, #opc_iconst_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(if_icmpne) { + POP r3 + sub r2, r0, #opc_iconst_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(if_icmplt) { + POP r3 + sub r2, r0, #opc_iconst_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(if_icmpge) { + POP r3 + sub r2, r0, #opc_iconst_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(if_icmpgt) { + POP r3 + sub r2, r0, #opc_iconst_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(if_icmple) { + POP r3 + sub r2, r0, #opc_iconst_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(ireturn) { + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + sub r1, r0, #opc_iconst_0 + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(invokeresolved) { + add jpc, jpc, #1 + sub r0, r0, #opc_iconst_0 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokeresolved +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(invokevfinal) { + add jpc, jpc, #1 + sub r0, r0, #opc_iconst_0 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokevfinal +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(invokestaticresolved) { + add jpc, jpc, #1 + sub r0, r0, #opc_iconst_0 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokestaticresolved +} + +(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5)(invokespecialresolved) { + add jpc, jpc, #1 + sub r0, r0, #opc_iconst_0 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokespecialresolved +} + +## --- Bytecode sequences iaload; xxx ----------------------------------------------- + +(iaload,faload,aaload)(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5) { + sub r2, r1, #opc_iconst_0 + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry38: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(iaload,faload,aaload)(bipush) { + ldrsb r2, [jpc, #2] + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_3 +#endif +.abortentry39: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_3_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(iaload,faload,aaload)(sipush) { + ldrsb r2, [jpc, #2] + ldrb tmp1, [jpc, #3] + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len + orr r2, tmp1, r2, lsl #8 +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_4 +#endif +.abortentry40: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_4_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(iaload,faload,aaload)(iload,fload,aload) { + ldrb r2, [jpc, #2] + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len + ldr r2, [locals, -r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_3 +#endif +.abortentry41: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_3_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(iaload,faload,aaload) +(iload_0,iload_1,iload_2,iload_3) +{ + rsb r2, r1, #opc_iload_0 + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len + ldr r2, [locals, r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry42: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(iaload,faload,aaload) +(aload_0,aload_1,aload_2,aload_3) +{ + rsb r2, r1, #opc_aload_0 + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len + ldr r2, [locals, r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry42_1: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH +} + +(iaload,faload,aaload)(iaload,faload,aaload) +{ + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry43: + ldr tmp1, [r3, #8] @ tmp1 = length + DISPATCH_START \seq_len + cmp r2, tmp1 + bcs array_bound_exception_jpc_2 + add r3, r3, r2, lsl #2 + POP lr @ r2 = index, lr = arrayref + ldr r2, [r3, #12] +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry44: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_1 + add lr, lr, r2, lsl #2 + ldr r2, [lr, #12] + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(iaload,faload,aaload)(astore,istore,fstore) { + ldrb r2, [jpc, #2] + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_3 +#endif +.abortentry45: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_3_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + str r3, [locals, -r2, lsl #2] + DISPATCH_FINISH +} + +(iaload,faload,aaload) +(istore_0,istore_1,istore_2,istore_3) { + rsb r2, r1, #opc_istore_0 + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry46: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + str r3, [locals, r2, lsl #2] + DISPATCH_FINISH +} + +(iaload,faload,aaload)(iastore,fastore) { + POP2 r3, lr @ r3 = index, lr = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry47: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_START \seq_len + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr tmp1, [lr, #12] + + POP2 r2, r3 @ tmp1 = value, r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry48: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH +} + +(iaload,faload,aaload)(bastore) { + POP2 r3, lr @ r3 = index, lr = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry49: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_START \seq_len + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr tmp1, [lr, #12] + + POP2 r2, r3 @ tmp1 = value, r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry50: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2 + strb tmp1, [r3, #12] + DISPATCH_FINISH +} + +(iaload,faload,aaload)(castore,sastore) { + POP2 r3, lr @ r3 = index, lr = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry51: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_START \seq_len + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr tmp1, [lr, #12] + + POP2 r2, r3 @ tmp1 = value, r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry52: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #1 + strh tmp1, [r3, #12] + DISPATCH_FINISH +} + +(iaload,faload,aaload)(iand) { + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry58: + ldr tmp1, [r3, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_2 + add r3, r3, r2, lsl #2 + ldr tmp1, [r3, #12] @ tmp1 = tos + POP r2 @ r2 = tosm1 + DISPATCH_NEXT + and tmp1, r2, tmp1 @ tosm1 <dop> tos + PUSH tmp1 + DISPATCH_FINISH +} + +(iaload,faload,aaload)(ior) { + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry59: + ldr tmp1, [r3, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_2 + add r3, r3, r2, lsl #2 + ldr tmp1, [r3, #12] @ tmp1 = tos + POP r2 @ r2 = tosm1 + DISPATCH_NEXT + orr tmp1, r2, tmp1 @ tosm1 <dop> tos + PUSH tmp1 + DISPATCH_FINISH +} + +(iaload,faload,aaload)(ixor) { + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry60: + ldr tmp1, [r3, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_2 + add r3, r3, r2, lsl #2 + ldr tmp1, [r3, #12] @ tmp1 = tos + POP r2 @ r2 = tosm1 + DISPATCH_NEXT + eor tmp1, r2, tmp1 @ tosm1 <dop> tos + PUSH tmp1 + DISPATCH_FINISH +} + +(iaload,faload,aaload)(ifeq,ifnull) { + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry61: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r3, [r3, #12] @ r1 = tos + + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaload,faload,aaload)(ifne,ifnonnull) { + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry62: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r3, [r3, #12] @ r1 = tos + + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaload,faload,aaload)(iflt) { + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry63: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r3, [r3, #12] @ r1 = tos + + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaload,faload,aaload)(ifge) { + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry64: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r3, [r3, #12] @ r1 = tos + + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaload,faload,aaload)(ifgt) { + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry65: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r3, [r3, #12] @ r1 = tos + + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaload,faload,aaload)(ifle) { + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry66: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r3, [r3, #12] @ r1 = tos + + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaload,faload,aaload)(if_icmpeq,if_acmpeq) { + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry67: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r2, [r3, #12] @ r1 = tos + + POP r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaload,faload,aaload)(if_icmpne,if_acmpne) { + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry68: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r2, [r3, #12] @ r1 = tos + + POP r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaload,faload,aaload)(if_icmplt) { + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry69: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r2, [r3, #12] @ r1 = tos + + POP r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaload,faload,aaload)(if_icmpge) { + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry70: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r2, [r3, #12] @ r1 = tos + + POP r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaload,faload,aaload)(if_icmpgt) { + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry71: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r2, [r3, #12] @ r1 = tos + + POP r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaload,faload,aaload)(if_icmple) { + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry72: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r2, [r3, #12] @ r1 = tos + + POP r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +# ---- iadd; xxx ------------------------------------------------------------ + +(iadd)(iload,fload,aload) { + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +} + +(iadd) +(iload_0,iload_1,iload_2,iload_3) +{ + DISPATCH_START \seq_len + rsb r3, r1, #opc_iload_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +} + +(iadd)(iaload,aaload,faload) { + POP3 r2, r3, lr @ lr = ref + DISPATCH_START \seq_len + add r2, r3, r2 @ r2 = index +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry73: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_1 + add lr, lr, r2, lsl #2 + ldr tmp1, [lr, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(iadd)(istore) { + mov r0, #opc_iadd_u4store + strb r0, [jpc] + b do_iadd_u4store +} + +(iadd) +(istore_0,istore_1,istore_2,istore_3) { + mov r0, #opc_iadd_istore_N + strb r0, [jpc] + b do_iadd_istore_N +} + +(iadd)(iastore,fastore) { + POP2 r2, r3 + DISPATCH_START \seq_len + add tmp1, r3, r2 @ tmp1 = value + POP2 r2, r3 @ r2, index, r3 = ref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry106: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH +} + +(iadd)(iadd) { + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + add tmp2, r3, r2 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(iadd)(isub) { + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + add tmp2, r3, r2 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(iadd)(ifeq,ifnull) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iadd)(ifne,ifnonnull) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iadd)(iflt) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iadd)(ifge) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iadd)(ifgt) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iadd)(ifle) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iadd)(if_icmpeq,if_acmpeq) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iadd)(if_icmpne,if_acmpne) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iadd)(if_icmplt) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iadd)(if_icmpge) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iadd)(if_icmpgt) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iadd)(if_icmple) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iadd)(goto) { + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + orr ip, ip, r1, lsl #8 + DISPATCH_START_REG ip + POP2 r2, r3 + add r2, r3, r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(iadd)(ireturn) { + POP2 r2, r3 + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + add r1, r3, r2 + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b +} + +(iadd)(iinc) { + POP2 tmp1, lr + DISPATCH_START \seq_len + add tmp1, lr, tmp1 + ldrb r3, [jpc, #-2] @ ECN: jpc now points to next bc + ldrsb r2, [jpc, #-1] + DISPATCH_NEXT + PUSH tmp1 + ldr tmp1, [locals, -r3, lsl #2] + DISPATCH_NEXT + add tmp1, tmp1, r2 + str tmp1, [locals, -r3, lsl #2] + DISPATCH_FINISH +} +# ---- sub; xxx ------------------------------------------------------------ + +(isub)(iload,fload,aload) { + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +} + +(isub) +(iload_0,iload_1,iload_2,iload_3) +{ + DISPATCH_START \seq_len + rsb r3, r1, #opc_iload_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +} + +(isub)(iaload,aaload,faload) { + POP3 r2, r3, lr @ lr = ref + DISPATCH_START \seq_len + sub r2, r3, r2 @ r2 = index +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry74: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_1 + add lr, lr, r2, lsl #2 + ldr tmp1, [lr, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(isub)(istore) { + mov r0, #opc_isub_u4store + strb r0, [jpc] + b do_isub_u4store +} + +(isub) +(istore_0,istore_1,istore_2,istore_3) { + mov r0, #opc_isub_istore_N + strb r0, [jpc] + b do_isub_istore_N +} + +(isub)(iastore,fastore) { + POP2 r2, r3 + DISPATCH_START \seq_len + sub tmp1, r3, r2 @ tmp1 = value + POP2 r2, r3 @ r2, index, r3 = ref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry105: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH +} + +(isub)(iadd) { + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + sub tmp2, r3, r2 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(isub)(isub) { + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + sub tmp2, r3, r2 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(isub)(ifeq,ifnull) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(isub)(ifne,ifnonnull) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(isub)(iflt) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(isub)(ifge) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(isub)(ifgt) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(isub)(ifle) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(isub)(if_icmpeq,if_acmpeq) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(isub)(if_icmpne,if_acmpne) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(isub)(if_icmplt) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(isub)(if_icmpge) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(isub)(if_icmpgt) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(isub)(if_icmple) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(isub)(goto) { + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + orr ip, ip, r1, lsl #8 + DISPATCH_START_REG ip + POP2 r2, r3 + sub r2, r3, r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(isub)(ireturn) { + POP2 r2, r3 + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + sub r1, r3, r2 + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b +} + +(isub)(iinc) { + POP2 tmp1, lr + DISPATCH_START \seq_len + sub tmp1, lr, tmp1 + ldrb r3, [jpc, #-2] @ ECN: jpc now points to next bc + ldrsb r2, [jpc, #-1] + DISPATCH_NEXT + PUSH tmp1 + ldr tmp1, [locals, -r3, lsl #2] + DISPATCH_NEXT + add tmp1, tmp1, r2 + str tmp1, [locals, -r3, lsl #2] + DISPATCH_FINISH +} +# ---- iand; xxx ------------------------------------------------------------ + +(iand)(iload,fload,aload) { + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + and tmp2, tmp1, tmp2 + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +} + +(iand) +(iload_0,iload_1,iload_2,iload_3) +{ + DISPATCH_START \seq_len + rsb r3, r1, #opc_iload_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + and tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +} + +(iand)(iaload,aaload,faload) { + POP3 r2, r3, lr @ lr = ref + DISPATCH_START \seq_len + and r2, r3, r2 @ r2 = index +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry75: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_1 + add lr, lr, r2, lsl #2 + ldr tmp1, [lr, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(iand)(istore) { + mov r0, #opc_iand_u4store + strb r0, [jpc] + b do_iand_u4store +} + +(iand) +(istore_0,istore_1,istore_2,istore_3) { + mov r0, #opc_iand_istore_N + strb r0, [jpc] + b do_iand_istore_N +} + +(iand)(iastore,fastore) { + POP2 r2, r3 + DISPATCH_START \seq_len + and tmp1, r3, r2 @ tmp1 = value + POP2 r2, r3 @ r2, index, r3 = ref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry107: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH +} + +(iand)(iadd) { + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + and tmp2, r3, r2 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(iand)(isub) { + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + and tmp2, r3, r2 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(iand)(ifeq,ifnull) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iand)(ifne,ifnonnull) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iand)(iflt) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iand)(ifge) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iand)(ifgt) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iand)(ifle) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iand)(if_icmpeq,if_acmpeq) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iand)(if_icmpne,if_acmpne) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iand)(if_icmplt) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iand)(if_icmpge) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iand)(if_icmpgt) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iand)(if_icmple) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iand)(goto) { + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + orr ip, ip, r1, lsl #8 + DISPATCH_START_REG ip + POP2 r2, r3 + and r2, r3, r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(iand)(ireturn) { + POP2 r2, r3 + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + and r1, r3, r2 + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b +} + +(iand)(iinc) { + POP2 tmp1, lr + DISPATCH_START \seq_len + and tmp1, lr, tmp1 + ldrb r3, [jpc, #-2] @ ECN: jpc now points to next bc + ldrsb r2, [jpc, #-1] + DISPATCH_NEXT + PUSH tmp1 + ldr tmp1, [locals, -r3, lsl #2] + DISPATCH_NEXT + add tmp1, tmp1, r2 + str tmp1, [locals, -r3, lsl #2] + DISPATCH_FINISH +} +# ---- ior; xxx ------------------------------------------------------------ + +(ior)(iload,fload,aload) { + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + orr tmp2, tmp1, tmp2 + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +} + +(ior) +(iload_0,iload_1,iload_2,iload_3) +{ + DISPATCH_START \seq_len + rsb r3, r1, #opc_iload_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + orr tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +} + +(ior)(iaload,aaload,faload) { + POP3 r2, r3, lr @ lr = ref + DISPATCH_START \seq_len + orr r2, r3, r2 @ r2 = index +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry76: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_1 + add lr, lr, r2, lsl #2 + ldr tmp1, [lr, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(ior)(istore) { + mov r0, #opc_ior_u4store + strb r0, [jpc] + b do_ior_u4store +} + +(ior) +(istore_0,istore_1,istore_2,istore_3) { + mov r0, #opc_ior_istore_N + strb r0, [jpc] + b do_ior_istore_N +} + +(ior)(iastore,fastore) { + POP2 r2, r3 + DISPATCH_START \seq_len + orr tmp1, r3, r2 @ tmp1 = value + POP2 r2, r3 @ r2, index, r3 = ref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry108: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH +} + +(ior)(iadd) { + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + orr tmp2, r3, r2 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(ior)(isub) { + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + orr tmp2, r3, r2 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(ior)(ifeq,ifnull) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ior)(ifne,ifnonnull) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ior)(iflt) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ior)(ifge) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ior)(ifgt) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ior)(ifle) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ior)(if_icmpeq,if_acmpeq) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ior)(if_icmpne,if_acmpne) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ior)(if_icmplt) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ior)(if_icmpge) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ior)(if_icmpgt) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ior)(if_icmple) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ior)(goto) { + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + orr ip, ip, r1, lsl #8 + DISPATCH_START_REG ip + POP2 r2, r3 + orr r2, r3, r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(ior)(ireturn) { + POP2 r2, r3 + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + orr r1, r3, r2 + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b +} + +(ior)(iinc) { + POP2 tmp1, lr + DISPATCH_START \seq_len + orr tmp1, lr, tmp1 + ldrb r3, [jpc, #-2] @ ECN: jpc now points to next bc + ldrsb r2, [jpc, #-1] + DISPATCH_NEXT + PUSH tmp1 + ldr tmp1, [locals, -r3, lsl #2] + DISPATCH_NEXT + add tmp1, tmp1, r2 + str tmp1, [locals, -r3, lsl #2] + DISPATCH_FINISH +} + +# ---- ixor; xxx ------------------------------------------------------------ + +(ixor)(iload,fload,aload) { + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + eor tmp2, tmp1, tmp2 + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +} + +(ixor) +(iload_0,iload_1,iload_2,iload_3) +{ + DISPATCH_START \seq_len + rsb r3, r1, #opc_iload_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + eor tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +} + +(ixor)(iaload,aaload,faload) { + POP3 r2, r3, lr @ lr = ref + DISPATCH_START \seq_len + eor r2, r3, r2 @ r2 = index +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry77: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_1 + add lr, lr, r2, lsl #2 + ldr tmp1, [lr, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(ixor)(istore) { + mov r0, #opc_ixor_u4store + strb r0, [jpc] + b do_ixor_u4store +} + +(ixor) +(istore_0,istore_1,istore_2,istore_3) { + mov r0, #opc_ixor_istore_N + strb r0, [jpc] + b do_ixor_istore_N +} + +(ixor)(iastore,fastore) { + POP2 r2, r3 + DISPATCH_START \seq_len + eor tmp1, r3, r2 @ tmp1 = value + POP2 r2, r3 @ r2, index, r3 = ref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry109: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH +} + +(ixor)(iadd) { + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + eor tmp2, r3, r2 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(ixor)(isub) { + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + eor tmp2, r3, r2 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +} + +(ixor)(ifeq,ifnull) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ixor)(ifne,ifnonnull) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ixor)(iflt) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ixor)(ifge) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ixor)(ifgt) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ixor)(ifle) { + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ixor)(if_icmpeq,if_acmpeq) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ixor)(if_icmpne,if_acmpne) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ixor)(if_icmplt) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ixor)(if_icmpge) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ixor)(if_icmpgt) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ixor)(if_icmple) { + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(ixor)(goto) { + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + orr ip, ip, r1, lsl #8 + DISPATCH_START_REG ip + POP2 r2, r3 + eor r2, r3, r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH +} + +(ixor)(ireturn) { + POP2 r2, r3 + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + eor r1, r3, r2 + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b +} + +(ixor)(iinc) { + POP2 tmp1, lr + DISPATCH_START \seq_len + eor tmp1, lr, tmp1 + ldrb r3, [jpc, #-2] @ ECN: jpc now points to next bc + ldrsb r2, [jpc, #-1] + DISPATCH_NEXT + PUSH tmp1 + ldr tmp1, [locals, -r3, lsl #2] + DISPATCH_NEXT + add tmp1, tmp1, r2 + str tmp1, [locals, -r3, lsl #2] + DISPATCH_FINISH +} + +# --- iinc; xxx -------------------------------------------------------------- + +(iinc)(iconst_m1,iconst_0,iconst_1,iconst_2,iconst_3,iconst_4,iconst_5) { + ldrsb tmp1, [jpc, #2] + sub lr, r1, #opc_iconst_0 + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + ldr r3, [locals, tmp2, lsl #2] + DISPATCH_NEXT + add r3, r3, tmp1 + DISPATCH_NEXT + PUSH lr + DISPATCH_NEXT + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +(iinc)(iload,aload,fload) { + ldrb lr, [jpc, #4] + ldrsb tmp1, [jpc, #2] + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + ldr r3, [locals, tmp2, lsl #2] + DISPATCH_NEXT + rsb lr, lr, #0 + DISPATCH_NEXT + add r3, r3, tmp1 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + ldr tmp1, [locals, lr, lsl #2] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +(iinc) +(iload_0,iload_1,iload_2,iload_3) +{ + rsb lr, r1, #opc_iload_0 + ldrsb tmp1, [jpc, #2] + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + ldr r3, [locals, tmp2, lsl #2] + DISPATCH_NEXT + add r3, r3, tmp1 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_NEXT + ldr tmp1, [locals, lr, lsl #2] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH +} + +################################################################################ +## ECN: Optimised bytecode triples +################################################################################ + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(iload,fload,aload) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb r3, [jpc, #2] + add tmp2, constpool, r2, lsl #12 + DISPATCH_START 6 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, r3, lsl #4 + ldrb r3, [jpc, #-1] + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_5 +#endif + DISPATCH_NEXT + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + rsb r3, r3, #0 +.abortentry89: + ldr tmp2, [tmp1, tmp2] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(iload_0,iload_1,iload_2,iload_3) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add tmp2, constpool, r2, lsl #12 + DISPATCH_START 5 + rsb r3, r1, #opc_iload_0 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_4 +#endif + DISPATCH_NEXT + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry90: + ldr tmp2, [tmp1, tmp2] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(iadd) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add tmp2, constpool, r2, lsl #12 + DISPATCH_START 5 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_4 +#endif + DISPATCH_NEXT + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + POP r3 +.abortentry91: + ldr tmp2, [tmp1, tmp2] + DISPATCH_NEXT + add tmp2, tmp2, r3 + PUSH tmp2 + DISPATCH_FINISH +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(ifeq,ifnull) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + orr ip, ip, r0, lsl #8 +.abortentry92: + ldr tmp2, [tmp1, tmp2] + cmp tmp2, #0 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(ifne,ifnonnull) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + orr ip, ip, r0, lsl #8 +.abortentry93: + ldr tmp2, [tmp1, tmp2] + cmp tmp2, #0 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(iflt) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + orr ip, ip, r0, lsl #8 +.abortentry94: + ldr tmp2, [tmp1, tmp2] + cmp tmp2, #0 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(ifge) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + orr ip, ip, r0, lsl #8 +.abortentry95: + ldr tmp2, [tmp1, tmp2] + cmp tmp2, #0 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(ifgt) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + orr ip, ip, r0, lsl #8 +.abortentry96: + ldr tmp2, [tmp1, tmp2] + cmp tmp2, #0 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(ifle) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + orr ip, ip, r0, lsl #8 +.abortentry97: + ldr tmp2, [tmp1, tmp2] + cmp tmp2, #0 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(if_icmpeq,if_acmpeq) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + POP r3 + orr ip, ip, r0, lsl #8 +.abortentry98: + ldr tmp2, [tmp1, tmp2] + cmp r3, tmp2 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(if_icmpne,if_acmpne) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + POP r3 + orr ip, ip, r0, lsl #8 +.abortentry99: + ldr tmp2, [tmp1, tmp2] + cmp r3, tmp2 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(if_icmplt) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + POP r3 + orr ip, ip, r0, lsl #8 +.abortentry100: + ldr tmp2, [tmp1, tmp2] + cmp r3, tmp2 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(if_icmpge) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + POP r3 + orr ip, ip, r0, lsl #8 +.abortentry101: + ldr tmp2, [tmp1, tmp2] + cmp r3, tmp2 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(if_icmpgt) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + POP r3 + orr ip, ip, r0, lsl #8 +.abortentry102: + ldr tmp2, [tmp1, tmp2] + cmp r3, tmp2 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iaccess_0,iaccess_1,iaccess_2,iaccess_3) +(if_icmple) { + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + POP r3 + orr ip, ip, r0, lsl #8 +.abortentry103: + ldr tmp2, [tmp1, tmp2] + cmp r3, tmp2 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(iadd) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + ldrb r2, [jpc, #1-\seq_len] + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp1, r2, #opc_iconst_0 + DISPATCH_NEXT + add r3, r3, tmp1 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(isub) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + ldrb r2, [jpc, #1-\seq_len] + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp1, r2, #opc_iconst_0 + DISPATCH_NEXT + sub r3, r3, tmp1 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(iand) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + ldrb r2, [jpc, #1-\seq_len] + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp1, r2, #opc_iconst_0 + DISPATCH_NEXT + and r3, r3, tmp1 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(ior) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + ldrb r2, [jpc, #1-\seq_len] + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp1, r2, #opc_iconst_0 + DISPATCH_NEXT + orr r3, r3, tmp1 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(ixor) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + ldrb r2, [jpc, #1-\seq_len] + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp1, r2, #opc_iconst_0 + DISPATCH_NEXT + eor r3, r3, tmp1 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload_iconst_N) +(iadd) +{ + ldrb r3, [jpc, #2] + rsb r2, r2, #0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr r2, [locals, r2, lsl #2] + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + add r3, r2, r3 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload_iconst_N) +(isub) +{ + ldrb r3, [jpc, #2] + rsb r2, r2, #0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr r2, [locals, r2, lsl #2] + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + sub r3, r2, r3 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload_iconst_N) +(iand) +{ + ldrb r3, [jpc, #2] + rsb r2, r2, #0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr r2, [locals, r2, lsl #2] + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + and r3, r2, r3 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload_iconst_N) +(ior) +{ + ldrb r3, [jpc, #2] + rsb r2, r2, #0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr r2, [locals, r2, lsl #2] + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + orr r3, r2, r3 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +# r2 = [jpc, #1] +(iload_iconst_N) +(ixor) +{ + ldrb r3, [jpc, #2] + rsb r2, r2, #0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr r2, [locals, r2, lsl #2] + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + eor r3, r2, r3 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH +} + +# Former quads + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(iadd_u4store) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + add r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +(iload_iconst_N) +(iadd_u4store) +{ + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #5] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + add r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(iadd_istore_N) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + add r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #opc_istore_0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +(iload_iconst_N) +(iadd_istore_N) +{ + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #4] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #opc_istore_0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + add r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(isub_u4store) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +(iload_iconst_N) +(isub_u4store) +{ + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #5] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + sub r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(isub_istore_N) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #opc_istore_0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +(iload_iconst_N) +(isub_istore_N) +{ + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #4] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #opc_istore_0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + sub r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(iand_u4store) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + and r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +(iload_iconst_N) +(iand_u4store) +{ + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #5] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + and r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(iand_istore_N) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + and r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #opc_istore_0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +(iload_iconst_N) +(iand_istore_N) +{ + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #4] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #opc_istore_0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + and r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(ior_u4store) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + orr r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +(iload_iconst_N) +(ior_u4store) +{ + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #5] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + orr r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(ior_istore_N) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + orr r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #opc_istore_0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +(iload_iconst_N) +(ior_istore_N) +{ + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #4] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #opc_istore_0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + orr r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(ixor_u4store) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + eor r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +(iload_iconst_N) +(ixor_u4store) +{ + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #5] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + eor r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH +} + +(iload_0_iconst_N,iload_1_iconst_N,iload_2_iconst_N,iload_3_iconst_N) +(ixor_istore_N) +{ + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + eor r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #opc_istore_0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH +} + +(iload_iconst_N) +(ixor_istore_N) +{ + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #4] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #opc_istore_0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + eor r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ports/hotspot/src/cpu/zero/vm/bytecodes.s Fri Aug 21 13:35:04 2009 +0200 @@ -0,0 +1,12797 @@ +#define opc_nop 0x00 +#define opc_aconst_null 0x01 +#define opc_iconst_m1 0x02 +#define opc_iconst_0 0x03 +#define opc_iconst_1 0x04 +#define opc_iconst_2 0x05 +#define opc_iconst_3 0x06 +#define opc_iconst_4 0x07 +#define opc_iconst_5 0x08 +#define opc_lconst_0 0x09 +#define opc_lconst_1 0x0a +#define opc_fconst_0 0x0b +#define opc_fconst_1 0x0c +#define opc_fconst_2 0x0d +#define opc_dconst_0 0x0e +#define opc_dconst_1 0x0f +#define opc_bipush 0x10 +#define opc_sipush 0x11 +#define opc_ldc 0x12 +#define opc_ldc_w 0x13 +#define opc_ldc2_w 0x14 +#define opc_iload 0x15 +#define opc_lload 0x16 +#define opc_fload 0x17 +#define opc_dload 0x18 +#define opc_aload 0x19 +#define opc_iload_0 0x1a +#define opc_iload_1 0x1b +#define opc_iload_2 0x1c +#define opc_iload_3 0x1d +#define opc_lload_0 0x1e +#define opc_lload_1 0x1f +#define opc_lload_2 0x20 +#define opc_lload_3 0x21 +#define opc_fload_0 0x22 +#define opc_fload_1 0x23 +#define opc_fload_2 0x24 +#define opc_fload_3 0x25 +#define opc_dload_0 0x26 +#define opc_dload_1 0x27 +#define opc_dload_2 0x28 +#define opc_dload_3 0x29 +#define opc_aload_0 0x2a +#define opc_aload_1 0x2b +#define opc_aload_2 0x2c +#define opc_aload_3 0x2d +#define opc_iaload 0x2e +#define opc_laload 0x2f +#define opc_faload 0x30 +#define opc_daload 0x31 +#define opc_aaload 0x32 +#define opc_baload 0x33 +#define opc_caload 0x34 +#define opc_saload 0x35 +#define opc_istore 0x36 +#define opc_lstore 0x37 +#define opc_fstore 0x38 +#define opc_dstore 0x39 +#define opc_astore 0x3a +#define opc_istore_0 0x3b +#define opc_istore_1 0x3c +#define opc_istore_2 0x3d +#define opc_istore_3 0x3e +#define opc_lstore_0 0x3f +#define opc_lstore_1 0x40 +#define opc_lstore_2 0x41 +#define opc_lstore_3 0x42 +#define opc_fstore_0 0x43 +#define opc_fstore_1 0x44 +#define opc_fstore_2 0x45 +#define opc_fstore_3 0x46 +#define opc_dstore_0 0x47 +#define opc_dstore_1 0x48 +#define opc_dstore_2 0x49 +#define opc_dstore_3 0x4a +#define opc_astore_0 0x4b +#define opc_astore_1 0x4c +#define opc_astore_2 0x4d +#define opc_astore_3 0x4e +#define opc_iastore 0x4f +#define opc_lastore 0x50 +#define opc_fastore 0x51 +#define opc_dastore 0x52 +#define opc_aastore 0x53 +#define opc_bastore 0x54 +#define opc_castore 0x55 +#define opc_sastore 0x56 +#define opc_pop 0x57 +#define opc_pop2 0x58 +#define opc_dup 0x59 +#define opc_dup_x1 0x5a +#define opc_dup_x2 0x5b +#define opc_dup2 0x5c +#define opc_dup2_x1 0x5d +#define opc_dup2_x2 0x5e +#define opc_swap 0x5f +#define opc_iadd 0x60 +#define opc_ladd 0x61 +#define opc_fadd 0x62 +#define opc_dadd 0x63 +#define opc_isub 0x64 +#define opc_lsub 0x65 +#define opc_fsub 0x66 +#define opc_dsub 0x67 +#define opc_imul 0x68 +#define opc_lmul 0x69 +#define opc_fmul 0x6a +#define opc_dmul 0x6b +#define opc_idiv 0x6c +#define opc_ldiv 0x6d +#define opc_fdiv 0x6e +#define opc_ddiv 0x6f +#define opc_irem 0x70 +#define opc_lrem 0x71 +#define opc_frem 0x72 +#define opc_drem 0x73 +#define opc_ineg 0x74 +#define opc_lneg 0x75 +#define opc_fneg 0x76 +#define opc_dneg 0x77 +#define opc_ishl 0x78 +#define opc_lshl 0x79 +#define opc_ishr 0x7a +#define opc_lshr 0x7b +#define opc_iushr 0x7c +#define opc_lushr 0x7d +#define opc_iand 0x7e +#define opc_land 0x7f +#define opc_ior 0x80 +#define opc_lor 0x81 +#define opc_ixor 0x82 +#define opc_lxor 0x83 +#define opc_iinc 0x84 +#define opc_i2l 0x85 +#define opc_i2f 0x86 +#define opc_i2d 0x87 +#define opc_l2i 0x88 +#define opc_l2f 0x89 +#define opc_l2d 0x8a +#define opc_f2i 0x8b +#define opc_f2l 0x8c +#define opc_f2d 0x8d +#define opc_d2i 0x8e +#define opc_d2l 0x8f +#define opc_d2f 0x90 +#define opc_i2b 0x91 +#define opc_i2c 0x92 +#define opc_i2s 0x93 +#define opc_lcmp 0x94 +#define opc_fcmpl 0x95 +#define opc_fcmpg 0x96 +#define opc_dcmpl 0x97 +#define opc_dcmpg 0x98 +#define opc_ifeq 0x99 +#define opc_ifne 0x9a +#define opc_iflt 0x9b +#define opc_ifge 0x9c +#define opc_ifgt 0x9d +#define opc_ifle 0x9e +#define opc_if_icmpeq 0x9f +#define opc_if_icmpne 0xa0 +#define opc_if_icmplt 0xa1 +#define opc_if_icmpge 0xa2 +#define opc_if_icmpgt 0xa3 +#define opc_if_icmple 0xa4 +#define opc_if_acmpeq 0xa5 +#define opc_if_acmpne 0xa6 +#define opc_goto 0xa7 +#define opc_jsr 0xa8 +#define opc_ret 0xa9 +#define opc_tableswitch 0xaa +#define opc_lookupswitch 0xab +#define opc_ireturn 0xac +#define opc_lreturn 0xad +#define opc_freturn 0xae +#define opc_dreturn 0xaf +#define opc_areturn 0xb0 +#define opc_return 0xb1 +#define opc_getstatic 0xb2 +#define opc_putstatic 0xb3 +#define opc_getfield 0xb4 +#define opc_putfield 0xb5 +#define opc_invokevirtual 0xb6 +#define opc_invokespecial 0xb7 +#define opc_invokestatic 0xb8 +#define opc_invokeinterface 0xb9 +#define opc_new 0xbb +#define opc_newarray 0xbc +#define opc_anewarray 0xbd +#define opc_arraylength 0xbe +#define opc_athrow 0xbf +#define opc_checkcast 0xc0 +#define opc_instanceof 0xc1 +#define opc_monitorenter 0xc2 +#define opc_monitorexit 0xc3 +#define opc_wide 0xc4 +#define opc_multianewarray 0xc5 +#define opc_ifnull 0xc6 +#define opc_ifnonnull 0xc7 +#define opc_goto_w 0xc8 +#define opc_jsr_w 0xc9 +#define opc_breakpoint 0xca +#define opc_bgetfield 0xcc +#define opc_cgetfield 0xcd +#define opc_igetfield 0xd0 +#define opc_lgetfield 0xd1 +#define opc_sgetfield 0xd2 +#define opc_aputfield 0xd3 +#define opc_bputfield 0xd4 +#define opc_cputfield 0xd5 +#define opc_iputfield 0xd8 +#define opc_lputfield 0xd9 +#define opc_iaccess_0 0xdb +#define opc_iaccess_1 0xdc +#define opc_iaccess_2 0xdd +#define opc_iaccess_3 0xde +#define opc_invokevfinal 0xe2 +#define opc_return_register_finalizer 0xe5 +#define opc_iload_0_iconst_N 0xe7 +#define opc_iload_1_iconst_N 0xe8 +#define opc_iload_2_iconst_N 0xe9 +#define opc_iload_3_iconst_N 0xea +#define opc_iload_iconst_N 0xeb +#define opc_invokeresolved 0xec +#define opc_iadd_istore_N 0xed +#define opc_isub_istore_N 0xee +#define opc_iand_istore_N 0xef +#define opc_ior_istore_N 0xf0 +#define opc_ixor_istore_N 0xf1 +#define opc_iadd_u4store 0xf2 +#define opc_isub_u4store 0xf3 +#define opc_iand_u4store 0xf4 +#define opc_ior_u4store 0xf5 +#define opc_ixor_u4store 0xf6 +#define opc_invokespecialresolved 0xf7 +#define opc_invokestaticresolved 0xf8 + +@----------------------------------------------------------------------------- + .macro nop jpc_off=0, seq_len=1 + DISPATCH \seq_len + .endm + + Opcode nop + nop +@----------------------------------------------------------------------------- + .macro u4const_0 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + mov lr, #0 + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode u4const_0 + u4const_0 +@----------------------------------------------------------------------------- + .macro iconst_N jpc_off=0, seq_len=1 + sub lr, r0, #opc_iconst_0 + DISPATCH_START \seq_len + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iconst_N + iconst_N +@----------------------------------------------------------------------------- + .macro u8const_0 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + mov tmp1, #0 + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode u8const_0 + u8const_0 +@----------------------------------------------------------------------------- + .macro lconst_1 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + mov tmp2, #1 + DISPATCH_NEXT + mov tmp1, #0 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode lconst_1 + lconst_1 +@----------------------------------------------------------------------------- + .macro fconst_1 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + mov tmp1, #0x3f800000 + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode fconst_1 + fconst_1 +@----------------------------------------------------------------------------- + .macro fconst_2 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + mov r2, #0x40000000 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode fconst_2 + fconst_2 +@----------------------------------------------------------------------------- + .macro dconst_1 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + mov tmp1, #0x3f000000 + DISPATCH_NEXT + orr tmp1, tmp1, #0x00f00000 + DISPATCH_NEXT + mov tmp2, #0 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode dconst_1 + dconst_1 +@----------------------------------------------------------------------------- + .macro bipush jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + mov tmp1, r2, lsl #24 + DISPATCH_NEXT + mov tmp1, tmp1, asr #24 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode bipush + bipush +@----------------------------------------------------------------------------- + .macro sipush jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + mov tmp1, r1 + DISPATCH_NEXT + mov r2, r2, lsl #24 + DISPATCH_NEXT + orr tmp1, tmp1, r2, asr #16 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode sipush + sipush +@----------------------------------------------------------------------------- + .macro u4load jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + rsb tmp1, r2, #0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode u4load + u4load +@----------------------------------------------------------------------------- + .macro u8load jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + sub r3, locals, r2, lsl #2 + DISPATCH_NEXT + ldmda r3, {tmp2, tmp1} + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode u8load + u8load +@----------------------------------------------------------------------------- + .macro aload_0 jpc_off=0, seq_len=1 + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode aload_0 + aload_0 +@----------------------------------------------------------------------------- + .macro iload_0 jpc_off=0, seq_len=1 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_0 + iload_0 +@----------------------------------------------------------------------------- + .macro fload_0 jpc_off=0, seq_len=1 + rsb tmp1, r0, #opc_fload_0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode fload_0 + fload_0 +@----------------------------------------------------------------------------- + .macro u8load_0 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + ldmda locals, {tmp2-tmp1} + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode u8load_0 + u8load_0 +@----------------------------------------------------------------------------- + .macro u8load_1 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + ldmdb locals, {tmp2-tmp1} + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode u8load_1 + u8load_1 +@----------------------------------------------------------------------------- + .macro u8load_2 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + ldr tmp2, [locals, #-12] + DISPATCH_NEXT + ldr tmp1, [locals, #-8] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode u8load_2 + u8load_2 +@----------------------------------------------------------------------------- + .macro u8load_3 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + ldr tmp2, [locals, #-16] + DISPATCH_NEXT + ldr tmp1, [locals, #-12] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode u8load_3 + u8load_3 +@----------------------------------------------------------------------------- + .macro u4aload jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry5: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + DISPATCH_NEXT + ldr tmp1, [r3, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode u4aload + u4aload +@----------------------------------------------------------------------------- + .macro u8aload jpc_off=0, seq_len=1 + POP2 r2, r3 + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry6: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #3 + ldr tmp2, [r3, #16] + DISPATCH_NEXT + ldr tmp1, [r3, #20] + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode u8aload + u8aload +@----------------------------------------------------------------------------- + .macro baload jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry7: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2 + DISPATCH_NEXT + ldrsb tmp1, [r3, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode baload + baload +@----------------------------------------------------------------------------- + .macro caload jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry8: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #1 + DISPATCH_NEXT + ldrh tmp1, [r3, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode caload + caload +@----------------------------------------------------------------------------- + .macro saload jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry9: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #1 + DISPATCH_NEXT + ldrsh tmp1, [r3, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode saload + saload +@----------------------------------------------------------------------------- + .macro u4store jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + rsb tmp1, r2, #0 + DISPATCH_NEXT + POP r3 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode u4store + u4store +@----------------------------------------------------------------------------- + .macro u8store jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + sub r3, locals, r2, lsl #2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + stmda r3, {tmp2, tmp1} + DISPATCH_FINISH + .endm + + Opcode u8store + u8store +@----------------------------------------------------------------------------- + .macro u4store_0 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + DISPATCH_NEXT + POP tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, #0] + DISPATCH_FINISH + .endm + + Opcode u4store_0 + u4store_0 +@----------------------------------------------------------------------------- + .macro u4store_1 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + DISPATCH_NEXT + POP tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, #-4] + DISPATCH_FINISH + .endm + + Opcode u4store_1 + u4store_1 +@----------------------------------------------------------------------------- + .macro u4store_2 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + DISPATCH_NEXT + POP tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, #-8] + DISPATCH_FINISH + .endm + + Opcode u4store_2 + u4store_2 +@----------------------------------------------------------------------------- + .macro u4store_3 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + DISPATCH_NEXT + POP tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, #-12] + DISPATCH_FINISH + .endm + + Opcode u4store_3 + u4store_3 +@----------------------------------------------------------------------------- + .macro u8store_0 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + DISPATCH_NEXT + POP2 tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + stmda locals, {tmp2, tmp1} + DISPATCH_FINISH + .endm + + Opcode u8store_0 + u8store_0 +@----------------------------------------------------------------------------- + .macro u8store_1 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + DISPATCH_NEXT + POP2 tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + stmdb locals, {tmp2, tmp1} + DISPATCH_FINISH + .endm + + Opcode u8store_1 + u8store_1 +@----------------------------------------------------------------------------- + .macro u8store_2 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + str tmp2, [locals, #-12] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, #-8] + DISPATCH_FINISH + .endm + + Opcode u8store_2 + u8store_2 +@----------------------------------------------------------------------------- + .macro u8store_3 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + str tmp2, [locals, #-16] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, #-12] + DISPATCH_FINISH + .endm + + Opcode u8store_3 + u8store_3 +@----------------------------------------------------------------------------- + .macro u4astore jpc_off=0, seq_len=1 + POP3 r3, tmp2, tmp1 @ r3 = value, tmp2 = index, tmp1 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry10: + ldr lr, [tmp1, #8] @ lr = limit + DISPATCH_NEXT + cmp tmp2, lr + bcs array_bound_exception_jpc_1_tmp2 + DISPATCH_NEXT + add tmp1, tmp1, tmp2, lsl #2 + DISPATCH_NEXT + str r3, [tmp1, #12] + DISPATCH_FINISH + .endm + + Opcode u4astore + u4astore +@----------------------------------------------------------------------------- + .macro u8astore jpc_off=0, seq_len=1 + POP4 r2, r3, tmp2, tmp1 @ r2,r3 = value, tmp2 = index, tmp1 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry11: + ldr ip, [tmp1, #8] @ ip = limit + cmp tmp2, ip + DISPATCH_NEXT + bcs array_bound_exception_jpc_1_tmp2 + DISPATCH_NEXT + add tmp2, tmp1, tmp2, lsl #3 + str r2, [tmp2, #16] + DISPATCH_NEXT + DISPATCH_NEXT + str r3, [tmp2, #20] + DISPATCH_FINISH + .endm + + Opcode u8astore + u8astore +@----------------------------------------------------------------------------- + .macro bastore jpc_off=0, seq_len=1 + POP3 r3, tmp2, tmp1 @ r3 = value, tmp2 = index, tmp1 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry12: + ldr lr, [tmp1, #8] @ lr = limit + DISPATCH_NEXT + cmp tmp2, lr + bcs array_bound_exception_jpc_1_tmp2 + DISPATCH_NEXT + add tmp1, tmp1, tmp2 + DISPATCH_NEXT + strb r3, [tmp1, #12] + DISPATCH_FINISH + .endm + + Opcode bastore + bastore +@----------------------------------------------------------------------------- + .macro u2astore jpc_off=0, seq_len=1 + POP3 r3, tmp2, tmp1 @ r3 = value, tmp2 = index, tmp1 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry13: + ldr lr, [tmp1, #8] @ lr = limit + DISPATCH_NEXT + cmp tmp2, lr + bcs array_bound_exception_jpc_1_tmp2 + DISPATCH_NEXT + add tmp1, tmp1, tmp2, lsl #1 + DISPATCH_NEXT + strh r3, [tmp1, #12] + DISPATCH_FINISH + .endm + + Opcode u2astore + u2astore +@----------------------------------------------------------------------------- + .macro jpop jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + add stack, stack, #4 + DISPATCH_FINISH + .endm + + Opcode jpop + jpop +@----------------------------------------------------------------------------- + .macro jpop2 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + add stack, stack, #8 + DISPATCH_FINISH + .endm + + Opcode jpop2 + jpop2 +@----------------------------------------------------------------------------- + .macro dup jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + ldr lr, [stack, #4] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode dup + dup +@----------------------------------------------------------------------------- + .macro dup_x1 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 r2, r3 + DISPATCH_NEXT + PUSH r2 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode dup_x1 + dup_x1 +@----------------------------------------------------------------------------- + .macro dup_x2 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP3 r2, r3, lr + DISPATCH_NEXT + PUSH r2 + DISPATCH_NEXT + PUSH3 r2, r3, lr + DISPATCH_FINISH + .endm + + Opcode dup_x2 + dup_x2 +@----------------------------------------------------------------------------- + .macro dup2 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + ldmib stack, {r2, r3} + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode dup2 + dup2 +@----------------------------------------------------------------------------- + .macro dup2_x1 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP3 r2, r3, lr + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_NEXT + PUSH3 r2, r3, lr + DISPATCH_FINISH + .endm + + Opcode dup2_x1 + dup2_x1 +@----------------------------------------------------------------------------- + .macro dup2_x2 jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP4 r2, r3, tmp1, lr + DISPATCH_NEXT + PUSH2 r2, r3 + PUSH4 r2, r3, tmp1, lr + DISPATCH_FINISH + .endm + + Opcode dup2_x2 + dup2_x2 +@----------------------------------------------------------------------------- + .macro swap jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 r2, r3 + DISPATCH_NEXT + PUSH r2 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode swap + swap +@----------------------------------------------------------------------------- + .macro iadd jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + add tmp2, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iadd + iadd +@----------------------------------------------------------------------------- + .macro ladd jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP4 r2, r3, tmp1, lr + DISPATCH_NEXT + adds r2, r2, tmp1 + adc r3, r3, lr + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode ladd + ladd +@----------------------------------------------------------------------------- + .macro fadd jpc_off=0, seq_len=1 + POP2 r0, r1 + bl __aeabi_fadd + PUSH r0 + DISPATCH \seq_len + .endm + + Opcode fadd + fadd +@----------------------------------------------------------------------------- + .macro isub jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode isub + isub +@----------------------------------------------------------------------------- + .macro lsub jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP4 r2, r3, tmp1, lr + DISPATCH_NEXT + subs r2, tmp1, r2 + sbc r3, lr, r3 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode lsub + lsub +@----------------------------------------------------------------------------- + .macro fsub jpc_off=0, seq_len=1 + POP r1 + POP r0 + bl __aeabi_fsub + PUSH r0 + DISPATCH \seq_len + .endm + + Opcode fsub + fsub +@----------------------------------------------------------------------------- + .macro imul jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 r2, tmp1 + DISPATCH_NEXT + mul tmp2, r2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode imul + imul +@----------------------------------------------------------------------------- + .macro lmul jpc_off=0, seq_len=1 + POP4 r2, tmp1, ip, lr + umull r3, r0, ip, r2 + mla tmp1, ip, tmp1, r0 + DISPATCH_START \seq_len + mla tmp1, lr, r2, tmp1 + DISPATCH_NEXT + PUSH2 r3, tmp1 + DISPATCH_FINISH + .endm + + Opcode lmul + lmul +@----------------------------------------------------------------------------- + .macro fmul jpc_off=0, seq_len=1 + POP2 r0, r1 + bl __aeabi_fmul + PUSH r0 + DISPATCH \seq_len + .endm + + Opcode fmul + fmul +@----------------------------------------------------------------------------- + .macro ldiv jpc_off=0, seq_len=1 + POP2 r2, r3 + POP2 r0, r1 + orrs lr, r2, r3 + beq .ldiv_0 + bl __aeabi_ldivmod + PUSH2 r0, r1 + DISPATCH \seq_len + .endm + + Opcode ldiv + ldiv +@----------------------------------------------------------------------------- + .macro fdiv jpc_off=0, seq_len=1 + POP r1 + POP r0 + bl __aeabi_fdiv + PUSH r0 + DISPATCH \seq_len + .endm + + Opcode fdiv + fdiv +@----------------------------------------------------------------------------- + .macro ddiv jpc_off=0, seq_len=1 + POP2 r2, r3 + POP2 r0, r1 + bl __aeabi_ddiv + PUSH2 r0, r1 + DISPATCH \seq_len + .endm + + Opcode ddiv + ddiv +@----------------------------------------------------------------------------- + .macro lrem jpc_off=0, seq_len=1 + POP2 r2, r3 + POP2 r0, r1 + orrs lr, r2, r3 + beq .lrem_0 + bl __aeabi_ldivmod + PUSH2 r2, r3 + DISPATCH \seq_len + .endm + + Opcode lrem + lrem +@----------------------------------------------------------------------------- + .macro frem jpc_off=0, seq_len=1 +@ ECN: It must be possible to do better than this + POP r0 + bl __aeabi_f2d + PUSH2 r0, r1 + GET_STACK 2, r0 + bl __aeabi_f2d + POP2 r2, r3 + bl fmod + bl __aeabi_d2f + PUT_STACK 0, r0 + DISPATCH \seq_len + .endm + + Opcode frem + frem +@----------------------------------------------------------------------------- + .macro drem jpc_off=0, seq_len=1 + POP2 r2, r3 + POP2 r0, r1 + bl fmod + PUSH2 r0, r1 + DISPATCH \seq_len + .endm + + Opcode drem + drem +@----------------------------------------------------------------------------- + .macro ineg jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP tmp1 + DISPATCH_NEXT + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode ineg + ineg +@----------------------------------------------------------------------------- + .macro lneg jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 r2, r3 + DISPATCH_NEXT + rsbs r2, r2, #0 + rsc r3, r3, #0 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode lneg + lneg +@----------------------------------------------------------------------------- + .macro fneg jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP r2 + DISPATCH_NEXT + eor r2, r2, #0x80000000 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode fneg + fneg +@----------------------------------------------------------------------------- + .macro dneg jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + GET_STACK 1, r2 + DISPATCH_NEXT + eor r2, r2, #0x80000000 + DISPATCH_NEXT + PUT_STACK 1, r2 + DISPATCH_FINISH + .endm + + Opcode dneg + dneg +@----------------------------------------------------------------------------- + .macro ishl jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 r2, r3 + DISPATCH_NEXT + and r2, r2, #31 + mov r2, r3, lsl r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode ishl + ishl +@----------------------------------------------------------------------------- + .macro lshl jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP3 r2, r3, lr + DISPATCH_NEXT + tst r2, #32 + and r2, r2, #31 + movne tmp1, #0 + movne lr, r3, lsl r2 + moveq tmp1, r3, lsl r2 + moveq lr, lr, lsl r2 + rsbeq r2, r2, #32 + orreq lr, lr, r3, lsr r2 + PUSH2 tmp1, lr + DISPATCH_FINISH + .endm + + Opcode lshl + lshl +@----------------------------------------------------------------------------- + .macro ishr jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 r2, r3 + DISPATCH_NEXT + and r2, r2, #31 + mov r2, r3, asr r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode ishr + ishr +@----------------------------------------------------------------------------- + .macro lshr jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + tst r2, #32 + and r2, r2, #31 + movne lr, tmp1, asr #31 + movne r3, tmp1, asr r2 + moveq lr, tmp1, asr r2 + moveq r3, r3, lsr r2 + rsbeq r2, r2, #32 + orreq r3, r3, tmp1, lsl r2 + PUSH2 r3, lr + DISPATCH_FINISH + .endm + + Opcode lshr + lshr +@----------------------------------------------------------------------------- + .macro iushr jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 r2, r3 + DISPATCH_NEXT + and r2, r2, #31 + mov r2, r3, lsr r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode iushr + iushr +@----------------------------------------------------------------------------- + .macro lushr jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + tst r2, #32 + and r2, r2, #31 + movne lr, #0 + movne r3, tmp1, lsr r2 + moveq lr, tmp1, lsr r2 + moveq r3, r3, lsr r2 + rsbeq r2, r2, #32 + orreq r3, r3, tmp1, lsl r2 + PUSH2 r3, lr + DISPATCH_FINISH + .endm + + Opcode lushr + lushr +@----------------------------------------------------------------------------- + .macro iand jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + and tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iand + iand +@----------------------------------------------------------------------------- + .macro land jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP4 r2, r3, tmp1, lr + DISPATCH_NEXT + and r2, tmp1, r2 + and r3, lr, r3 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode land + land +@----------------------------------------------------------------------------- + .macro ior jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + orr tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode ior + ior +@----------------------------------------------------------------------------- + .macro lor jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP4 r2, r3, tmp1, lr + DISPATCH_NEXT + orr r2, tmp1, r2 + orr r3, lr, r3 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode lor + lor +@----------------------------------------------------------------------------- + .macro ixor jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + eor tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode ixor + ixor +@----------------------------------------------------------------------------- + .macro lxor jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP4 r2, r3, tmp1, lr + DISPATCH_NEXT + eor r2, tmp1, r2 + eor r3, lr, r3 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode lxor + lxor +@----------------------------------------------------------------------------- + .macro iinc jpc_off=0, seq_len=3 + ldrsb lr, [jpc, #2] + DISPATCH_START \seq_len + rsb tmp1, r2, #0 + DISPATCH_NEXT + ldr r3, [locals, tmp1, lsl #2] + DISPATCH_NEXT + add r3, r3, lr + DISPATCH_NEXT + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iinc + iinc +@----------------------------------------------------------------------------- + .macro i2l jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP r2 + DISPATCH_NEXT + mov r3, r2, asr #31 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode i2l + i2l +@----------------------------------------------------------------------------- + .macro i2f jpc_off=0, seq_len=1 + POP r0 + bl __aeabi_i2f + PUSH r0 + DISPATCH \seq_len + .endm + + Opcode i2f + i2f +@----------------------------------------------------------------------------- + .macro i2d jpc_off=0, seq_len=1 + POP r0 + bl __aeabi_i2d + PUSH2 r0, r1 + DISPATCH \seq_len + .endm + + Opcode i2d + i2d +@----------------------------------------------------------------------------- + .macro l2i jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP r3 + DISPATCH_NEXT + PUT_STACK 0, r3 + DISPATCH_FINISH + .endm + + Opcode l2i + l2i +@----------------------------------------------------------------------------- + .macro l2f jpc_off=0, seq_len=1 + POP2 r0, r1 + bl __aeabi_l2f + PUSH r0 + DISPATCH \seq_len + .endm + + Opcode l2f + l2f +@----------------------------------------------------------------------------- + .macro l2d jpc_off=0, seq_len=1 + POP2 r0, r1 + bl __aeabi_l2d + PUSH2 r0, r1 + DISPATCH \seq_len + .endm + + Opcode l2d + l2d +@----------------------------------------------------------------------------- + .macro f2i jpc_off=0, seq_len=1 + POP r0 + bl _ZN13SharedRuntime3f2iEf + PUSH r0 + DISPATCH \seq_len + .endm + + Opcode f2i + f2i +@----------------------------------------------------------------------------- + .macro f2l jpc_off=0, seq_len=1 + POP r0 + bl _ZN13SharedRuntime3f2lEf + PUSH2 r0, r1 + DISPATCH \seq_len + .endm + + Opcode f2l + f2l +@----------------------------------------------------------------------------- + .macro f2d jpc_off=0, seq_len=1 + POP r0 + bl __aeabi_f2d + PUSH2 r0, r1 + DISPATCH \seq_len + .endm + + Opcode f2d + f2d +@----------------------------------------------------------------------------- + .macro d2i jpc_off=0, seq_len=1 + POP2 r0, r1 + bl _ZN13SharedRuntime3d2iEd + PUSH r0 + DISPATCH \seq_len + .endm + + Opcode d2i + d2i +@----------------------------------------------------------------------------- + .macro d2l jpc_off=0, seq_len=1 + POP2 r0, r1 + bl _ZN13SharedRuntime3d2lEd + PUSH2 r0, r1 + DISPATCH \seq_len + .endm + + Opcode d2l + d2l +@----------------------------------------------------------------------------- + .macro d2f jpc_off=0, seq_len=1 + POP2 r0, r1 + bl __aeabi_d2f + PUSH r0 + DISPATCH \seq_len + .endm + + Opcode d2f + d2f +@----------------------------------------------------------------------------- + .macro i2b jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP r3 + DISPATCH_NEXT + mov r3, r3, asl #24 + mov r3, r3, asr #24 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode i2b + i2b +@----------------------------------------------------------------------------- + .macro i2c jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP r3 + DISPATCH_NEXT + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode i2c + i2c +@----------------------------------------------------------------------------- + .macro i2s jpc_off=0, seq_len=1 + DISPATCH_START \seq_len + POP r3 + DISPATCH_NEXT + mov r3, r3, asl #16 + mov r3, r3, asr #16 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode i2s + i2s +@----------------------------------------------------------------------------- + .macro lcmp jpc_off=0, seq_len=1 + POP4 r2, r3, tmp1, lr + DISPATCH_START \seq_len + subs r2, tmp1, r2 + movne r2, #1 + sbcs lr, lr, r3 + DISPATCH_NEXT + movne r2, #1 + rsblt r2, r2, #0 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode lcmp + lcmp +@----------------------------------------------------------------------------- + .macro fcmpl jpc_off=0, seq_len=1 + ldmib stack, {r0, r1} + bl __aeabi_fcmpgt + cmp r0, #0 + movne r3, #-1 + bne 3f + ldmib stack, {r0, r1} + bl __aeabi_fcmplt + cmp r0, #0 + movne r3, #1 + bne 3f + ldmib stack, {r0, r1} + bl __aeabi_fcmpeq + cmp r0, #0 + movne r3, #0 + moveq r3, #-1 +3: + DISPATCH_START \seq_len + add stack, stack, #8 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode fcmpl + fcmpl +@----------------------------------------------------------------------------- + .macro fcmpg jpc_off=0, seq_len=1 + ldmib stack, {r0, r1} + bl __aeabi_fcmpgt + cmp r0, #0 + movne r3, #-1 + bne 4f + ldmib stack, {r0, r1} + bl __aeabi_fcmplt + cmp r0, #0 + movne r3, #1 + bne 4f + ldmib stack, {r0, r1} + bl __aeabi_fcmpeq + cmp r0, #0 + movne r3, #0 + moveq r3, #1 +4: + DISPATCH_START \seq_len + add stack, stack, #8 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode fcmpg + fcmpg +@----------------------------------------------------------------------------- + .macro dcmpl jpc_off=0, seq_len=1 + ldmib stack, {r0, r1, r2, r3} + bl __aeabi_dcmpgt + cmp r0, #0 + movne r3, #-1 + bne 5f + ldmib stack, {r0, r1, r2, r3} + bl __aeabi_dcmplt + cmp r0, #0 + movne r3, #1 + bne 5f + ldmib stack, {r0, r1, r2, r3} + bl __aeabi_dcmpeq + cmp r0, #0 + movne r3, #0 + moveq r3, #-1 +5: + DISPATCH_START \seq_len + add stack, stack, #16 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode dcmpl + dcmpl +@----------------------------------------------------------------------------- + .macro dcmpg jpc_off=0, seq_len=1 + ldmib stack, {r0, r1, r2, r3} + bl __aeabi_dcmpgt + cmp r0, #0 + movne r3, #-1 + bne 6f + ldmib stack, {r0, r1, r2, r3} + bl __aeabi_dcmplt + cmp r0, #0 + movne r3, #1 + bne 6f + ldmib stack, {r0, r1, r2, r3} + bl __aeabi_dcmpeq + cmp r0, #0 + movne r3, #0 + moveq r3, #1 +6: + DISPATCH_START \seq_len + add stack, stack, #16 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode dcmpg + dcmpg +@----------------------------------------------------------------------------- + .macro ifeq_unsafe jpc_off=0, seq_len=0 + POP r3 + mov r2, r2, lsl #24 + cmp r3, #0 + orr ip, r1, r2, asr #16 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ifeq_unsafe + ifeq_unsafe +@----------------------------------------------------------------------------- + .macro ifne_unsafe jpc_off=0, seq_len=0 + POP r3 + mov r2, r2, lsl #24 + cmp r3, #0 + orr ip, r1, r2, asr #16 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ifne_unsafe + ifne_unsafe +@----------------------------------------------------------------------------- + .macro iflt_unsafe jpc_off=0, seq_len=0 + POP r3 + mov r2, r2, lsl #24 + cmp r3, #0 + orr ip, r1, r2, asr #16 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iflt_unsafe + iflt_unsafe +@----------------------------------------------------------------------------- + .macro ifge_unsafe jpc_off=0, seq_len=0 + POP r3 + mov r2, r2, lsl #24 + cmp r3, #0 + orr ip, r1, r2, asr #16 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ifge_unsafe + ifge_unsafe +@----------------------------------------------------------------------------- + .macro ifgt_unsafe jpc_off=0, seq_len=0 + POP r3 + mov r2, r2, lsl #24 + cmp r3, #0 + orr ip, r1, r2, asr #16 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ifgt_unsafe + ifgt_unsafe +@----------------------------------------------------------------------------- + .macro ifle_unsafe jpc_off=0, seq_len=0 + POP r3 + mov r2, r2, lsl #24 + cmp r3, #0 + orr ip, r1, r2, asr #16 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ifle_unsafe + ifle_unsafe +@----------------------------------------------------------------------------- + .macro if_icmpeq_unsafe jpc_off=0, seq_len=0 + POP2 r3, tmp1 + mov r2, r2, lsl #24 + cmp tmp1, r3 + orr ip, r1, r2, asr #16 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode if_icmpeq_unsafe + if_icmpeq_unsafe +@----------------------------------------------------------------------------- + .macro if_icmpne_unsafe jpc_off=0, seq_len=0 + POP2 r3, tmp1 + mov r2, r2, lsl #24 + cmp tmp1, r3 + orr ip, r1, r2, asr #16 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode if_icmpne_unsafe + if_icmpne_unsafe +@----------------------------------------------------------------------------- + .macro if_icmplt_unsafe jpc_off=0, seq_len=0 + POP2 r3, tmp1 + mov r2, r2, lsl #24 + cmp tmp1, r3 + orr ip, r1, r2, asr #16 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode if_icmplt_unsafe + if_icmplt_unsafe +@----------------------------------------------------------------------------- + .macro if_icmpge_unsafe jpc_off=0, seq_len=0 + POP2 r3, tmp1 + mov r2, r2, lsl #24 + cmp tmp1, r3 + orr ip, r1, r2, asr #16 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode if_icmpge_unsafe + if_icmpge_unsafe +@----------------------------------------------------------------------------- + .macro if_icmpgt_unsafe jpc_off=0, seq_len=0 + POP2 r3, tmp1 + mov r2, r2, lsl #24 + cmp tmp1, r3 + orr ip, r1, r2, asr #16 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode if_icmpgt_unsafe + if_icmpgt_unsafe +@----------------------------------------------------------------------------- + .macro if_icmple_unsafe jpc_off=0, seq_len=0 + POP2 r3, tmp1 + mov r2, r2, lsl #24 + cmp tmp1, r3 + orr ip, r1, r2, asr #16 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode if_icmple_unsafe + if_icmple_unsafe +@----------------------------------------------------------------------------- + .macro goto_unsafe jpc_off=0, seq_len=0 + mov r2, r2, lsl #24 + orr ip, r1, r2, asr #16 + DISPATCH_START_REG ip + DISPATCH_BYTECODE + .endm + + Opcode goto_unsafe + goto_unsafe +@----------------------------------------------------------------------------- + .macro jsr jpc_off=0, seq_len=0 + ldr r3, [istate, #ISTATE_METHOD] + ldr r1, [r3, #8] + rsb r2, r1, jpc + sub r2, r2, #45 + PUSH r2 + b do_goto_safe + .endm + + Opcode jsr + jsr +@----------------------------------------------------------------------------- + .macro ret jpc_off=0, seq_len=0 + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [r0, #8] + ldr r1, [locals, -r2, lsl #2] + add jpc, r3, r1 + DISPATCH 48 + .endm + + Opcode ret + ret +@----------------------------------------------------------------------------- + .macro tableswitch jpc_off=0, seq_len=0 + POP a2 + bic a1, jpc, #3 + ldr a4,[a1,#8] +@ BYTESEX_REVERSE a3, a4, a3 + + eor a3, a4, a4, ror #16 + bic a3, a3, #0xff0000 + mov a4, a4, ror #8 + eor a3, a4, a3, lsr #8 + + ldr a4,[a1,#12] +@ BYTESEX_REVERSE a4, a4, ip + + eor ip, a4, a4, ror #16 + bic ip, ip, #0xff0000 + mov a4, a4, ror #8 + eor a4, a4, ip, lsr #8 + + sub a2,a2,a3 + sub a4,a4,a3 + cmp a4,a2 + ldrcc a1,[a1,#4] + addcs a1,a1,a2,LSL #2 + ldrcs a1,[a1,#16] +@ BYTESEX_REVERSE a1, a1, a4 + + eor a4, a1, a1, ror #16 + bic a4, a4, #0xff0000 + mov a1, a1, ror #8 + eors ip, a1, a4, lsr #8 + + DISPATCH_START_REG ip + DISPATCH_BYTECODE + .endm + + Opcode tableswitch + tableswitch +@----------------------------------------------------------------------------- + .macro lookupswitch jpc_off=0, seq_len=0 + POP a2 + bic a1, jpc, #3 +@ BYTESEX_REVERSE a2, a2, ip + + eor ip, a2, a2, ror #16 + bic ip, ip, #0xff0000 + mov a2, a2, ror #8 + eor a2, a2, ip, lsr #8 + + ldr a3,[a1,#8] +@ BYTESEX_REVERSE a3, a3, ip + + eor ip, a3, a3, ror #16 + bic ip, ip, #0xff0000 + mov a3, a3, ror #8 + eor a3, a3, ip, lsr #8 + + subs a4,a3,#1 + bmi 1f + add a1, a1, #4 +0: + ldr a3,[a1,#8]! + cmp a3,a2 + beq 2f + subs a4,a4,#1 + bpl 0b +1: + bic a1, jpc, #3 +2: + ldr a2,[a1,#4] +@ BYTESEX_REVERSE a2, a2, ip + + eor ip, a2, a2, ror #16 + bic ip, ip, #0xff0000 + mov a2, a2, ror #8 + eors ip, a2, ip, lsr #8 + + DISPATCH_START_REG ip + DISPATCH_BYTECODE + .endm + + Opcode lookupswitch + lookupswitch +@----------------------------------------------------------------------------- + .macro igetfield jpc_off=0, seq_len=3 + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP tmp1 + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry78: + ldr tmp2, [tmp1, tmp2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode igetfield + igetfield +@----------------------------------------------------------------------------- + .macro bgetfield jpc_off=0, seq_len=3 + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP tmp1 + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry79: + ldrsb tmp2, [tmp1, tmp2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode bgetfield + bgetfield +@----------------------------------------------------------------------------- + .macro cgetfield jpc_off=0, seq_len=3 + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP tmp1 + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry80: + ldrh tmp2, [tmp1, tmp2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode cgetfield + cgetfield +@----------------------------------------------------------------------------- + .macro sgetfield jpc_off=0, seq_len=3 + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP tmp1 + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry81: + ldrsh tmp2, [tmp1, tmp2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode sgetfield + sgetfield +@----------------------------------------------------------------------------- + .macro lgetfield jpc_off=0, seq_len=3 + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP tmp1 + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT +.abortentry82: + ldmia tmp2, {tmp2, tmp1} + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode lgetfield + lgetfield +@----------------------------------------------------------------------------- + .macro iputfield jpc_off=0, seq_len=3 + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP2 r3, tmp1 @ r3 = value, tmp1 = object + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT +.abortentry83: + str r3, [tmp1, tmp2] + DISPATCH_FINISH + .endm + + Opcode iputfield + iputfield +@----------------------------------------------------------------------------- + .macro cputfield jpc_off=0, seq_len=3 + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP2 r3, tmp1 @ r3 = value, tmp1 = object + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT +.abortentry84: + strh r3, [tmp1, tmp2] + DISPATCH_FINISH + .endm + + Opcode cputfield + cputfield +@----------------------------------------------------------------------------- + .macro bputfield jpc_off=0, seq_len=3 + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP2 r3, tmp1 @ r3 = value, tmp1 = object + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT +.abortentry85: + strb r3, [tmp1, tmp2] + DISPATCH_FINISH + .endm + + Opcode bputfield + bputfield +@----------------------------------------------------------------------------- + .macro aputfield jpc_off=0, seq_len=3 + GET_STACK 1, r0 @ r0 = object + add tmp2, constpool, r1, lsl #12 + POP r1 @ r1 = value + add tmp2, tmp2, r2, lsl #4 + ldr tmp2, [tmp2, #8] + cmp r0, #0 + beq null_ptr_exception + add r0, r0, tmp2 + bl oop_store + ldr r3, [dispatch, #Universe_collectedHeap_Address-XXX] + DISPATCH_START 3 + POP r2 + ldr r3, [r3, #0] + DISPATCH_NEXT + ldr r3, [r3, #12] + DISPATCH_NEXT + ldr r3, [r3, #76] + mov tmp2, #0 + strb tmp2, [r3, r2, lsr #9] + DISPATCH_FINISH + .endm + + Opcode aputfield + aputfield +@----------------------------------------------------------------------------- + .macro lputfield jpc_off=0, seq_len=3 + DISPATCH_START 3 + add tmp2, constpool, r1, lsl #12 + POP3 r3, tmp1, lr @ r3, tmp1 = value, lr = object + add tmp2, tmp2, r2, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + add tmp2, lr, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT +.abortentry86: + stm tmp2, {r3, tmp1} + DISPATCH_FINISH + .endm + + Opcode lputfield + lputfield +@----------------------------------------------------------------------------- + .macro getstatic jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + add tmp2, constpool, r1, lsl #12 + ldr r3, [tmp2, r2, lsl #4]! @ tmp2 = cache, r3 = flags + DISPATCH_NEXT + and r3, r3, #0x00ff0000 + cmp r3, #178 << 16 + bne resolve_getstatic + ldr r3, [tmp2, #4] + ldr r2, [tmp2, #12] + ldr lr, [tmp2, #8] + movs r2, r2, lsr #29 + bhi getstatic_w @ C = 1, Z = 0 => R2 == 3, 5, 7 + bcs getstatic_h @ C = 1 => R2 = 1 + beq getstatic_sb @ Z = 1 => R2 = 0 + tst r2, #2 + bne getstatic_dw + b getstatic_sh + .endm + + Opcode getstatic + getstatic +@----------------------------------------------------------------------------- + .macro putstatic jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + add tmp2, constpool, r1, lsl #12 + ldr r3, [tmp2, r2, lsl #4]! @ tmp2 = cache, r3 = flags + DISPATCH_NEXT + and r3, r3, #0xff000000 + cmp r3, #179 << 24 + bne resolve_putstatic + ldr r3, [tmp2, #4] @ r3 = object + ldr lr, [tmp2, #12] @ lr = tos_type + ldr r2, [tmp2, #8] @ r2 = offset + movs lr, lr, lsr #29 + bhi putstatic_w @ C = 1, Z = 0 => R2 == 3, 5, 7 + bcs putstatic_h @ C = 1 => R2 = 1 + beq putstatic_sb @ Z = 1 => R2 = 0 + tst lr, #2 + bne putstatic_dw + b putstatic_sh + .endm + + Opcode putstatic + putstatic +@----------------------------------------------------------------------------- + .macro return_unsafe jpc_off=0, seq_len=0 + + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + ldr tmp_xxx, [istate, #ISTATE_THREAD] + + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + + ldr r2, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [r2, #0] + ldrh r0, [r0, #40] + add r1, r2, #4 + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + add stack, r1, r0, lsl #2 + cmp istate, #0 + beq normal_return + + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT + add r2, r2, #4 + DISPATCH_NEXT + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + bl return_check_monitors + b 2b + .endm + + Opcode return_unsafe + return_unsafe +@----------------------------------------------------------------------------- + .macro ireturn_unsafe jpc_off=0, seq_len=0 + + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + ldr tmp_xxx, [istate, #ISTATE_THREAD] + + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + + POP r1 @ pop result before we lose stack + + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + bl return_check_monitors + b 2b + .endm + + Opcode ireturn_unsafe + ireturn_unsafe +@----------------------------------------------------------------------------- + .macro lreturn_unsafe jpc_off=0, seq_len=0 + + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + + ldr r2, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [r2, #0] + ldrh r0, [r0, #40] + add r1, r2, #4 + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + + POP2 r2, r3 + + add stack, r1, r0, lsl #2 + stmdb stack!, {r2, r3} + cmp istate, #0 + beq normal_return + + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT + add r2, r2, #4 + DISPATCH_NEXT + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + bl return_check_monitors + b 2b + .endm + + Opcode lreturn_unsafe + lreturn_unsafe +@----------------------------------------------------------------------------- + .macro ldc jpc_off=0, seq_len=2 + ldrb lr, [jpc, #1] + ldr r3, [istate, #ISTATE_METHOD] @ method + + DISPATCH_START \seq_len + + ldr r2, [r3, #12] @ constants + ldr r3, [r2, #8] + add r3, r3, #12 + ldrb r3, [r3, lr] + + DISPATCH_NEXT + + cmp r3, #JVM_CONSTANT_Integer + cmpne r3, #JVM_CONSTANT_Float + cmpne r3, #JVM_CONSTANT_String + bne 1f + + DISPATCH_NEXT + + add r3, r2, lr, lsl #2 + ldr lr, [r3, #32] + PUSH lr + DISPATCH_FINISH +1: + cmp r3, #JVM_CONSTANT_Class + bne 2f + add r0, r2, #32 + ldr r0, [r0, lr, lsl #2] + ldr r1, [r0, #60] + PUSH r1 + DISPATCH 0 +2: + sub jpc, jpc, #\seq_len + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + mov r1, #0 + bl _ZN18InterpreterRuntime3ldcEP10JavaThreadb + ldr r0, [istate, #ISTATE_THREAD] @ thread + ldr stack, [istate, #ISTATE_STACK] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr r1, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + add constpool, constpool, #CONST_POOL_OFFSET + cmp r1, #0 + ldr locals, [istate, #ISTATE_LOCALS] + bne handle_exception + ldr r3, [r0, #THREAD_VM_RESULT] + mov r2, #0 + PUSH r3 + str r2, [r0, #THREAD_VM_RESULT] + DISPATCH \seq_len + .endm + + Opcode ldc + ldc +@----------------------------------------------------------------------------- + .macro ldc_w jpc_off=0, seq_len=3 + ldrb lr, [jpc, #1] + + ldr r3, [istate, #ISTATE_METHOD] @ method + ldrb ip, [jpc, #2] + ldr r2, [r3, #12] @ constants + + DISPATCH_START \seq_len + + ldr r3, [r2, #8] + orr lr, ip, lr, lsl #8 + add r3, r3, #12 + ldrb r3, [r3, lr] + + DISPATCH_NEXT + + cmp r3, #JVM_CONSTANT_Integer + cmpne r3, #JVM_CONSTANT_Float + cmpne r3, #JVM_CONSTANT_String + bne 1f + + DISPATCH_NEXT + + add r3, r2, lr, lsl #2 + ldr lr, [r3, #32] + PUSH lr + DISPATCH_FINISH +1: + cmp r3, #JVM_CONSTANT_Class + bne 2f + add r0, r2, #32 + ldr r0, [r0, lr, lsl #2] + ldr r1, [r0, #60] + PUSH r1 + DISPATCH 0 +2: + sub jpc, jpc, #\seq_len + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + mov r1, #1 + bl _ZN18InterpreterRuntime3ldcEP10JavaThreadb + ldr r0, [istate, #ISTATE_THREAD] @ thread + ldr stack, [istate, #ISTATE_STACK] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr r1, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + add constpool, constpool, #CONST_POOL_OFFSET + cmp r1, #0 + ldr locals, [istate, #ISTATE_LOCALS] + bne handle_exception + ldr r3, [r0, #THREAD_VM_RESULT] + mov r2, #0 + PUSH r3 + str r2, [r0, #THREAD_VM_RESULT] + DISPATCH \seq_len + .endm + + Opcode ldc_w + ldc_w +@----------------------------------------------------------------------------- + .macro ldc2_w jpc_off=0, seq_len=3 + ldrb r3, [jpc, #1] + + ldr tmp1, [istate, #ISTATE_METHOD] @ method + ldrb lr, [jpc, #2] + ldr r2, [tmp1, #12] @ constants + + DISPATCH_START \seq_len + + ldr tmp1, [r2, #8] + orr r3, lr, r3, lsl #8 + add tmp1, tmp1, #12 + ldrb tmp1, [tmp1, r3] + + DISPATCH_NEXT + + cmp tmp1, #JVM_CONSTANT_Long + cmpne tmp1, #JVM_CONSTANT_Double + bne vm_fatal_error + + DISPATCH_NEXT + add tmp1, r2, r3, lsl #2 + add tmp1, tmp1, #32 + ldmia tmp1, {r3, tmp1} + PUSH2 r3, tmp1 + DISPATCH_FINISH + .endm + + Opcode ldc2_w + ldc2_w +@----------------------------------------------------------------------------- + .macro iadd_u4store jpc_off=0, seq_len=3 + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iadd_u4store + iadd_u4store +@----------------------------------------------------------------------------- + .macro isub_u4store jpc_off=0, seq_len=3 + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode isub_u4store + isub_u4store +@----------------------------------------------------------------------------- + .macro iand_u4store jpc_off=0, seq_len=3 + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + and tmp2, tmp1, tmp2 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iand_u4store + iand_u4store +@----------------------------------------------------------------------------- + .macro ior_u4store jpc_off=0, seq_len=3 + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + orr tmp2, tmp1, tmp2 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode ior_u4store + ior_u4store +@----------------------------------------------------------------------------- + .macro ixor_u4store jpc_off=0, seq_len=3 + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + eor tmp2, tmp1, tmp2 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode ixor_u4store + ixor_u4store +@----------------------------------------------------------------------------- + .macro iadd_istore_N jpc_off=0, seq_len=2 + ldrb lr, [jpc, #1] + DISPATCH_START \seq_len + DISPATCH_NEXT + rsb r3, lr, #opc_istore_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iadd_istore_N + iadd_istore_N +@----------------------------------------------------------------------------- + .macro isub_istore_N jpc_off=0, seq_len=2 + ldrb lr, [jpc, #1] + DISPATCH_START \seq_len + DISPATCH_NEXT + rsb r3, lr, #opc_istore_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode isub_istore_N + isub_istore_N +@----------------------------------------------------------------------------- + .macro iand_istore_N jpc_off=0, seq_len=2 + ldrb lr, [jpc, #1] + DISPATCH_START \seq_len + DISPATCH_NEXT + rsb r3, lr, #opc_istore_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + and tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iand_istore_N + iand_istore_N +@----------------------------------------------------------------------------- + .macro ior_istore_N jpc_off=0, seq_len=2 + ldrb lr, [jpc, #1] + DISPATCH_START \seq_len + DISPATCH_NEXT + rsb r3, lr, #opc_istore_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + orr tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode ior_istore_N + ior_istore_N +@----------------------------------------------------------------------------- + .macro ixor_istore_N jpc_off=0, seq_len=2 + ldrb lr, [jpc, #1] + DISPATCH_START \seq_len + DISPATCH_NEXT + rsb r3, lr, #opc_istore_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + eor tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode ixor_istore_N + ixor_istore_N +@----------------------------------------------------------------------------- + .macro iload_iconst_N jpc_off=0, seq_len=3 + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + rsb r2, r2, #0 + DISPATCH_NEXT + sub r3, r3, #opc_iconst_0 + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N + iload_iconst_N +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N jpc_off=0, seq_len=2 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + ldrb r2, [jpc, #1-\seq_len] + DISPATCH_NEXT + ldr tmp1, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp2, r2, #opc_iconst_0 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N + iload_0_iconst_N +@----------------------------------------------------------------------------- + .macro iaccess_0 jpc_off=0, seq_len=4 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb r3, [jpc, #2] + add tmp2, constpool, r2, lsl #12 + DISPATCH_START 4 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, r3, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + DISPATCH_NEXT + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry87: + ldr tmp2, [tmp1, tmp2] + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iaccess_0 + iaccess_0 +@----------------------------------------------------------------------------- + .macro aload_0_aload_0 jpc_off=0, seq_len=2 + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_aload_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode aload_0_aload_0 + aload_0_aload_0 +@----------------------------------------------------------------------------- + .macro aload_0_iload_0 jpc_off=0, seq_len=2 + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_iload_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode aload_0_iload_0 + aload_0_iload_0 +@----------------------------------------------------------------------------- + .macro iload_0_aload_0 jpc_off=0, seq_len=2 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_aload_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_0_aload_0 + iload_0_aload_0 +@----------------------------------------------------------------------------- + .macro iload_0_iload_0 jpc_off=0, seq_len=2 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_iload_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_0_iload_0 + iload_0_iload_0 +@----------------------------------------------------------------------------- + .macro aload_0_iload jpc_off=0, seq_len=3 + ldrb r3, [jpc, #2] + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp1 + DISPATCH_FINISH + .endm + + Opcode aload_0_iload + aload_0_iload +@----------------------------------------------------------------------------- + .macro iload_0_iload jpc_off=0, seq_len=3 + ldrb r3, [jpc, #2] + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_0_iload + iload_0_iload +@----------------------------------------------------------------------------- + .macro iload_aload_0 jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_aload_0 + DISPATCH_NEXT + rsb tmp1, r2, #0 + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_aload_0 + iload_aload_0 +@----------------------------------------------------------------------------- + .macro iload_iload_0 jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_iload_0 + DISPATCH_NEXT + rsb tmp1, r2, #0 + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_iload_0 + iload_iload_0 +@----------------------------------------------------------------------------- + .macro iload_iload jpc_off=0, seq_len=4 + ldrb tmp2, [jpc, #3] + rsb tmp1, r2, #0 + DISPATCH_START \seq_len + rsb tmp2, tmp2, #0 + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 tmp2, tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_iload + iload_iload +@----------------------------------------------------------------------------- + .macro aload_0_astore_0 jpc_off=0, seq_len=2 + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_astore_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode aload_0_astore_0 + aload_0_astore_0 +@----------------------------------------------------------------------------- + .macro iload_0_istore_0 jpc_off=0, seq_len=2 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + rsb tmp2, r1, #opc_istore_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_0_istore_0 + iload_0_istore_0 +@----------------------------------------------------------------------------- + .macro aload_0_astore jpc_off=0, seq_len=3 + ldrb tmp2, [jpc, #2] + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + rsb tmp2, tmp2, #0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode aload_0_astore + aload_0_astore +@----------------------------------------------------------------------------- + .macro iload_0_astore jpc_off=0, seq_len=3 + ldrb tmp2, [jpc, #2] + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + rsb tmp2, tmp2, #0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp1, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_0_astore + iload_0_astore +@----------------------------------------------------------------------------- + .macro iload_astore_0 jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + rsb tmp1, r1, #opc_astore_0 + DISPATCH_NEXT + rsb tmp2, r2, #0 + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_astore_0 + iload_astore_0 +@----------------------------------------------------------------------------- + .macro iload_istore_0 jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + rsb tmp1, r1, #opc_istore_0 + DISPATCH_NEXT + rsb tmp2, r2, #0 + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_istore_0 + iload_istore_0 +@----------------------------------------------------------------------------- + .macro iload_astore jpc_off=0, seq_len=4 + ldrb tmp1, [jpc, #3] + rsb tmp2, r2, #0 + DISPATCH_START \seq_len + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + str tmp2, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_astore + iload_astore +@----------------------------------------------------------------------------- + .macro aload_0_iconst_m1 jpc_off=0, seq_len=2 + rsb tmp1, r0, #opc_aload_0 + DISPATCH_START \seq_len + sub tmp2, r1, #opc_iconst_0 + DISPATCH_NEXT + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode aload_0_iconst_m1 + aload_0_iconst_m1 +@----------------------------------------------------------------------------- + .macro iload_0_iconst_m1 jpc_off=0, seq_len=2 + add r0, r0, #opc_iload_0_iconst_N-opc_iload_0 + strb r0, [jpc] + b do_iload_0_iconst_N + .endm + + Opcode iload_0_iconst_m1 + iload_0_iconst_m1 +@----------------------------------------------------------------------------- + .macro iload_iconst_m1 jpc_off=0, seq_len=3 + cmp r0, #opc_iload + DISPATCH_START \seq_len + sub r3, r1, #opc_iconst_0 + DISPATCH_NEXT + ldr tmp2, [locals, -r2, lsl #2] + DISPATCH_NEXT + beq 1f + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH +1: + mov tmp1, #opc_iload_iconst_N + strb tmp1, [jpc, #-\seq_len]! + b do_iload_iconst_N + .endm + + Opcode iload_iconst_m1 + iload_iconst_m1 +@----------------------------------------------------------------------------- + .macro aload_0_bipush jpc_off=0, seq_len=3 + ldrsb r2, [jpc, #2] + rsb r3, r0, #opc_aload_0 + DISPATCH_START \seq_len + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode aload_0_bipush + aload_0_bipush +@----------------------------------------------------------------------------- + .macro iload_0_bipush jpc_off=0, seq_len=3 + ldrsb r2, [jpc, #2] + rsb r3, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode iload_0_bipush + iload_0_bipush +@----------------------------------------------------------------------------- + .macro aload_0_sipush jpc_off=0, seq_len=4 + ldrsb r2, [jpc, #2] @ zero_extendqisi2 + ldrb lr, [jpc, #3] @ zero_extendqisi2 + rsb r3, r0, #opc_aload_0 + DISPATCH_START \seq_len + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + orr r2, lr, r2, asl #8 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode aload_0_sipush + aload_0_sipush +@----------------------------------------------------------------------------- + .macro iload_0_sipush jpc_off=0, seq_len=4 + ldrsb r2, [jpc, #2] @ zero_extendqisi2 + ldrb lr, [jpc, #3] @ zero_extendqisi2 + rsb r3, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + orr r2, lr, r2, asl #8 + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode iload_0_sipush + iload_0_sipush +@----------------------------------------------------------------------------- + .macro iload_bipush jpc_off=0, seq_len=4 + ldrsb r3, [jpc, #3] + DISPATCH_START \seq_len + ldr lr, [locals, -r2, lsl #2] + DISPATCH_NEXT + PUSH2 r3, lr + DISPATCH_FINISH + .endm + + Opcode iload_bipush + iload_bipush +@----------------------------------------------------------------------------- + .macro iload_sipush jpc_off=0, seq_len=5 + ldrsb r3, [jpc, #3] + ldrb lr, [jpc, #4] + DISPATCH_START \seq_len + ldr tmp1, [locals, -r2, lsl #2] + orr r3, lr, r3, asl #8 + DISPATCH_NEXT + PUSH2 r3, tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_sipush + iload_sipush +@----------------------------------------------------------------------------- + .macro iload_0_iaload jpc_off=0, seq_len=2 + POP r3 + rsb r2, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr r2, [locals, r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry19: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2, lsl #2 + ldr lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_0_iaload + iload_0_iaload +@----------------------------------------------------------------------------- + .macro iload_iaload jpc_off=0, seq_len=3 + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry20: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2, lsl #2 + ldr lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_iaload + iload_iaload +@----------------------------------------------------------------------------- + .macro iload_0_baload jpc_off=0, seq_len=2 + POP r3 + rsb r2, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr r2, [locals, r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry21: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2 + ldrsb lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_0_baload + iload_0_baload +@----------------------------------------------------------------------------- + .macro iload_0_caload jpc_off=0, seq_len=2 + POP r3 + rsb r2, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr r2, [locals, r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry22: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2, lsl #1 + ldrh lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_0_caload + iload_0_caload +@----------------------------------------------------------------------------- + .macro iload_0_saload jpc_off=0, seq_len=2 + POP r3 + rsb r2, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr r2, [locals, r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry23: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2, lsl #1 + ldrsh lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_0_saload + iload_0_saload +@----------------------------------------------------------------------------- + .macro iload_baload jpc_off=0, seq_len=3 + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry24: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2 + ldrsb lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_baload + iload_baload +@----------------------------------------------------------------------------- + .macro iload_caload jpc_off=0, seq_len=3 + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry25: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2, lsl #1 + ldrh lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_caload + iload_caload +@----------------------------------------------------------------------------- + .macro iload_saload jpc_off=0, seq_len=3 + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry26: + ldr lr, [r3, #8] @ lr = length + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + add r3, r3, r2, lsl #1 + ldrsh lr, [r3, #12] + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_saload + iload_saload +@----------------------------------------------------------------------------- + .macro iload_0_iastore jpc_off=0, seq_len=2 + POP2 r2, r3 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry27: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH + .endm + + Opcode iload_0_iastore + iload_0_iastore +@----------------------------------------------------------------------------- + .macro iload_0_bastore jpc_off=0, seq_len=2 + POP2 r2, r3 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry28: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2 + strb tmp1, [r3, #12] + DISPATCH_FINISH + .endm + + Opcode iload_0_bastore + iload_0_bastore +@----------------------------------------------------------------------------- + .macro iload_0_castore jpc_off=0, seq_len=2 + POP2 r2, r3 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry29: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #1 + strh tmp1, [r3, #12] + DISPATCH_FINISH + .endm + + Opcode iload_0_castore + iload_0_castore +@----------------------------------------------------------------------------- + .macro iload_iastore jpc_off=0, seq_len=3 + POP2 r3, tmp1 + DISPATCH_START \seq_len + ldr r2, [locals, -r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry30: + ldr lr, [tmp1, #8] @ lr = limit + DISPATCH_NEXT + cmp r3, lr + bcs array_bound_exception_jpc_1_r3 + DISPATCH_NEXT + add tmp1, tmp1, r3, lsl #2 + str r2, [tmp1, #12] + DISPATCH_FINISH + .endm + + Opcode iload_iastore + iload_iastore +@----------------------------------------------------------------------------- + .macro iload_bastore jpc_off=0, seq_len=3 + POP2 r3, tmp1 + DISPATCH_START \seq_len + ldr r2, [locals, -r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry31: + ldr lr, [tmp1, #8] @ lr = limit + DISPATCH_NEXT + cmp r3, lr + bcs array_bound_exception_jpc_1_r3 + DISPATCH_NEXT + add tmp1, tmp1, r3 + strb r2, [tmp1, #12] + DISPATCH_FINISH + .endm + + Opcode iload_bastore + iload_bastore +@----------------------------------------------------------------------------- + .macro iload_castore jpc_off=0, seq_len=3 + POP2 r3, tmp1 + DISPATCH_START \seq_len + ldr r2, [locals, -r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry32: + ldr lr, [tmp1, #8] @ lr = limit + DISPATCH_NEXT + cmp r3, lr + bcs array_bound_exception_jpc_1_r3 + DISPATCH_NEXT + add tmp1, tmp1, r3, lsl #1 + strh r2, [tmp1, #12] + DISPATCH_FINISH + .endm + + Opcode iload_castore + iload_castore +@----------------------------------------------------------------------------- + .macro iload_0_iadd jpc_off=0, seq_len=2 + POP tmp2 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + add tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_0_iadd + iload_0_iadd +@----------------------------------------------------------------------------- + .macro iload_iadd jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + POP tmp1 + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iload_iadd + iload_iadd +@----------------------------------------------------------------------------- + .macro iload_0_isub jpc_off=0, seq_len=2 + POP tmp2 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + sub tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_0_isub + iload_0_isub +@----------------------------------------------------------------------------- + .macro iload_isub jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + POP tmp1 + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iload_isub + iload_isub +@----------------------------------------------------------------------------- + .macro iload_0_imul jpc_off=0, seq_len=2 + POP r2 + rsb lr, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr lr, [locals, lr, lsl #2] + DISPATCH_NEXT + mul r3, r2, lr + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode iload_0_imul + iload_0_imul +@----------------------------------------------------------------------------- + .macro iload_imul jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_NEXT + mul lr, r3, r2 + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_imul + iload_imul +@----------------------------------------------------------------------------- + .macro iload_0_idiv jpc_off=0, seq_len=2 + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + add jpc, jpc, #1 + POP r1 + b int_div + .endm + + Opcode iload_0_idiv + iload_0_idiv +@----------------------------------------------------------------------------- + .macro iload_idiv jpc_off=0, seq_len=3 + add jpc, jpc, #2 + POP r1 + ldr r0, [locals, -r2, lsl #2] + b int_div + .endm + + Opcode iload_idiv + iload_idiv +@----------------------------------------------------------------------------- + .macro iload_0_irem jpc_off=0, seq_len=2 + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + add jpc, jpc, #1 + POP r1 + b int_rem + .endm + + Opcode iload_0_irem + iload_0_irem +@----------------------------------------------------------------------------- + .macro iload_irem jpc_off=0, seq_len=3 + ldr r0, [locals, -r2, lsl #2] + add jpc, jpc, #2 + POP r1 + b int_rem + .endm + + Opcode iload_irem + iload_irem +@----------------------------------------------------------------------------- + .macro iload_0_ineg jpc_off=0, seq_len=2 + rsb lr, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr lr, [locals, lr, lsl #2] + DISPATCH_NEXT + rsb lr, lr, #0 + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_0_ineg + iload_0_ineg +@----------------------------------------------------------------------------- + .macro iload_ineg jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + ldr r2, [locals, -r2, lsl #2] + DISPATCH_NEXT + rsb r2, r2, #0 + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode iload_ineg + iload_ineg +@----------------------------------------------------------------------------- + .macro iload_0_ishl jpc_off=0, seq_len=2 + POP r2 + rsb lr, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr lr, [locals, lr, lsl #2] + DISPATCH_NEXT + mov lr, r2, lsl lr + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_0_ishl + iload_0_ishl +@----------------------------------------------------------------------------- + .macro iload_ishl jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_NEXT + mov r2, r3, lsl r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode iload_ishl + iload_ishl +@----------------------------------------------------------------------------- + .macro iload_0_ishr jpc_off=0, seq_len=2 + POP r2 + rsb lr, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr lr, [locals, lr, lsl #2] + DISPATCH_NEXT + mov lr, r2, asr lr + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_0_ishr + iload_0_ishr +@----------------------------------------------------------------------------- + .macro iload_ishr jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_NEXT + mov r2, r3, asr r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode iload_ishr + iload_ishr +@----------------------------------------------------------------------------- + .macro iload_0_iushr jpc_off=0, seq_len=2 + POP r2 + rsb lr, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr lr, [locals, lr, lsl #2] + DISPATCH_NEXT + mov lr, r2, lsr lr + DISPATCH_NEXT + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_0_iushr + iload_0_iushr +@----------------------------------------------------------------------------- + .macro iload_iushr jpc_off=0, seq_len=3 + ldrb r2, [jpc, #1] + DISPATCH_START \seq_len + POP r3 + ldr r2, [locals, -r2, lsl #2] + DISPATCH_NEXT + mov r2, r3, lsr r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode iload_iushr + iload_iushr +@----------------------------------------------------------------------------- + .macro iload_0_iand jpc_off=0, seq_len=2 + POP tmp2 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + and tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_0_iand + iload_0_iand +@----------------------------------------------------------------------------- + .macro iload_iand jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + POP tmp1 + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + and tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iload_iand + iload_iand +@----------------------------------------------------------------------------- + .macro iload_0_ior jpc_off=0, seq_len=2 + POP tmp2 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + orr tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_0_ior + iload_0_ior +@----------------------------------------------------------------------------- + .macro iload_ior jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + POP tmp1 + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + orr tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iload_ior + iload_ior +@----------------------------------------------------------------------------- + .macro iload_0_ixor jpc_off=0, seq_len=2 + POP tmp2 + rsb tmp1, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr tmp1, [locals, tmp1, lsl #2] + DISPATCH_NEXT + eor tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iload_0_ixor + iload_0_ixor +@----------------------------------------------------------------------------- + .macro iload_ixor jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + POP tmp1 + DISPATCH_NEXT + ldr tmp2, [locals, tmp2, lsl #2] + DISPATCH_NEXT + eor tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iload_ixor + iload_ixor +@----------------------------------------------------------------------------- + .macro iload_0_i2c jpc_off=0, seq_len=2 + rsb lr, r0, #opc_iload_0 + DISPATCH_START \seq_len + ldr lr, [locals, lr, lsl #2] + DISPATCH_NEXT + mov lr, lr, asl #16 + mov lr, lr, lsr #16 + PUSH lr + DISPATCH_FINISH + .endm + + Opcode iload_0_i2c + iload_0_i2c +@----------------------------------------------------------------------------- + .macro iload_i2c jpc_off=0, seq_len=3 + DISPATCH_START \seq_len + ldr r2, [locals, -r2, lsl #2] + DISPATCH_NEXT + mov r2, r2, asl #16 + mov r2, r2, lsr #16 + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode iload_i2c + iload_i2c +@----------------------------------------------------------------------------- + .macro iload_0_ifeq jpc_off=0, seq_len=1 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + rsb r3, r0, #opc_iload_0 + add jpc, jpc, #1 + ldr r3, [locals, r3, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_0_ifeq + iload_0_ifeq +@----------------------------------------------------------------------------- + .macro iload_ifeq jpc_off=0, seq_len=2 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + add jpc, jpc, #2 + ldr r3, [locals, -r2, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_ifeq + iload_ifeq +@----------------------------------------------------------------------------- + .macro iload_0_ifne jpc_off=0, seq_len=1 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + rsb r3, r0, #opc_iload_0 + add jpc, jpc, #1 + ldr r3, [locals, r3, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_0_ifne + iload_0_ifne +@----------------------------------------------------------------------------- + .macro iload_ifne jpc_off=0, seq_len=2 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + add jpc, jpc, #2 + ldr r3, [locals, -r2, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_ifne + iload_ifne +@----------------------------------------------------------------------------- + .macro iload_0_iflt jpc_off=0, seq_len=1 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + rsb r3, r0, #opc_iload_0 + add jpc, jpc, #1 + ldr r3, [locals, r3, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_0_iflt + iload_0_iflt +@----------------------------------------------------------------------------- + .macro iload_iflt jpc_off=0, seq_len=2 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + add jpc, jpc, #2 + ldr r3, [locals, -r2, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_iflt + iload_iflt +@----------------------------------------------------------------------------- + .macro iload_0_ifge jpc_off=0, seq_len=1 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + rsb r3, r0, #opc_iload_0 + add jpc, jpc, #1 + ldr r3, [locals, r3, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_0_ifge + iload_0_ifge +@----------------------------------------------------------------------------- + .macro iload_ifge jpc_off=0, seq_len=2 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + add jpc, jpc, #2 + ldr r3, [locals, -r2, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_ifge + iload_ifge +@----------------------------------------------------------------------------- + .macro iload_0_ifgt jpc_off=0, seq_len=1 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + rsb r3, r0, #opc_iload_0 + add jpc, jpc, #1 + ldr r3, [locals, r3, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_0_ifgt + iload_0_ifgt +@----------------------------------------------------------------------------- + .macro iload_ifgt jpc_off=0, seq_len=2 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + add jpc, jpc, #2 + ldr r3, [locals, -r2, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_ifgt + iload_ifgt +@----------------------------------------------------------------------------- + .macro iload_0_ifle jpc_off=0, seq_len=1 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + rsb r3, r0, #opc_iload_0 + add jpc, jpc, #1 + ldr r3, [locals, r3, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_0_ifle + iload_0_ifle +@----------------------------------------------------------------------------- + .macro iload_ifle jpc_off=0, seq_len=2 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + add jpc, jpc, #2 + ldr r3, [locals, -r2, lsl #2] + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_ifle + iload_ifle +@----------------------------------------------------------------------------- + .macro iload_0_if_icmpeq jpc_off=0, seq_len=1 + POP r3 + rsb r2, r0, #opc_iload_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + ldr r2, [locals, r2, lsl #2] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_0_if_icmpeq + iload_0_if_icmpeq +@----------------------------------------------------------------------------- + .macro iload_if_icmpeq jpc_off=0, seq_len=2 + POP r3 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + ldr r2, [locals, -r2, lsl #2] + add jpc, jpc, #2 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_if_icmpeq + iload_if_icmpeq +@----------------------------------------------------------------------------- + .macro iload_0_if_icmpne jpc_off=0, seq_len=1 + POP r3 + rsb r2, r0, #opc_iload_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + ldr r2, [locals, r2, lsl #2] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_0_if_icmpne + iload_0_if_icmpne +@----------------------------------------------------------------------------- + .macro iload_if_icmpne jpc_off=0, seq_len=2 + POP r3 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + ldr r2, [locals, -r2, lsl #2] + add jpc, jpc, #2 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_if_icmpne + iload_if_icmpne +@----------------------------------------------------------------------------- + .macro iload_0_if_icmplt jpc_off=0, seq_len=1 + POP r3 + rsb r2, r0, #opc_iload_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + ldr r2, [locals, r2, lsl #2] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_0_if_icmplt + iload_0_if_icmplt +@----------------------------------------------------------------------------- + .macro iload_if_icmplt jpc_off=0, seq_len=2 + POP r3 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + ldr r2, [locals, -r2, lsl #2] + add jpc, jpc, #2 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_if_icmplt + iload_if_icmplt +@----------------------------------------------------------------------------- + .macro iload_0_if_icmpge jpc_off=0, seq_len=1 + POP r3 + rsb r2, r0, #opc_iload_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + ldr r2, [locals, r2, lsl #2] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_0_if_icmpge + iload_0_if_icmpge +@----------------------------------------------------------------------------- + .macro iload_if_icmpge jpc_off=0, seq_len=2 + POP r3 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + ldr r2, [locals, -r2, lsl #2] + add jpc, jpc, #2 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_if_icmpge + iload_if_icmpge +@----------------------------------------------------------------------------- + .macro iload_0_if_icmpgt jpc_off=0, seq_len=1 + POP r3 + rsb r2, r0, #opc_iload_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + ldr r2, [locals, r2, lsl #2] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_0_if_icmpgt + iload_0_if_icmpgt +@----------------------------------------------------------------------------- + .macro iload_if_icmpgt jpc_off=0, seq_len=2 + POP r3 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + ldr r2, [locals, -r2, lsl #2] + add jpc, jpc, #2 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_if_icmpgt + iload_if_icmpgt +@----------------------------------------------------------------------------- + .macro iload_0_if_icmple jpc_off=0, seq_len=1 + POP r3 + rsb r2, r0, #opc_iload_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + ldr r2, [locals, r2, lsl #2] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_0_if_icmple + iload_0_if_icmple +@----------------------------------------------------------------------------- + .macro iload_if_icmple jpc_off=0, seq_len=2 + POP r3 + ldrsb r1, [jpc, #3] + ldrb ip, [jpc, #4] + ldr r2, [locals, -r2, lsl #2] + add jpc, jpc, #2 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iload_if_icmple + iload_if_icmple +@----------------------------------------------------------------------------- + .macro iload_0_ireturn jpc_off=0, seq_len=1 + rsb r0, r0, #opc_iload_0 + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + ldr r1, [locals, r0, lsl #2] + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b + .endm + + Opcode iload_0_ireturn + iload_0_ireturn +@----------------------------------------------------------------------------- + .macro iload_ireturn jpc_off=0, seq_len=2 + + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + ldr r1, [locals, -r2, lsl #2] + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #2 + bl return_check_monitors + POP r1 + b 2b + .endm + + Opcode iload_ireturn + iload_ireturn +@----------------------------------------------------------------------------- + .macro iload_0_invokeresolved jpc_off=0, seq_len=4 + add jpc, jpc, #1 + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokeresolved + .endm + + Opcode iload_0_invokeresolved + iload_0_invokeresolved +@----------------------------------------------------------------------------- + .macro aload_0_invokeresolved jpc_off=0, seq_len=4 + add jpc, jpc, #1 + rsb r0, r0, #opc_aload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokeresolved + .endm + + Opcode aload_0_invokeresolved + aload_0_invokeresolved +@----------------------------------------------------------------------------- + .macro iload_invokeresolved jpc_off=0, seq_len=5 + ldr r0, [locals, -r2, lsl #2] + add jpc, jpc, #2 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokeresolved + .endm + + Opcode iload_invokeresolved + iload_invokeresolved +@----------------------------------------------------------------------------- + .macro iload_0_invokevfinal jpc_off=0, seq_len=4 + add jpc, jpc, #1 + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokevfinal + .endm + + Opcode iload_0_invokevfinal + iload_0_invokevfinal +@----------------------------------------------------------------------------- + .macro aload_0_invokevfinal jpc_off=0, seq_len=4 + add jpc, jpc, #1 + rsb r0, r0, #opc_aload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokevfinal + .endm + + Opcode aload_0_invokevfinal + aload_0_invokevfinal +@----------------------------------------------------------------------------- + .macro iload_invokevfinal jpc_off=0, seq_len=5 + ldr r0, [locals, -r2, lsl #2] + add jpc, jpc, #2 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokevfinal + .endm + + Opcode iload_invokevfinal + iload_invokevfinal +@----------------------------------------------------------------------------- + .macro iload_0_invokespecialresolved jpc_off=0, seq_len=4 + add jpc, jpc, #1 + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokespecialresolved + .endm + + Opcode iload_0_invokespecialresolved + iload_0_invokespecialresolved +@----------------------------------------------------------------------------- + .macro aload_0_invokespecialresolved jpc_off=0, seq_len=4 + add jpc, jpc, #1 + rsb r0, r0, #opc_aload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokespecialresolved + .endm + + Opcode aload_0_invokespecialresolved + aload_0_invokespecialresolved +@----------------------------------------------------------------------------- + .macro iload_invokespecialresolved jpc_off=0, seq_len=5 + ldr r0, [locals, -r2, lsl #2] + add jpc, jpc, #2 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokespecialresolved + .endm + + Opcode iload_invokespecialresolved + iload_invokespecialresolved +@----------------------------------------------------------------------------- + .macro iload_0_invokestaticresolved jpc_off=0, seq_len=4 + add jpc, jpc, #1 + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokestaticresolved + .endm + + Opcode iload_0_invokestaticresolved + iload_0_invokestaticresolved +@----------------------------------------------------------------------------- + .macro aload_0_invokestaticresolved jpc_off=0, seq_len=4 + add jpc, jpc, #1 + rsb r0, r0, #opc_aload_0 + ldr r0, [locals, r0, lsl #2] + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokestaticresolved + .endm + + Opcode aload_0_invokestaticresolved + aload_0_invokestaticresolved +@----------------------------------------------------------------------------- + .macro iload_invokestaticresolved jpc_off=0, seq_len=5 + ldr r0, [locals, -r2, lsl #2] + add jpc, jpc, #2 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokestaticresolved + .endm + + Opcode iload_invokestaticresolved + iload_invokestaticresolved +@----------------------------------------------------------------------------- + .macro iload_0_invokeinterface jpc_off=0, seq_len=1 + add jpc, jpc, #1 + rsb r0, r0, #opc_iload_0 + ldr r0, [locals, r0, lsl #2] + PUSH r0 + b do_invokeinterface + .endm + + Opcode iload_0_invokeinterface + iload_0_invokeinterface +@----------------------------------------------------------------------------- + .macro aload_0_invokeinterface jpc_off=0, seq_len=1 + add jpc, jpc, #1 + rsb r0, r0, #opc_aload_0 + ldr r0, [locals, r0, lsl #2] + PUSH r0 + b do_invokeinterface + .endm + + Opcode aload_0_invokeinterface + aload_0_invokeinterface +@----------------------------------------------------------------------------- + .macro iload_invokeinterface jpc_off=0, seq_len=2 + ldr r0, [locals, -r2, lsl #2] + add jpc, jpc, #2 + PUSH r0 + b do_invokeinterface + .endm + + Opcode iload_invokeinterface + iload_invokeinterface +@----------------------------------------------------------------------------- + .macro aload_0_igetfield jpc_off=0, seq_len=4 + add r0, r0, #opc_iaccess_0-opc_aload_0 + strb r0, [jpc] + DISPATCH_BYTECODE + .endm + + Opcode aload_0_igetfield + aload_0_igetfield +@----------------------------------------------------------------------------- + .macro iload_igetfield jpc_off=0, seq_len=5 + ldrb ip, [jpc, #4] + rsb tmp1, r2, #0 + ldrb r3, [jpc, #3] + add tmp2, constpool, ip, lsl #12 + DISPATCH_START 5 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, r3, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + DISPATCH_NEXT + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry88: + ldr tmp2, [tmp1, tmp2] + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iload_igetfield + iload_igetfield +@----------------------------------------------------------------------------- + .macro iconst_m1_istore_0 jpc_off=0, seq_len=2 + sub r3, r0, #opc_iconst_0 + DISPATCH_START \seq_len + rsb r2, r1, #opc_istore_0 + str r3, [locals, r2, lsl #2] + DISPATCH_BYTECODE + .endm + + Opcode iconst_m1_istore_0 + iconst_m1_istore_0 +@----------------------------------------------------------------------------- + .macro iconst_m1_astore jpc_off=0, seq_len=3 + ldrb r2, [jpc, #2] + sub r3, r0, #opc_iconst_0 + DISPATCH_START \seq_len + str r3, [locals, -r2, lsl #2] + DISPATCH_BYTECODE + .endm + + Opcode iconst_m1_astore + iconst_m1_astore +@----------------------------------------------------------------------------- + .macro iconst_m1_iadd jpc_off=0, seq_len=2 + sub tmp1, r0, #opc_iconst_0 + DISPATCH_START \seq_len + POP tmp2 + DISPATCH_NEXT + add tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iconst_m1_iadd + iconst_m1_iadd +@----------------------------------------------------------------------------- + .macro iconst_m1_isub jpc_off=0, seq_len=2 + sub tmp1, r0, #opc_iconst_0 + DISPATCH_START \seq_len + POP tmp2 + DISPATCH_NEXT + sub tmp1, tmp2, tmp1 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iconst_m1_isub + iconst_m1_isub +@----------------------------------------------------------------------------- + .macro iconst_m1_idiv jpc_off=0, seq_len=2 + subs lr, r0, #opc_iconst_2 + DISPATCH_START \seq_len + POP tmp1 + DISPATCH_NEXT + beq 5f + bcc 3f + cmp lr, #(opc_iconst_4-opc_iconst_2) + beq 4f + bcc 2f +@ divide by 5 +1: + mvn lr, #0x198 @ Form 0x66666667 in lr + bic lr, lr, #0x9800 + add lr, lr, lr, lsl #16 + smull a3, a4, tmp1, lr + mov a3, tmp1, asr #31 + rsb tmp1, a3, a4, asr #1 + b 6f +@ divide by 3 +2: + mvn lr, #0xa9 @ Form 0x55555556 in lr + bic lr, lr, #0xaa00 + add lr, lr, lr, lsl #16 + smull a3, a4, tmp1, lr + sub tmp1, a4, tmp1, asr #31 + b 6f +3: + cmp lr, #(opc_iconst_0-opc_iconst_2) + beq .iconst_div_rem_0 + rsbcc tmp1, tmp1, #0 @ Divide by -1 or 1 + b 6f +@ divide by 4 +4: movs a4, tmp1 + addmi a4, a4, #3 + mov tmp1, a4, asr #2 + b 6f +@ divide by 2 +5: + add tmp1, tmp1, tmp1, lsr #31 + mov tmp1, tmp1, asr #1 +6: + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iconst_m1_idiv + iconst_m1_idiv +@----------------------------------------------------------------------------- + .macro iconst_m1_ishl jpc_off=0, seq_len=2 + sub tmp1, r0, #opc_iconst_0 + DISPATCH_START \seq_len + POP r2 + DISPATCH_NEXT + mov tmp1, r2, lsl tmp1 + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iconst_m1_ishl + iconst_m1_ishl +@----------------------------------------------------------------------------- + .macro iconst_m1_if_icmpeq jpc_off=0, seq_len=1 + POP r3 + sub r2, r0, #opc_iconst_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iconst_m1_if_icmpeq + iconst_m1_if_icmpeq +@----------------------------------------------------------------------------- + .macro iconst_m1_if_icmpne jpc_off=0, seq_len=1 + POP r3 + sub r2, r0, #opc_iconst_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iconst_m1_if_icmpne + iconst_m1_if_icmpne +@----------------------------------------------------------------------------- + .macro iconst_m1_if_icmplt jpc_off=0, seq_len=1 + POP r3 + sub r2, r0, #opc_iconst_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iconst_m1_if_icmplt + iconst_m1_if_icmplt +@----------------------------------------------------------------------------- + .macro iconst_m1_if_icmpge jpc_off=0, seq_len=1 + POP r3 + sub r2, r0, #opc_iconst_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iconst_m1_if_icmpge + iconst_m1_if_icmpge +@----------------------------------------------------------------------------- + .macro iconst_m1_if_icmpgt jpc_off=0, seq_len=1 + POP r3 + sub r2, r0, #opc_iconst_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iconst_m1_if_icmpgt + iconst_m1_if_icmpgt +@----------------------------------------------------------------------------- + .macro iconst_m1_if_icmple jpc_off=0, seq_len=1 + POP r3 + sub r2, r0, #opc_iconst_0 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iconst_m1_if_icmple + iconst_m1_if_icmple +@----------------------------------------------------------------------------- + .macro iconst_m1_ireturn jpc_off=0, seq_len=1 + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + sub r1, r0, #opc_iconst_0 + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b + .endm + + Opcode iconst_m1_ireturn + iconst_m1_ireturn +@----------------------------------------------------------------------------- + .macro iconst_m1_invokeresolved jpc_off=0, seq_len=4 + add jpc, jpc, #1 + sub r0, r0, #opc_iconst_0 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokeresolved + .endm + + Opcode iconst_m1_invokeresolved + iconst_m1_invokeresolved +@----------------------------------------------------------------------------- + .macro iconst_m1_invokevfinal jpc_off=0, seq_len=4 + add jpc, jpc, #1 + sub r0, r0, #opc_iconst_0 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokevfinal + .endm + + Opcode iconst_m1_invokevfinal + iconst_m1_invokevfinal +@----------------------------------------------------------------------------- + .macro iconst_m1_invokestaticresolved jpc_off=0, seq_len=4 + add jpc, jpc, #1 + sub r0, r0, #opc_iconst_0 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokestaticresolved + .endm + + Opcode iconst_m1_invokestaticresolved + iconst_m1_invokestaticresolved +@----------------------------------------------------------------------------- + .macro iconst_m1_invokespecialresolved jpc_off=0, seq_len=4 + add jpc, jpc, #1 + sub r0, r0, #opc_iconst_0 + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] + PUSH r0 + b do_invokespecialresolved + .endm + + Opcode iconst_m1_invokespecialresolved + iconst_m1_invokespecialresolved +@----------------------------------------------------------------------------- + .macro iaload_iconst_m1 jpc_off=0, seq_len=2 + sub r2, r1, #opc_iconst_0 + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry38: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode iaload_iconst_m1 + iaload_iconst_m1 +@----------------------------------------------------------------------------- + .macro iaload_bipush jpc_off=0, seq_len=3 + ldrsb r2, [jpc, #2] + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_3 +#endif +.abortentry39: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_3_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode iaload_bipush + iaload_bipush +@----------------------------------------------------------------------------- + .macro iaload_sipush jpc_off=0, seq_len=4 + ldrsb r2, [jpc, #2] + ldrb tmp1, [jpc, #3] + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len + orr r2, tmp1, r2, lsl #8 +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_4 +#endif +.abortentry40: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_4_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode iaload_sipush + iaload_sipush +@----------------------------------------------------------------------------- + .macro iaload_iload jpc_off=0, seq_len=3 + ldrb r2, [jpc, #2] + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len + ldr r2, [locals, -r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_3 +#endif +.abortentry41: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_3_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode iaload_iload + iaload_iload +@----------------------------------------------------------------------------- + .macro iaload_iload_0 jpc_off=0, seq_len=2 + rsb r2, r1, #opc_iload_0 + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len + ldr r2, [locals, r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry42: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode iaload_iload_0 + iaload_iload_0 +@----------------------------------------------------------------------------- + .macro iaload_aload_0 jpc_off=0, seq_len=2 + rsb r2, r1, #opc_aload_0 + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len + ldr r2, [locals, r2, lsl #2] +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry42_1: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + PUSH2 r2, r3 + DISPATCH_FINISH + .endm + + Opcode iaload_aload_0 + iaload_aload_0 +@----------------------------------------------------------------------------- + .macro iaload_iaload jpc_off=0, seq_len=2 + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry43: + ldr tmp1, [r3, #8] @ tmp1 = length + DISPATCH_START \seq_len + cmp r2, tmp1 + bcs array_bound_exception_jpc_2 + add r3, r3, r2, lsl #2 + POP lr @ r2 = index, lr = arrayref + ldr r2, [r3, #12] +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry44: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_1 + add lr, lr, r2, lsl #2 + ldr r2, [lr, #12] + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode iaload_iaload + iaload_iaload +@----------------------------------------------------------------------------- + .macro iaload_astore jpc_off=0, seq_len=3 + ldrb r2, [jpc, #2] + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_3 +#endif +.abortentry45: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_3_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + str r3, [locals, -r2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iaload_astore + iaload_astore +@----------------------------------------------------------------------------- + .macro iaload_istore_0 jpc_off=0, seq_len=2 + rsb r2, r1, #opc_istore_0 + POP2 r3, lr @ r3 = index, lr = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry46: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr r3, [lr, #12] + DISPATCH_NEXT + str r3, [locals, r2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iaload_istore_0 + iaload_istore_0 +@----------------------------------------------------------------------------- + .macro iaload_iastore jpc_off=0, seq_len=2 + POP2 r3, lr @ r3 = index, lr = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry47: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_START \seq_len + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr tmp1, [lr, #12] + + POP2 r2, r3 @ tmp1 = value, r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry48: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH + .endm + + Opcode iaload_iastore + iaload_iastore +@----------------------------------------------------------------------------- + .macro iaload_bastore jpc_off=0, seq_len=2 + POP2 r3, lr @ r3 = index, lr = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry49: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_START \seq_len + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr tmp1, [lr, #12] + + POP2 r2, r3 @ tmp1 = value, r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry50: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2 + strb tmp1, [r3, #12] + DISPATCH_FINISH + .endm + + Opcode iaload_bastore + iaload_bastore +@----------------------------------------------------------------------------- + .macro iaload_castore jpc_off=0, seq_len=2 + POP2 r3, lr @ r3 = index, lr = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry51: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_START \seq_len + cmp r3, tmp1 + bcs array_bound_exception_jpc_2_r3 + add lr, lr, r3, lsl #2 + ldr tmp1, [lr, #12] + + POP2 r2, r3 @ tmp1 = value, r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry52: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #1 + strh tmp1, [r3, #12] + DISPATCH_FINISH + .endm + + Opcode iaload_castore + iaload_castore +@----------------------------------------------------------------------------- + .macro iaload_iand jpc_off=0, seq_len=2 + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry58: + ldr tmp1, [r3, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_2 + add r3, r3, r2, lsl #2 + ldr tmp1, [r3, #12] @ tmp1 = tos + POP r2 @ r2 = tosm1 + DISPATCH_NEXT + and tmp1, r2, tmp1 @ tosm1 <dop> tos + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iaload_iand + iaload_iand +@----------------------------------------------------------------------------- + .macro iaload_ior jpc_off=0, seq_len=2 + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry59: + ldr tmp1, [r3, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_2 + add r3, r3, r2, lsl #2 + ldr tmp1, [r3, #12] @ tmp1 = tos + POP r2 @ r2 = tosm1 + DISPATCH_NEXT + orr tmp1, r2, tmp1 @ tosm1 <dop> tos + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iaload_ior + iaload_ior +@----------------------------------------------------------------------------- + .macro iaload_ixor jpc_off=0, seq_len=2 + POP2 r2, r3 @ r2 = index, r3 = arrayref + DISPATCH_START \seq_len +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_2 +#endif +.abortentry60: + ldr tmp1, [r3, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_2 + add r3, r3, r2, lsl #2 + ldr tmp1, [r3, #12] @ tmp1 = tos + POP r2 @ r2 = tosm1 + DISPATCH_NEXT + eor tmp1, r2, tmp1 @ tosm1 <dop> tos + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iaload_ixor + iaload_ixor +@----------------------------------------------------------------------------- + .macro iaload_ifeq jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry61: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r3, [r3, #12] @ r1 = tos + + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaload_ifeq + iaload_ifeq +@----------------------------------------------------------------------------- + .macro iaload_ifne jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry62: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r3, [r3, #12] @ r1 = tos + + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaload_ifne + iaload_ifne +@----------------------------------------------------------------------------- + .macro iaload_iflt jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry63: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r3, [r3, #12] @ r1 = tos + + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaload_iflt + iaload_iflt +@----------------------------------------------------------------------------- + .macro iaload_ifge jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry64: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r3, [r3, #12] @ r1 = tos + + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaload_ifge + iaload_ifge +@----------------------------------------------------------------------------- + .macro iaload_ifgt jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry65: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r3, [r3, #12] @ r1 = tos + + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaload_ifgt + iaload_ifgt +@----------------------------------------------------------------------------- + .macro iaload_ifle jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry66: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r3, [r3, #12] @ r1 = tos + + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaload_ifle + iaload_ifle +@----------------------------------------------------------------------------- + .macro iaload_if_icmpeq jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry67: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r2, [r3, #12] @ r1 = tos + + POP r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaload_if_icmpeq + iaload_if_icmpeq +@----------------------------------------------------------------------------- + .macro iaload_if_icmpne jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry68: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r2, [r3, #12] @ r1 = tos + + POP r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaload_if_icmpne + iaload_if_icmpne +@----------------------------------------------------------------------------- + .macro iaload_if_icmplt jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry69: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r2, [r3, #12] @ r1 = tos + + POP r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaload_if_icmplt + iaload_if_icmplt +@----------------------------------------------------------------------------- + .macro iaload_if_icmpge jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry70: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r2, [r3, #12] @ r1 = tos + + POP r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaload_if_icmpge + iaload_if_icmpge +@----------------------------------------------------------------------------- + .macro iaload_if_icmpgt jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry71: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r2, [r3, #12] @ r1 = tos + + POP r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaload_if_icmpgt + iaload_if_icmpgt +@----------------------------------------------------------------------------- + .macro iaload_if_icmple jpc_off=0, seq_len=1 + POP2 r2, r3 @ r2 = index, r3 = arrayref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_0 +#endif +.abortentry72: + ldr r1, [r3, #8] @ r1 = length + cmp r2, r1 + bcs array_bound_exception_jpc_0 + add r3, r3, r2, lsl #2 + ldr r2, [r3, #12] @ r1 = tos + + POP r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + cmp r3, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaload_if_icmple + iaload_if_icmple +@----------------------------------------------------------------------------- + .macro iadd_iload jpc_off=0, seq_len=3 + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH + .endm + + Opcode iadd_iload + iadd_iload +@----------------------------------------------------------------------------- + .macro iadd_iload_0 jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + rsb r3, r1, #opc_iload_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH + .endm + + Opcode iadd_iload_0 + iadd_iload_0 +@----------------------------------------------------------------------------- + .macro iadd_iaload jpc_off=0, seq_len=2 + POP3 r2, r3, lr @ lr = ref + DISPATCH_START \seq_len + add r2, r3, r2 @ r2 = index +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry73: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_1 + add lr, lr, r2, lsl #2 + ldr tmp1, [lr, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iadd_iaload + iadd_iaload +@----------------------------------------------------------------------------- + .macro iadd_istore jpc_off=0, seq_len=3 + mov r0, #opc_iadd_u4store + strb r0, [jpc] + b do_iadd_u4store + .endm + + Opcode iadd_istore + iadd_istore +@----------------------------------------------------------------------------- + .macro iadd_istore_0 jpc_off=0, seq_len=2 + mov r0, #opc_iadd_istore_N + strb r0, [jpc] + b do_iadd_istore_N + .endm + + Opcode iadd_istore_0 + iadd_istore_0 +@----------------------------------------------------------------------------- + .macro iadd_iastore jpc_off=0, seq_len=2 + POP2 r2, r3 + DISPATCH_START \seq_len + add tmp1, r3, r2 @ tmp1 = value + POP2 r2, r3 @ r2, index, r3 = ref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry106: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH + .endm + + Opcode iadd_iastore + iadd_iastore +@----------------------------------------------------------------------------- + .macro iadd_iadd jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + add tmp2, r3, r2 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iadd_iadd + iadd_iadd +@----------------------------------------------------------------------------- + .macro iadd_isub jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + add tmp2, r3, r2 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iadd_isub + iadd_isub +@----------------------------------------------------------------------------- + .macro iadd_ifeq jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iadd_ifeq + iadd_ifeq +@----------------------------------------------------------------------------- + .macro iadd_ifne jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iadd_ifne + iadd_ifne +@----------------------------------------------------------------------------- + .macro iadd_iflt jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iadd_iflt + iadd_iflt +@----------------------------------------------------------------------------- + .macro iadd_ifge jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iadd_ifge + iadd_ifge +@----------------------------------------------------------------------------- + .macro iadd_ifgt jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iadd_ifgt + iadd_ifgt +@----------------------------------------------------------------------------- + .macro iadd_ifle jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iadd_ifle + iadd_ifle +@----------------------------------------------------------------------------- + .macro iadd_if_icmpeq jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iadd_if_icmpeq + iadd_if_icmpeq +@----------------------------------------------------------------------------- + .macro iadd_if_icmpne jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iadd_if_icmpne + iadd_if_icmpne +@----------------------------------------------------------------------------- + .macro iadd_if_icmplt jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iadd_if_icmplt + iadd_if_icmplt +@----------------------------------------------------------------------------- + .macro iadd_if_icmpge jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iadd_if_icmpge + iadd_if_icmpge +@----------------------------------------------------------------------------- + .macro iadd_if_icmpgt jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iadd_if_icmpgt + iadd_if_icmpgt +@----------------------------------------------------------------------------- + .macro iadd_if_icmple jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iadd_if_icmple + iadd_if_icmple +@----------------------------------------------------------------------------- + .macro iadd_goto jpc_off=0, seq_len=1 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + orr ip, ip, r1, lsl #8 + DISPATCH_START_REG ip + POP2 r2, r3 + add r2, r3, r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode iadd_goto + iadd_goto +@----------------------------------------------------------------------------- + .macro iadd_ireturn jpc_off=0, seq_len=1 + POP2 r2, r3 + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + add r1, r3, r2 + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b + .endm + + Opcode iadd_ireturn + iadd_ireturn +@----------------------------------------------------------------------------- + .macro iadd_iinc jpc_off=0, seq_len=4 + POP2 tmp1, lr + DISPATCH_START \seq_len + add tmp1, lr, tmp1 + ldrb r3, [jpc, #-2] @ ECN: jpc now points to next bc + ldrsb r2, [jpc, #-1] + DISPATCH_NEXT + PUSH tmp1 + ldr tmp1, [locals, -r3, lsl #2] + DISPATCH_NEXT + add tmp1, tmp1, r2 + str tmp1, [locals, -r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iadd_iinc + iadd_iinc +@----------------------------------------------------------------------------- + .macro isub_iload jpc_off=0, seq_len=3 + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH + .endm + + Opcode isub_iload + isub_iload +@----------------------------------------------------------------------------- + .macro isub_iload_0 jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + rsb r3, r1, #opc_iload_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH + .endm + + Opcode isub_iload_0 + isub_iload_0 +@----------------------------------------------------------------------------- + .macro isub_iaload jpc_off=0, seq_len=2 + POP3 r2, r3, lr @ lr = ref + DISPATCH_START \seq_len + sub r2, r3, r2 @ r2 = index +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry74: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_1 + add lr, lr, r2, lsl #2 + ldr tmp1, [lr, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode isub_iaload + isub_iaload +@----------------------------------------------------------------------------- + .macro isub_istore jpc_off=0, seq_len=3 + mov r0, #opc_isub_u4store + strb r0, [jpc] + b do_isub_u4store + .endm + + Opcode isub_istore + isub_istore +@----------------------------------------------------------------------------- + .macro isub_istore_0 jpc_off=0, seq_len=2 + mov r0, #opc_isub_istore_N + strb r0, [jpc] + b do_isub_istore_N + .endm + + Opcode isub_istore_0 + isub_istore_0 +@----------------------------------------------------------------------------- + .macro isub_iastore jpc_off=0, seq_len=2 + POP2 r2, r3 + DISPATCH_START \seq_len + sub tmp1, r3, r2 @ tmp1 = value + POP2 r2, r3 @ r2, index, r3 = ref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry105: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH + .endm + + Opcode isub_iastore + isub_iastore +@----------------------------------------------------------------------------- + .macro isub_iadd jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + sub tmp2, r3, r2 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode isub_iadd + isub_iadd +@----------------------------------------------------------------------------- + .macro isub_isub jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + sub tmp2, r3, r2 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode isub_isub + isub_isub +@----------------------------------------------------------------------------- + .macro isub_ifeq jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode isub_ifeq + isub_ifeq +@----------------------------------------------------------------------------- + .macro isub_ifne jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode isub_ifne + isub_ifne +@----------------------------------------------------------------------------- + .macro isub_iflt jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode isub_iflt + isub_iflt +@----------------------------------------------------------------------------- + .macro isub_ifge jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode isub_ifge + isub_ifge +@----------------------------------------------------------------------------- + .macro isub_ifgt jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode isub_ifgt + isub_ifgt +@----------------------------------------------------------------------------- + .macro isub_ifle jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode isub_ifle + isub_ifle +@----------------------------------------------------------------------------- + .macro isub_if_icmpeq jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode isub_if_icmpeq + isub_if_icmpeq +@----------------------------------------------------------------------------- + .macro isub_if_icmpne jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode isub_if_icmpne + isub_if_icmpne +@----------------------------------------------------------------------------- + .macro isub_if_icmplt jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode isub_if_icmplt + isub_if_icmplt +@----------------------------------------------------------------------------- + .macro isub_if_icmpge jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode isub_if_icmpge + isub_if_icmpge +@----------------------------------------------------------------------------- + .macro isub_if_icmpgt jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode isub_if_icmpgt + isub_if_icmpgt +@----------------------------------------------------------------------------- + .macro isub_if_icmple jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + sub r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode isub_if_icmple + isub_if_icmple +@----------------------------------------------------------------------------- + .macro isub_goto jpc_off=0, seq_len=1 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + orr ip, ip, r1, lsl #8 + DISPATCH_START_REG ip + POP2 r2, r3 + sub r2, r3, r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode isub_goto + isub_goto +@----------------------------------------------------------------------------- + .macro isub_ireturn jpc_off=0, seq_len=1 + POP2 r2, r3 + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + sub r1, r3, r2 + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b + .endm + + Opcode isub_ireturn + isub_ireturn +@----------------------------------------------------------------------------- + .macro isub_iinc jpc_off=0, seq_len=4 + POP2 tmp1, lr + DISPATCH_START \seq_len + sub tmp1, lr, tmp1 + ldrb r3, [jpc, #-2] @ ECN: jpc now points to next bc + ldrsb r2, [jpc, #-1] + DISPATCH_NEXT + PUSH tmp1 + ldr tmp1, [locals, -r3, lsl #2] + DISPATCH_NEXT + add tmp1, tmp1, r2 + str tmp1, [locals, -r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode isub_iinc + isub_iinc +@----------------------------------------------------------------------------- + .macro iand_iload jpc_off=0, seq_len=3 + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + and tmp2, tmp1, tmp2 + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH + .endm + + Opcode iand_iload + iand_iload +@----------------------------------------------------------------------------- + .macro iand_iload_0 jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + rsb r3, r1, #opc_iload_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + and tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH + .endm + + Opcode iand_iload_0 + iand_iload_0 +@----------------------------------------------------------------------------- + .macro iand_iaload jpc_off=0, seq_len=2 + POP3 r2, r3, lr @ lr = ref + DISPATCH_START \seq_len + and r2, r3, r2 @ r2 = index +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry75: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_1 + add lr, lr, r2, lsl #2 + ldr tmp1, [lr, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iand_iaload + iand_iaload +@----------------------------------------------------------------------------- + .macro iand_istore jpc_off=0, seq_len=3 + mov r0, #opc_iand_u4store + strb r0, [jpc] + b do_iand_u4store + .endm + + Opcode iand_istore + iand_istore +@----------------------------------------------------------------------------- + .macro iand_istore_0 jpc_off=0, seq_len=2 + mov r0, #opc_iand_istore_N + strb r0, [jpc] + b do_iand_istore_N + .endm + + Opcode iand_istore_0 + iand_istore_0 +@----------------------------------------------------------------------------- + .macro iand_iastore jpc_off=0, seq_len=2 + POP2 r2, r3 + DISPATCH_START \seq_len + and tmp1, r3, r2 @ tmp1 = value + POP2 r2, r3 @ r2, index, r3 = ref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry107: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH + .endm + + Opcode iand_iastore + iand_iastore +@----------------------------------------------------------------------------- + .macro iand_iadd jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + and tmp2, r3, r2 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iand_iadd + iand_iadd +@----------------------------------------------------------------------------- + .macro iand_isub jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + and tmp2, r3, r2 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iand_isub + iand_isub +@----------------------------------------------------------------------------- + .macro iand_ifeq jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iand_ifeq + iand_ifeq +@----------------------------------------------------------------------------- + .macro iand_ifne jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iand_ifne + iand_ifne +@----------------------------------------------------------------------------- + .macro iand_iflt jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iand_iflt + iand_iflt +@----------------------------------------------------------------------------- + .macro iand_ifge jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iand_ifge + iand_ifge +@----------------------------------------------------------------------------- + .macro iand_ifgt jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iand_ifgt + iand_ifgt +@----------------------------------------------------------------------------- + .macro iand_ifle jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iand_ifle + iand_ifle +@----------------------------------------------------------------------------- + .macro iand_if_icmpeq jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iand_if_icmpeq + iand_if_icmpeq +@----------------------------------------------------------------------------- + .macro iand_if_icmpne jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iand_if_icmpne + iand_if_icmpne +@----------------------------------------------------------------------------- + .macro iand_if_icmplt jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iand_if_icmplt + iand_if_icmplt +@----------------------------------------------------------------------------- + .macro iand_if_icmpge jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iand_if_icmpge + iand_if_icmpge +@----------------------------------------------------------------------------- + .macro iand_if_icmpgt jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iand_if_icmpgt + iand_if_icmpgt +@----------------------------------------------------------------------------- + .macro iand_if_icmple jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + and r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iand_if_icmple + iand_if_icmple +@----------------------------------------------------------------------------- + .macro iand_goto jpc_off=0, seq_len=1 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + orr ip, ip, r1, lsl #8 + DISPATCH_START_REG ip + POP2 r2, r3 + and r2, r3, r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode iand_goto + iand_goto +@----------------------------------------------------------------------------- + .macro iand_ireturn jpc_off=0, seq_len=1 + POP2 r2, r3 + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + and r1, r3, r2 + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b + .endm + + Opcode iand_ireturn + iand_ireturn +@----------------------------------------------------------------------------- + .macro iand_iinc jpc_off=0, seq_len=4 + POP2 tmp1, lr + DISPATCH_START \seq_len + and tmp1, lr, tmp1 + ldrb r3, [jpc, #-2] @ ECN: jpc now points to next bc + ldrsb r2, [jpc, #-1] + DISPATCH_NEXT + PUSH tmp1 + ldr tmp1, [locals, -r3, lsl #2] + DISPATCH_NEXT + add tmp1, tmp1, r2 + str tmp1, [locals, -r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iand_iinc + iand_iinc +@----------------------------------------------------------------------------- + .macro ior_iload jpc_off=0, seq_len=3 + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + orr tmp2, tmp1, tmp2 + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH + .endm + + Opcode ior_iload + ior_iload +@----------------------------------------------------------------------------- + .macro ior_iload_0 jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + rsb r3, r1, #opc_iload_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + orr tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH + .endm + + Opcode ior_iload_0 + ior_iload_0 +@----------------------------------------------------------------------------- + .macro ior_iaload jpc_off=0, seq_len=2 + POP3 r2, r3, lr @ lr = ref + DISPATCH_START \seq_len + orr r2, r3, r2 @ r2 = index +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry76: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_1 + add lr, lr, r2, lsl #2 + ldr tmp1, [lr, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode ior_iaload + ior_iaload +@----------------------------------------------------------------------------- + .macro ior_istore jpc_off=0, seq_len=3 + mov r0, #opc_ior_u4store + strb r0, [jpc] + b do_ior_u4store + .endm + + Opcode ior_istore + ior_istore +@----------------------------------------------------------------------------- + .macro ior_istore_0 jpc_off=0, seq_len=2 + mov r0, #opc_ior_istore_N + strb r0, [jpc] + b do_ior_istore_N + .endm + + Opcode ior_istore_0 + ior_istore_0 +@----------------------------------------------------------------------------- + .macro ior_iastore jpc_off=0, seq_len=2 + POP2 r2, r3 + DISPATCH_START \seq_len + orr tmp1, r3, r2 @ tmp1 = value + POP2 r2, r3 @ r2, index, r3 = ref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry108: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH + .endm + + Opcode ior_iastore + ior_iastore +@----------------------------------------------------------------------------- + .macro ior_iadd jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + orr tmp2, r3, r2 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode ior_iadd + ior_iadd +@----------------------------------------------------------------------------- + .macro ior_isub jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + orr tmp2, r3, r2 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode ior_isub + ior_isub +@----------------------------------------------------------------------------- + .macro ior_ifeq jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ior_ifeq + ior_ifeq +@----------------------------------------------------------------------------- + .macro ior_ifne jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ior_ifne + ior_ifne +@----------------------------------------------------------------------------- + .macro ior_iflt jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ior_iflt + ior_iflt +@----------------------------------------------------------------------------- + .macro ior_ifge jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ior_ifge + ior_ifge +@----------------------------------------------------------------------------- + .macro ior_ifgt jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ior_ifgt + ior_ifgt +@----------------------------------------------------------------------------- + .macro ior_ifle jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ior_ifle + ior_ifle +@----------------------------------------------------------------------------- + .macro ior_if_icmpeq jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ior_if_icmpeq + ior_if_icmpeq +@----------------------------------------------------------------------------- + .macro ior_if_icmpne jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ior_if_icmpne + ior_if_icmpne +@----------------------------------------------------------------------------- + .macro ior_if_icmplt jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ior_if_icmplt + ior_if_icmplt +@----------------------------------------------------------------------------- + .macro ior_if_icmpge jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ior_if_icmpge + ior_if_icmpge +@----------------------------------------------------------------------------- + .macro ior_if_icmpgt jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ior_if_icmpgt + ior_if_icmpgt +@----------------------------------------------------------------------------- + .macro ior_if_icmple jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + orr r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ior_if_icmple + ior_if_icmple +@----------------------------------------------------------------------------- + .macro ior_goto jpc_off=0, seq_len=1 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + orr ip, ip, r1, lsl #8 + DISPATCH_START_REG ip + POP2 r2, r3 + orr r2, r3, r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode ior_goto + ior_goto +@----------------------------------------------------------------------------- + .macro ior_ireturn jpc_off=0, seq_len=1 + POP2 r2, r3 + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + orr r1, r3, r2 + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b + .endm + + Opcode ior_ireturn + ior_ireturn +@----------------------------------------------------------------------------- + .macro ior_iinc jpc_off=0, seq_len=4 + POP2 tmp1, lr + DISPATCH_START \seq_len + orr tmp1, lr, tmp1 + ldrb r3, [jpc, #-2] @ ECN: jpc now points to next bc + ldrsb r2, [jpc, #-1] + DISPATCH_NEXT + PUSH tmp1 + ldr tmp1, [locals, -r3, lsl #2] + DISPATCH_NEXT + add tmp1, tmp1, r2 + str tmp1, [locals, -r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode ior_iinc + ior_iinc +@----------------------------------------------------------------------------- + .macro ixor_iload jpc_off=0, seq_len=3 + ldrb r3, [jpc, #2] + DISPATCH_START \seq_len + POP2 tmp2, tmp1 + DISPATCH_NEXT + rsb r3, r3, #0 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + eor tmp2, tmp1, tmp2 + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH + .endm + + Opcode ixor_iload + ixor_iload +@----------------------------------------------------------------------------- + .macro ixor_iload_0 jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + rsb r3, r1, #opc_iload_0 + POP2 tmp2, tmp1 + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + eor tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH + .endm + + Opcode ixor_iload_0 + ixor_iload_0 +@----------------------------------------------------------------------------- + .macro ixor_iaload jpc_off=0, seq_len=2 + POP3 r2, r3, lr @ lr = ref + DISPATCH_START \seq_len + eor r2, r3, r2 @ r2 = index +#ifndef HW_NULL_PTR_CHECK + cmp lr, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry77: + ldr tmp1, [lr, #8] @ tmp1 = length + DISPATCH_NEXT + cmp r2, tmp1 + bcs array_bound_exception_jpc_1 + add lr, lr, r2, lsl #2 + ldr tmp1, [lr, #12] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode ixor_iaload + ixor_iaload +@----------------------------------------------------------------------------- + .macro ixor_istore jpc_off=0, seq_len=3 + mov r0, #opc_ixor_u4store + strb r0, [jpc] + b do_ixor_u4store + .endm + + Opcode ixor_istore + ixor_istore +@----------------------------------------------------------------------------- + .macro ixor_istore_0 jpc_off=0, seq_len=2 + mov r0, #opc_ixor_istore_N + strb r0, [jpc] + b do_ixor_istore_N + .endm + + Opcode ixor_istore_0 + ixor_istore_0 +@----------------------------------------------------------------------------- + .macro ixor_iastore jpc_off=0, seq_len=2 + POP2 r2, r3 + DISPATCH_START \seq_len + eor tmp1, r3, r2 @ tmp1 = value + POP2 r2, r3 @ r2, index, r3 = ref +#ifndef HW_NULL_PTR_CHECK + cmp r3, #0 + beq null_ptr_exception_jpc_1 +#endif +.abortentry109: + ldr lr, [r3, #8] @ lr = limit + DISPATCH_NEXT + cmp r2, lr + bcs array_bound_exception_jpc_1 + DISPATCH_NEXT + add r3, r3, r2, lsl #2 + str tmp1, [r3, #12] + DISPATCH_FINISH + .endm + + Opcode ixor_iastore + ixor_iastore +@----------------------------------------------------------------------------- + .macro ixor_iadd jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + eor tmp2, r3, r2 + DISPATCH_NEXT + add tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode ixor_iadd + ixor_iadd +@----------------------------------------------------------------------------- + .macro ixor_isub jpc_off=0, seq_len=2 + DISPATCH_START \seq_len + POP3 r2, r3, tmp1 + DISPATCH_NEXT + eor tmp2, r3, r2 + DISPATCH_NEXT + sub tmp2, tmp1, tmp2 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode ixor_isub + ixor_isub +@----------------------------------------------------------------------------- + .macro ixor_ifeq jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ixor_ifeq + ixor_ifeq +@----------------------------------------------------------------------------- + .macro ixor_ifne jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ixor_ifne + ixor_ifne +@----------------------------------------------------------------------------- + .macro ixor_iflt jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ixor_iflt + ixor_iflt +@----------------------------------------------------------------------------- + .macro ixor_ifge jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ixor_ifge + ixor_ifge +@----------------------------------------------------------------------------- + .macro ixor_ifgt jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ixor_ifgt + ixor_ifgt +@----------------------------------------------------------------------------- + .macro ixor_ifle jpc_off=0, seq_len=1 + POP2 r2, r3 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r3, r3, r2 + add jpc, jpc, #1 + cmp r3, #0 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ixor_ifle + ixor_ifle +@----------------------------------------------------------------------------- + .macro ixor_if_icmpeq jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ixor_if_icmpeq + ixor_if_icmpeq +@----------------------------------------------------------------------------- + .macro ixor_if_icmpne jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ixor_if_icmpne + ixor_if_icmpne +@----------------------------------------------------------------------------- + .macro ixor_if_icmplt jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ixor_if_icmplt + ixor_if_icmplt +@----------------------------------------------------------------------------- + .macro ixor_if_icmpge jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ixor_if_icmpge + ixor_if_icmpge +@----------------------------------------------------------------------------- + .macro ixor_if_icmpgt jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ixor_if_icmpgt + ixor_if_icmpgt +@----------------------------------------------------------------------------- + .macro ixor_if_icmple jpc_off=0, seq_len=1 + POP3 r2, r3, lr + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + eor r2, r3, r2 + add jpc, jpc, #1 + cmp lr, r2 + orr ip, ip, r1, lsl #8 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode ixor_if_icmple + ixor_if_icmple +@----------------------------------------------------------------------------- + .macro ixor_goto jpc_off=0, seq_len=1 + ldrsb r1, [jpc, #2] + ldrb ip, [jpc, #3] + add jpc, jpc, #1 + orr ip, ip, r1, lsl #8 + DISPATCH_START_REG ip + POP2 r2, r3 + eor r2, r3, r2 + DISPATCH_NEXT + PUSH r2 + DISPATCH_FINISH + .endm + + Opcode ixor_goto + ixor_goto +@----------------------------------------------------------------------------- + .macro ixor_ireturn jpc_off=0, seq_len=1 + POP2 r2, r3 + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + eor r1, r3, r2 + ldr tmp_xxx, [istate, #ISTATE_THREAD] + cmp tmp1, tmp2 + bcc 1f +2: + mov r3, #0 + ldr stack, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [stack, #0] + ldrh r0, [r0, #40] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r1, [stack, r0, lsl #2]! + cmp istate, #0 + beq normal_return + ldr jpc, [istate, #ISTATE_BCP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + DISPATCH_START 3 @ ldrb r0, [jpc, #3]! + sub stack, stack, #4 + ldr r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + DISPATCH_NEXT @ ldrb r1, [jpc, #2] + add r2, r2, #4 + DISPATCH_NEXT @ ldr ip, [dispatch, r0, lsl #2] + str r2, [tmp_xxx, #THREAD_JAVA_SP] + DISPATCH_NEXT @ ldrb r2, [jpc, #1] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT @ ands lr, ip, lr + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_FINISH +1: + PUSH r1 + add jpc, jpc, #1 + bl return_check_monitors + POP r1 + b 2b + .endm + + Opcode ixor_ireturn + ixor_ireturn +@----------------------------------------------------------------------------- + .macro ixor_iinc jpc_off=0, seq_len=4 + POP2 tmp1, lr + DISPATCH_START \seq_len + eor tmp1, lr, tmp1 + ldrb r3, [jpc, #-2] @ ECN: jpc now points to next bc + ldrsb r2, [jpc, #-1] + DISPATCH_NEXT + PUSH tmp1 + ldr tmp1, [locals, -r3, lsl #2] + DISPATCH_NEXT + add tmp1, tmp1, r2 + str tmp1, [locals, -r3, lsl #2] + DISPATCH_FINISH + .endm + + Opcode ixor_iinc + ixor_iinc +@----------------------------------------------------------------------------- + .macro iinc_iconst_m1 jpc_off=0, seq_len=4 + ldrsb tmp1, [jpc, #2] + sub lr, r1, #opc_iconst_0 + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + ldr r3, [locals, tmp2, lsl #2] + DISPATCH_NEXT + add r3, r3, tmp1 + DISPATCH_NEXT + PUSH lr + DISPATCH_NEXT + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iinc_iconst_m1 + iinc_iconst_m1 +@----------------------------------------------------------------------------- + .macro iinc_iload jpc_off=0, seq_len=5 + ldrb lr, [jpc, #4] + ldrsb tmp1, [jpc, #2] + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + ldr r3, [locals, tmp2, lsl #2] + DISPATCH_NEXT + rsb lr, lr, #0 + DISPATCH_NEXT + add r3, r3, tmp1 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + ldr tmp1, [locals, lr, lsl #2] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iinc_iload + iinc_iload +@----------------------------------------------------------------------------- + .macro iinc_iload_0 jpc_off=0, seq_len=4 + rsb lr, r1, #opc_iload_0 + ldrsb tmp1, [jpc, #2] + DISPATCH_START \seq_len + rsb tmp2, r2, #0 + ldr r3, [locals, tmp2, lsl #2] + DISPATCH_NEXT + add r3, r3, tmp1 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_NEXT + ldr tmp1, [locals, lr, lsl #2] + DISPATCH_NEXT + PUSH tmp1 + DISPATCH_FINISH + .endm + + Opcode iinc_iload_0 + iinc_iload_0 +@----------------------------------------------------------------------------- + .macro iaccess_0_iload jpc_off=0, seq_len=6 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb r3, [jpc, #2] + add tmp2, constpool, r2, lsl #12 + DISPATCH_START 6 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, r3, lsl #4 + ldrb r3, [jpc, #-1] + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_5 +#endif + DISPATCH_NEXT + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + rsb r3, r3, #0 +.abortentry89: + ldr tmp2, [tmp1, tmp2] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH + .endm + + Opcode iaccess_0_iload + iaccess_0_iload +@----------------------------------------------------------------------------- + .macro iaccess_0_iload_0 jpc_off=0, seq_len=5 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add tmp2, constpool, r2, lsl #12 + DISPATCH_START 5 + rsb r3, r1, #opc_iload_0 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_4 +#endif + DISPATCH_NEXT + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT +.abortentry90: + ldr tmp2, [tmp1, tmp2] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + PUSH2 r3, tmp2 + DISPATCH_FINISH + .endm + + Opcode iaccess_0_iload_0 + iaccess_0_iload_0 +@----------------------------------------------------------------------------- + .macro iaccess_0_iadd jpc_off=0, seq_len=5 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add tmp2, constpool, r2, lsl #12 + DISPATCH_START 5 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + DISPATCH_NEXT +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_4 +#endif + DISPATCH_NEXT + ldr tmp2, [tmp2, #8] + DISPATCH_NEXT + POP r3 +.abortentry91: + ldr tmp2, [tmp1, tmp2] + DISPATCH_NEXT + add tmp2, tmp2, r3 + PUSH tmp2 + DISPATCH_FINISH + .endm + + Opcode iaccess_0_iadd + iaccess_0_iadd +@----------------------------------------------------------------------------- + .macro iaccess_0_ifeq jpc_off=0, seq_len=4 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + orr ip, ip, r0, lsl #8 +.abortentry92: + ldr tmp2, [tmp1, tmp2] + cmp tmp2, #0 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaccess_0_ifeq + iaccess_0_ifeq +@----------------------------------------------------------------------------- + .macro iaccess_0_ifne jpc_off=0, seq_len=4 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + orr ip, ip, r0, lsl #8 +.abortentry93: + ldr tmp2, [tmp1, tmp2] + cmp tmp2, #0 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaccess_0_ifne + iaccess_0_ifne +@----------------------------------------------------------------------------- + .macro iaccess_0_iflt jpc_off=0, seq_len=4 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + orr ip, ip, r0, lsl #8 +.abortentry94: + ldr tmp2, [tmp1, tmp2] + cmp tmp2, #0 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaccess_0_iflt + iaccess_0_iflt +@----------------------------------------------------------------------------- + .macro iaccess_0_ifge jpc_off=0, seq_len=4 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + orr ip, ip, r0, lsl #8 +.abortentry95: + ldr tmp2, [tmp1, tmp2] + cmp tmp2, #0 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaccess_0_ifge + iaccess_0_ifge +@----------------------------------------------------------------------------- + .macro iaccess_0_ifgt jpc_off=0, seq_len=4 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + orr ip, ip, r0, lsl #8 +.abortentry96: + ldr tmp2, [tmp1, tmp2] + cmp tmp2, #0 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaccess_0_ifgt + iaccess_0_ifgt +@----------------------------------------------------------------------------- + .macro iaccess_0_ifle jpc_off=0, seq_len=4 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + orr ip, ip, r0, lsl #8 +.abortentry97: + ldr tmp2, [tmp1, tmp2] + cmp tmp2, #0 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaccess_0_ifle + iaccess_0_ifle +@----------------------------------------------------------------------------- + .macro iaccess_0_if_icmpeq jpc_off=0, seq_len=4 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + POP r3 + orr ip, ip, r0, lsl #8 +.abortentry98: + ldr tmp2, [tmp1, tmp2] + cmp r3, tmp2 + beq 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaccess_0_if_icmpeq + iaccess_0_if_icmpeq +@----------------------------------------------------------------------------- + .macro iaccess_0_if_icmpne jpc_off=0, seq_len=4 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + POP r3 + orr ip, ip, r0, lsl #8 +.abortentry99: + ldr tmp2, [tmp1, tmp2] + cmp r3, tmp2 + bne 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaccess_0_if_icmpne + iaccess_0_if_icmpne +@----------------------------------------------------------------------------- + .macro iaccess_0_if_icmplt jpc_off=0, seq_len=4 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + POP r3 + orr ip, ip, r0, lsl #8 +.abortentry100: + ldr tmp2, [tmp1, tmp2] + cmp r3, tmp2 + blt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaccess_0_if_icmplt + iaccess_0_if_icmplt +@----------------------------------------------------------------------------- + .macro iaccess_0_if_icmpge jpc_off=0, seq_len=4 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + POP r3 + orr ip, ip, r0, lsl #8 +.abortentry101: + ldr tmp2, [tmp1, tmp2] + cmp r3, tmp2 + bge 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaccess_0_if_icmpge + iaccess_0_if_icmpge +@----------------------------------------------------------------------------- + .macro iaccess_0_if_icmpgt jpc_off=0, seq_len=4 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + POP r3 + orr ip, ip, r0, lsl #8 +.abortentry102: + ldr tmp2, [tmp1, tmp2] + cmp r3, tmp2 + bgt 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaccess_0_if_icmpgt + iaccess_0_if_icmpgt +@----------------------------------------------------------------------------- + .macro iaccess_0_if_icmple jpc_off=0, seq_len=4 + ldrb r2, [jpc, #3] + rsb tmp1, r0, #opc_iaccess_0 + ldrb ip, [jpc, #2] + add jpc, jpc, #4 + ldrsb r0, [jpc, #1] + add tmp2, constpool, r2, lsl #12 + ldr tmp1, [locals, tmp1, lsl #2] + add tmp2, ip, lsl #4 + ldrb ip, [jpc, #2] +#ifndef HW_NULL_PTR_CHECK + cmp tmp1, #0 + beq null_ptr_exception_jpc_3 +#endif + ldr tmp2, [tmp2, #8] + POP r3 + orr ip, ip, r0, lsl #8 +.abortentry103: + ldr tmp2, [tmp1, tmp2] + cmp r3, tmp2 + ble 1f + mov ip, #3 +1: + ldrb r0, [jpc, ip]! + DISPATCH_BYTECODE + .endm + + Opcode iaccess_0_if_icmple + iaccess_0_if_icmple +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_iadd jpc_off=0, seq_len=3 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + ldrb r2, [jpc, #1-\seq_len] + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp1, r2, #opc_iconst_0 + DISPATCH_NEXT + add r3, r3, tmp1 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_iadd + iload_0_iconst_N_iadd +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_isub jpc_off=0, seq_len=3 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + ldrb r2, [jpc, #1-\seq_len] + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp1, r2, #opc_iconst_0 + DISPATCH_NEXT + sub r3, r3, tmp1 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_isub + iload_0_iconst_N_isub +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_iand jpc_off=0, seq_len=3 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + ldrb r2, [jpc, #1-\seq_len] + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp1, r2, #opc_iconst_0 + DISPATCH_NEXT + and r3, r3, tmp1 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_iand + iload_0_iconst_N_iand +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_ior jpc_off=0, seq_len=3 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + ldrb r2, [jpc, #1-\seq_len] + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp1, r2, #opc_iconst_0 + DISPATCH_NEXT + orr r3, r3, tmp1 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_ior + iload_0_iconst_N_ior +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_ixor jpc_off=0, seq_len=3 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + ldrb r2, [jpc, #1-\seq_len] + DISPATCH_NEXT + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub tmp1, r2, #opc_iconst_0 + DISPATCH_NEXT + eor r3, r3, tmp1 + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_ixor + iload_0_iconst_N_ixor +@----------------------------------------------------------------------------- + .macro iload_iconst_N_iadd jpc_off=0, seq_len=4 + ldrb r3, [jpc, #2] + rsb r2, r2, #0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr r2, [locals, r2, lsl #2] + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + add r3, r2, r3 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_iadd + iload_iconst_N_iadd +@----------------------------------------------------------------------------- + .macro iload_iconst_N_isub jpc_off=0, seq_len=4 + ldrb r3, [jpc, #2] + rsb r2, r2, #0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr r2, [locals, r2, lsl #2] + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + sub r3, r2, r3 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_isub + iload_iconst_N_isub +@----------------------------------------------------------------------------- + .macro iload_iconst_N_iand jpc_off=0, seq_len=4 + ldrb r3, [jpc, #2] + rsb r2, r2, #0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr r2, [locals, r2, lsl #2] + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + and r3, r2, r3 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_iand + iload_iconst_N_iand +@----------------------------------------------------------------------------- + .macro iload_iconst_N_ior jpc_off=0, seq_len=4 + ldrb r3, [jpc, #2] + rsb r2, r2, #0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr r2, [locals, r2, lsl #2] + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + orr r3, r2, r3 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_ior + iload_iconst_N_ior +@----------------------------------------------------------------------------- + .macro iload_iconst_N_ixor jpc_off=0, seq_len=4 + ldrb r3, [jpc, #2] + rsb r2, r2, #0 + DISPATCH_START \seq_len + DISPATCH_NEXT + ldr r2, [locals, r2, lsl #2] + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + eor r3, r2, r3 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH r3 + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_ixor + iload_iconst_N_ixor +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_iadd_u4store jpc_off=0, seq_len=5 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + add r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_iadd_u4store + iload_0_iconst_N_iadd_u4store +@----------------------------------------------------------------------------- + .macro iload_iconst_N_iadd_u4store jpc_off=0, seq_len=6 + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #5] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + add r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_iadd_u4store + iload_iconst_N_iadd_u4store +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_iadd_istore_N jpc_off=0, seq_len=4 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + add r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #opc_istore_0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_iadd_istore_N + iload_0_iconst_N_iadd_istore_N +@----------------------------------------------------------------------------- + .macro iload_iconst_N_iadd_istore_N jpc_off=0, seq_len=5 + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #4] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #opc_istore_0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + add r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_iadd_istore_N + iload_iconst_N_iadd_istore_N +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_isub_u4store jpc_off=0, seq_len=5 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_isub_u4store + iload_0_iconst_N_isub_u4store +@----------------------------------------------------------------------------- + .macro iload_iconst_N_isub_u4store jpc_off=0, seq_len=6 + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #5] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + sub r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_isub_u4store + iload_iconst_N_isub_u4store +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_isub_istore_N jpc_off=0, seq_len=4 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + sub r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #opc_istore_0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_isub_istore_N + iload_0_iconst_N_isub_istore_N +@----------------------------------------------------------------------------- + .macro iload_iconst_N_isub_istore_N jpc_off=0, seq_len=5 + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #4] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #opc_istore_0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + sub r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_isub_istore_N + iload_iconst_N_isub_istore_N +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_iand_u4store jpc_off=0, seq_len=5 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + and r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_iand_u4store + iload_0_iconst_N_iand_u4store +@----------------------------------------------------------------------------- + .macro iload_iconst_N_iand_u4store jpc_off=0, seq_len=6 + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #5] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + and r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_iand_u4store + iload_iconst_N_iand_u4store +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_iand_istore_N jpc_off=0, seq_len=4 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + and r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #opc_istore_0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_iand_istore_N + iload_0_iconst_N_iand_istore_N +@----------------------------------------------------------------------------- + .macro iload_iconst_N_iand_istore_N jpc_off=0, seq_len=5 + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #4] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #opc_istore_0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + and r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_iand_istore_N + iload_iconst_N_iand_istore_N +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_ior_u4store jpc_off=0, seq_len=5 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + orr r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_ior_u4store + iload_0_iconst_N_ior_u4store +@----------------------------------------------------------------------------- + .macro iload_iconst_N_ior_u4store jpc_off=0, seq_len=6 + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #5] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + orr r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_ior_u4store + iload_iconst_N_ior_u4store +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_ior_istore_N jpc_off=0, seq_len=4 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + orr r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #opc_istore_0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_ior_istore_N + iload_0_iconst_N_ior_istore_N +@----------------------------------------------------------------------------- + .macro iload_iconst_N_ior_istore_N jpc_off=0, seq_len=5 + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #4] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #opc_istore_0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + orr r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_ior_istore_N + iload_iconst_N_ior_istore_N +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_ixor_u4store jpc_off=0, seq_len=5 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + eor r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_ixor_u4store + iload_0_iconst_N_ixor_u4store +@----------------------------------------------------------------------------- + .macro iload_iconst_N_ixor_u4store jpc_off=0, seq_len=6 + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #5] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + eor r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_ixor_u4store + iload_iconst_N_ixor_u4store +@----------------------------------------------------------------------------- + .macro iload_0_iconst_N_ixor_istore_N jpc_off=0, seq_len=4 + rsb r3, r0, #opc_iload_0_iconst_N + DISPATCH_START \seq_len + sub r2, r2, #opc_iconst_0 + DISPATCH_NEXT + ldrb tmp1, [jpc, #-1] + ldr r3, [locals, r3, lsl #2] + DISPATCH_NEXT + eor r3, r3, r2 + DISPATCH_NEXT + rsb tmp1, tmp1, #opc_istore_0 + DISPATCH_NEXT + str r3, [locals, tmp1, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_0_iconst_N_ixor_istore_N + iload_0_iconst_N_ixor_istore_N +@----------------------------------------------------------------------------- + .macro iload_iconst_N_ixor_istore_N jpc_off=0, seq_len=5 + ldrb r3, [jpc, #2] + ldrb lr, [jpc, #4] + rsb r2, r2, #0 + DISPATCH_START \seq_len + sub r3, r3, #opc_iconst_0 + DISPATCH_NEXT + rsb tmp2, lr, #opc_istore_0 + DISPATCH_NEXT + ldr tmp1, [locals, r2, lsl #2] + DISPATCH_NEXT + eor r3, tmp1, r3 + DISPATCH_NEXT + str r3, [locals, tmp2, lsl #2] + DISPATCH_FINISH + .endm + + Opcode iload_iconst_N_ixor_istore_N + iload_iconst_N_ixor_istore_N + .macro MAIN_DISPATCH_TABLE + .word do_nop + .word do_u4const_0 + .word dispatch_iconst_m1+1 + .word dispatch_iconst_0+1 + .word dispatch_iconst_1+1 + .word dispatch_iconst_2+1 + .word dispatch_iconst_3+1 + .word dispatch_iconst_4+1 + .word dispatch_iconst_5+1 + .word do_u8const_0 + .word do_lconst_1 + .word do_u4const_0 + .word do_fconst_1 + .word do_fconst_2 + .word do_u8const_0 + .word do_dconst_1 + .word do_bipush + .word do_sipush + .word do_ldc + .word do_ldc_w + .word do_ldc2_w + .word dispatch_iload+2 + .word do_u8load + .word dispatch_fload+2 + .word do_u8load + .word dispatch_aload+2 + .word dispatch_iload_0+1 + .word dispatch_iload_1+1 + .word dispatch_iload_2+1 + .word dispatch_iload_3+1 + .word do_u8load_0 + .word do_u8load_1 + .word do_u8load_2 + .word do_u8load_3 + .word do_fload_0 + .word do_fload_0 + .word do_fload_0 + .word do_fload_0 + .word do_u8load_0 + .word do_u8load_1 + .word do_u8load_2 + .word do_u8load_3 + .word dispatch_aload_0+1 + .word dispatch_aload_1+1 + .word dispatch_aload_2+1 + .word dispatch_aload_3+1 + .word dispatch_iaload+1 + .word do_u8aload + .word dispatch_faload+1 + .word do_u8aload + .word dispatch_aaload+1 + .word do_baload + .word do_caload + .word do_saload + .word do_u4store + .word do_u8store + .word do_u4store + .word do_u8store + .word do_u4store + .word do_u4store_0 + .word do_u4store_1 + .word do_u4store_2 + .word do_u4store_3 + .word do_u8store_0 + .word do_u8store_1 + .word do_u8store_2 + .word do_u8store_3 + .word do_u4store_0 + .word do_u4store_1 + .word do_u4store_2 + .word do_u4store_3 + .word do_u8store_0 + .word do_u8store_1 + .word do_u8store_2 + .word do_u8store_3 + .word do_u4store_0 + .word do_u4store_1 + .word do_u4store_2 + .word do_u4store_3 + .word do_u4astore + .word do_u8astore + .word do_u4astore + .word do_u8astore + .word do_aastore + .word do_bastore + .word do_u2astore + .word do_u2astore + .word do_jpop + .word do_jpop2 + .word do_dup + .word do_dup_x1 + .word do_dup_x2 + .word do_dup2 + .word do_dup2_x1 + .word do_dup2_x2 + .word do_swap + .word dispatch_iadd+1 + .word do_ladd + .word do_fadd + .word do_dadd + .word dispatch_isub+1 + .word do_lsub + .word do_fsub + .word do_dsub + .word do_imul + .word do_lmul + .word do_fmul + .word do_dmul + .word do_idiv + .word do_ldiv + .word do_fdiv + .word do_ddiv + .word do_irem + .word do_lrem + .word do_frem + .word do_drem + .word do_ineg + .word do_lneg + .word do_fneg + .word do_dneg + .word do_ishl + .word do_lshl + .word do_ishr + .word do_lshr + .word do_iushr + .word do_lushr + .word dispatch_iand+1 + .word do_land + .word dispatch_ior+1 + .word do_lor + .word dispatch_ixor+1 + .word do_lxor + .word dispatch_iinc+3 + .word do_i2l + .word do_i2f + .word do_i2d + .word do_l2i + .word do_l2f + .word do_l2d + .word do_f2i + .word do_f2l + .word do_f2d + .word do_d2i + .word do_d2l + .word do_d2f + .word do_i2b + .word do_i2c + .word do_i2s + .word do_lcmp + .word do_fcmpl + .word do_fcmpg + .word do_dcmpl + .word do_dcmpg + .word do_ifeq_unsafe + .word do_ifne_unsafe + .word do_iflt_unsafe + .word do_ifge_unsafe + .word do_ifgt_unsafe + .word do_ifle_unsafe + .word do_if_icmpeq_unsafe + .word do_if_icmpne_unsafe + .word do_if_icmplt_unsafe + .word do_if_icmpge_unsafe + .word do_if_icmpgt_unsafe + .word do_if_icmple_unsafe + .word do_if_icmpeq_unsafe + .word do_if_icmpne_unsafe + .word do_goto_unsafe + .word do_jsr + .word do_ret + .word do_tableswitch + .word do_lookupswitch + .word do_ireturn_unsafe + .word do_lreturn_unsafe + .word do_ireturn_unsafe + .word do_lreturn_unsafe + .word do_ireturn_unsafe + .word do_return_unsafe + .word do_getstatic + .word do_putstatic + .word do_getfield + .word do_putfield + .word do_invokevirtual + .word do_invokespecial + .word do_invokestatic + .word do_invokeinterface + .word do_undefined + .word do_new + .word do_newarray + .word do_anewarray + .word do_arraylength + .word do_athrow + .word do_checkcast + .word do_instanceof + .word do_monitorenter + .word do_monitorexit + .word do_wide + .word do_multianewarray + .word do_ifeq_unsafe + .word do_ifne_unsafe + .word do_goto_w + .word do_jsr_w + .word do_breakpoint + .word do_undefined + .word do_bgetfield + .word do_cgetfield + .word do_undefined + .word do_undefined + .word do_igetfield + .word do_lgetfield + .word do_sgetfield + .word do_aputfield + .word do_bputfield + .word do_cputfield + .word do_undefined + .word do_undefined + .word do_iputfield + .word do_lputfield + .word do_undefined + .word dispatch_iaccess_0+4 + .word dispatch_iaccess_1+4 + .word dispatch_iaccess_2+4 + .word dispatch_iaccess_3+4 + .word do_undefined + .word do_undefined + .word do_undefined + .word do_invokevfinal + .word do_undefined + .word do_undefined + .word do_return_register_finalizer + .word do_undefined + .word dispatch_iload_0_iconst_N+2 + .word dispatch_iload_1_iconst_N+2 + .word dispatch_iload_2_iconst_N+2 + .word dispatch_iload_3_iconst_N+2 + .word dispatch_iload_iconst_N+3 + .word do_invokeresolved + .word do_iadd_istore_N + .word do_isub_istore_N + .word do_iand_istore_N + .word do_ior_istore_N + .word do_ixor_istore_N + .word do_iadd_u4store + .word do_isub_u4store + .word do_iand_u4store + .word do_ior_u4store + .word do_ixor_u4store + .word do_invokespecialresolved + .word do_invokestaticresolved + .word do_undefined + .word do_undefined + .word do_undefined + .word do_undefined + .word do_undefined + .word do_undefined + .word do_undefined + .endm + .macro SUB_DISPATCH_TABLES +dispatch_iconst_m1: +dispatch_iconst_0: +dispatch_iconst_1: +dispatch_iconst_2: +dispatch_iconst_3: +dispatch_iconst_4: +dispatch_iconst_5: + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_m1_astore + .word do_iconst_N + .word do_iconst_m1_astore + .word do_iconst_N + .word do_iconst_m1_astore + .word do_iconst_m1_istore_0 + .word do_iconst_m1_istore_0 + .word do_iconst_m1_istore_0 + .word do_iconst_m1_istore_0 + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_m1_iadd + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word 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do_iload_iconst_N + .word do_iload_iconst_N + .word do_iload_iconst_N_iadd_istore_N + .word do_iload_iconst_N_isub_istore_N + .word do_iload_iconst_N_iand_istore_N + .word do_iload_iconst_N_ior_istore_N + .word do_iload_iconst_N_ixor_istore_N + .word do_iload_iconst_N_iadd_u4store + .word do_iload_iconst_N_isub_u4store + .word do_iload_iconst_N_iand_u4store + .word do_iload_iconst_N_ior_u4store + .word do_iload_iconst_N_ixor_u4store + .word do_iload_iconst_N + .word do_iload_iconst_N + .word do_iload_iconst_N + .word do_iload_iconst_N + .word do_iload_iconst_N + .word do_iload_iconst_N + .word do_iload_iconst_N + .word do_iload_iconst_N + .word do_iload_iconst_N + .endm
--- a/ports/hotspot/src/cpu/zero/vm/bytecodes_zero.cpp Thu Aug 13 15:48:51 2009 +0100 +++ b/ports/hotspot/src/cpu/zero/vm/bytecodes_zero.cpp Fri Aug 21 13:35:04 2009 +0200 @@ -28,5 +28,32 @@ void Bytecodes::pd_initialize() { - // No zero specific initialization +#if defined(PRODUCT) && defined(HOTSPOT_ASM) + def(_iaccess_0, "_iaccess_0", "b_jj", NULL, T_INT, 1, true, _aload_0); + def(_iaccess_1, "_iaccess_1", "b_jj", NULL, T_INT, 1, true, _aload_1); + def(_iaccess_2, "_iaccess_2", "b_jj", NULL, T_INT, 1, true, _aload_2); + def(_iaccess_3, "_iaccess_3", "b_jj", NULL, T_INT, 1, true, _aload_3); + + def(_iload_0_iconst_N, "iload_0_iconst_N", "b_", NULL, T_INT, 2, false, _iload_0); + def(_iload_1_iconst_N, "iload_1_iconst_N", "b_", NULL, T_INT, 2, false, _iload_1); + def(_iload_2_iconst_N, "iload_2_iconst_N", "b_", NULL, T_INT, 2, false, _iload_2); + def(_iload_3_iconst_N, "iload_3_iconst_N", "b_", NULL, T_INT, 2, false, _iload_3); + def(_iload_iconst_N, "iload_iconst_N", "bi_", NULL, T_INT, 2, false, _iload); + def(_invokeresolved, "invokeresolved", "bjj", NULL, T_ILLEGAL, -1, true, _invokevirtual); + + def(_iadd_istore_N, "iadd_istore_N", "b_", NULL, T_VOID, -2, false, _iadd); + def(_isub_istore_N, "isub_istore_N", "b_", NULL, T_VOID, -2, false, _isub); + def(_iand_istore_N, "iand_istore_N", "b_", NULL, T_VOID, -2, false, _iand); + def(_ior_istore_N, "ior_istore_N", "b_", NULL, T_VOID, -2, false, _ior); + def(_ixor_istore_N, "ixor_istore_N", "b_", NULL, T_VOID, -2, false, _ixor); + + def(_iadd_u4store, "iadd_u4store", "b_i", NULL, T_VOID, -2, false, _iadd); + def(_isub_u4store, "isub_u4store", "b_i", NULL, T_VOID, -2, false, _isub); + def(_iand_u4store, "iand_u4store", "b_i", NULL, T_VOID, -2, false, _iand); + def(_ior_u4store, "ior_u4store", "b_i", NULL, T_VOID, -2, false, _ior); + def(_ixor_u4store, "ixor_u4store", "b_i", NULL, T_VOID, -2, false, _ixor); + + def(_invokespecialresolved, "invokespecialresolved", "bjj", NULL, T_ILLEGAL, -1, true, _invokespecial); + def(_invokestaticresolved, "invokestaticresolved", "bjj", NULL, T_ILLEGAL, 0, true, _invokestatic); +#endif // HOTSPOT_ASM }
--- a/ports/hotspot/src/cpu/zero/vm/bytecodes_zero.hpp Thu Aug 13 15:48:51 2009 +0100 +++ b/ports/hotspot/src/cpu/zero/vm/bytecodes_zero.hpp Fri Aug 21 13:35:04 2009 +0200 @@ -0,0 +1,24 @@ +#if defined(PRODUCT) && defined(HOTSPOT_ASM) +#define _iaccess_0 ((Bytecodes::Code)0xdb) +#define _iaccess_1 ((Bytecodes::Code)0xdc) +#define _iaccess_2 ((Bytecodes::Code)0xdd) +#define _iaccess_3 ((Bytecodes::Code)0xde) + _iload_0_iconst_N , // 231 + _iload_1_iconst_N , // 232 + _iload_2_iconst_N , // 233 + _iload_3_iconst_N , // 234 + _iload_iconst_N , // 235 + _invokeresolved , // 236 + _iadd_istore_N , // 237 + _isub_istore_N , // 238 + _iand_istore_N , // 239 + _ior_istore_N , // 240 + _ixor_istore_N , // 241 + _iadd_u4store , // 242 + _isub_u4store , // 243 + _iand_u4store , // 244 + _ior_u4store , // 245 + _ixor_u4store , // 246 + _invokespecialresolved , // 247 + _invokestaticresolved , // 248 +#endif // HOTSPOT_ASM
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ports/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S Fri Aug 21 13:35:04 2009 +0200 @@ -0,0 +1,5820 @@ +#if defined(PRODUCT) && defined(HOTSPOT_ASM) +//#define HW_NULL_PTR_CHECK +//#define UNALIGNED_ACCESS +//#define B14 + +#define ARMv4 + +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) + +// ECN: DOH!!! gcc 4.4 has changed the name mangling scheme!!! +#if GCC_VERSION >= 40400 +#define oop_store _Z9oop_storeIP7oopDescEvPT_S1_ +#else +#define oop_store _Z9oop_storeIP7oopDescEvPVT_S1_ +#endif + +#define stack r4 +#define jpc r5 +#define dispatch r6 +#define locals r7 +#define istate r8 +#define constpool r9 +#define arm_sp r13 + +#define CONST_POOL_OFFSET 16 + +#define tmp_xxx r7 +#define tmp_yyy r5 +#define tmp_zzz r8 +#define tmp_vvv r9 + +#define tmp1 r11 +#define tmp2 r10 + +#define regset r4-r11 + +#define tos_btos 0 +#define tos_ctos 1 +#define tos_stos 2 +#define tos_itos 3 +#define tos_ltos 4 +#define tos_ftos 5 +#define tos_dtos 6 +#define tos_atos 7 + +#define JVM_CONSTANT_Utf8 1 +#define JVM_CONSTANT_Unicode 2 +#define JVM_CONSTANT_Integer 3 +#define JVM_CONSTANT_Float 4 +#define JVM_CONSTANT_Long 5 +#define JVM_CONSTANT_Double 6 +#define JVM_CONSTANT_Class 7 +#define JVM_CONSTANT_String 8 +#define JVM_CONSTANT_Fieldref 9 +#define JVM_CONSTANT_Methodref 10 +#define JVM_CONSTANT_InterfaceMethodref 11 +#define JVM_CONSTANT_NameAndType 12 + +#define JVM_CONSTANT_UnresolvedClass 100 +#define JVM_CONSTANT_ClassIndex 101 +#define JVM_CONSTANT_UnresolvedString 102 +#define JVM_CONSTANT_StringIndex 103 +#define JVM_CONSTANT_UnresolvedClassInError 104 + +#define T_BOOLEAN 4 +#define T_CHAR 5 +#define T_FLOAT 6 +#define T_DOUBLE 7 +#define T_BYTE 8 +#define T_SHORT 9 +#define T_INT 10 +#define T_LONG 11 +#define T_OBJECT 12 +#define T_ARRAY 13 +#define T_VOID 14 + +#define _thread_uninitialized 0 +#define _thread_new 2 +#define _thread_new_trans 3 +#define _thread_in_native 4 +#define _thread_in_native_trans 5 +#define _thread_in_vm 6 +#define _thread_in_vm_trans 7 +#define _thread_in_Java 8 +#define _thread_in_Java_trans 9 +#define _thread_blocked 10 +#define _thread_blocked_trans 11 +#define _thread_max_state 12 + + +#define THREAD_VTABLE 0 +#define THREAD_PENDING_EXC 4 +#define THREAD_SUSPEND_FLAGS 24 +#define THREAD_ACTIVE_HANDLES 32 +#define THREAD_LAST_HANDLE_MARK 40 + +#ifdef B14 +#define THREAD_TLAB_TOP 56 +#define THREAD_TLAB_END 64 +#define THREAD_HANDLE_AREA 152 +#define THREAD_STACK_BASE 156 +#define THREAD_STACK_SIZE 160 +#define THREAD_LAST_JAVA_SP 260 +#define THREAD_JNI_ENVIRONMENT 272 +#define THREAD_VM_RESULT 300 +#define THREAD_STATE 320 +#define THREAD_DO_NOT_UNLOCK 345 +#define THREAD_JAVA_STACK_BASE 476 +#define THREAD_JAVA_SP 484 +#define THREAD_TOP_ZERO_FRAME 488 + +#define THREAD_VTABLE_IS_LOCK_OWNED 56 +#else +#define THREAD_TLAB_TOP 56-4 +#define THREAD_TLAB_END 64-4 +#define THREAD_HANDLE_AREA 152-4 +#define THREAD_STACK_BASE 156-4 +#define THREAD_STACK_SIZE 160-4 +#define THREAD_LAST_JAVA_SP 260-4 +#define THREAD_JNI_ENVIRONMENT 272-4 +#define THREAD_VM_RESULT 300-4 +#define THREAD_STATE 320-4 +#define THREAD_DO_NOT_UNLOCK 345-4 +#define THREAD_JAVA_STACK_BASE 476-4 +#define THREAD_JAVA_SP 484-4 +#define THREAD_TOP_ZERO_FRAME 488-4 + +#define THREAD_VTABLE_IS_LOCK_OWNED 52 +#endif + +#define UNIVERSE_VTABLE 0 +#define UNIVERSE_VTABLE_TOP_ADDR 96 +#define UNIVERSE_VTABLE_END_ADDR 100 + +#ifdef B14 +#define VMSYMBOLS_ArithmeticException 77 +#define VMSYMBOLS_ArrayIndexOutOfBounds 78 +#define VMSYMBOLS_ArrayStoreException 79 +#define VMSYMBOLS_ClassCastException 80 +#define VMSYMBOLS_NullPointerException 95 +#define VMSYMBOLS_AbstractMethodError 103 +#define VMSYMBOLS_IncompatibleClassChangeError 110 +#define VMSYMBOLS_InternalError 111 +#else +#define VMSYMBOLS_ArithmeticException 78 +#define VMSYMBOLS_ArrayIndexOutOfBounds 79 +#define VMSYMBOLS_ArrayStoreException 80 +#define VMSYMBOLS_ClassCastException 81 +#define VMSYMBOLS_NullPointerException 96 +#define VMSYMBOLS_AbstractMethodError 104 +#define VMSYMBOLS_IncompatibleClassChangeError 111 +#define VMSYMBOLS_InternalError 112 +#endif + +#define ISTATE_THREAD 0 +#define ISTATE_BCP 4 +#define ISTATE_LOCALS 8 +#define ISTATE_CONSTANTS 12 +#define ISTATE_METHOD 16 +#define ISTATE_MDX 20 +#define ISTATE_STACK 24 +#define ISTATE_SAVED_ISTATE 28 +#define ISTATE_MSG 28 +#define ISTATE_CALLEE 32 // union frame_manager_message + +#define ISTATE_PREV_LINK 44 +#define ISTATE_OOP_TEMP 48 +#define ISTATE_STACK_BASE 52 +#define ISTATE_STACK_LIMIT 56 +#define ISTATE_MONITOR_BASE 60 +#define ISTATE_SELF_LINK 64 +#define ISTATE_CAFEBABF 68 + +#define last_implemented_bytecode 248 + + .macro ALIGN_CODE + .align 6 + .endm + + .macro ALIGN_DATA + .align 6 + .endm + + .macro ALIGN_OPCODE + .align 6 + .endm + + .macro ALIGN_WORD + .align 2 + .endm + + .macro Opcode label + ALIGN_OPCODE +do_\label: + .endm + + .macro GET_STACK offset, reg + ldr \reg, [stack, #(\offset+1) * 4] + .endm + + .macro PUT_STACK offset, reg + str \reg, [stack, #(\offset+1) * 4] + .endm + + .macro PUSH4 reg1, reg2, reg3, reg4 + stmda stack!, {\reg1, \reg2, \reg3, \reg4} + .endm + + .macro POP4 reg1, reg2, reg3, reg4 + ldmib stack!, {\reg1, \reg2, \reg3, \reg4} + .endm + + .macro PUSH3 reg1, reg2, reg3 + stmda stack!, {\reg1, \reg2, \reg3} + .endm + + .macro POP3 reg1, reg2, reg3 + ldmib stack!, {\reg1, \reg2, \reg3} + .endm + + .macro PUSH2 reg1, reg2 + stmda stack!, {\reg1, \reg2} + .endm + + .macro PUSH reg + str \reg, [stack], #-4 + .endm + + .macro POP2 reg1, reg2 + ldmib stack!, {\reg1, \reg2} + .endm + + .macro POP reg + ldr \reg, [stack, #4]! + .endm + + .set dispatch_state, 0 + + .macro DISPATCH_START step=0 + .set dispatch_state, 1 + ldrb r0, [jpc, #\step]! + .endm + + .macro DISPATCH_START_REG reg + .set dispatch_state, 1 + ldrb r0, [jpc, \reg]! + .endm + + .macro DISPATCH_STATE state + .set dispatch_state, \state + .endm + + .macro DISPATCH_1 + ldrb r1, [jpc, #2] + .endm + + .macro DISPATCH_2 + ldr ip, [dispatch, r0, lsl #2] + .endm + + .macro DISPATCH_3 + ldrb r2, [jpc, #1] + .endm + + .macro DISPATCH_4 + ands lr, ip, #7 + .endm + + .macro DISPATCH_NEXT + .if dispatch_state == 0 + .error "DISPATCH_FINISH without a DISPATCH_START or DISPATCH_STATE" + .elseif dispatch_state == 1 + DISPATCH_1 + .elseif dispatch_state == 2 + DISPATCH_2 + .elseif dispatch_state == 3 + DISPATCH_3 + .elseif dispatch_state == 4 + DISPATCH_4 + .else + .error "Too many DISPATCH_NEXTs" + .endif + .set dispatch_state, dispatch_state + 1 + .endm + + .macro DISPATCH_FINISH + .if dispatch_state == 0 + .error "DISPATCH_FINISH without a DISPATCH_START or DISPATCH_STATE" + .elseif dispatch_state == 1 + DISPATCH_1 + DISPATCH_2 + DISPATCH_3 + DISPATCH_4 + .elseif dispatch_state == 2 + DISPATCH_2 + DISPATCH_3 + DISPATCH_4 + .elseif dispatch_state == 3 + DISPATCH_3 + DISPATCH_4 + .elseif dispatch_state == 4 + DISPATCH_4 + .endif + moveq pc, ip + ldrb r1, [jpc, lr] + bic ip, ip, #7 + ldr ip, [ip, r1, lsl #2] + mov pc, ip + .set dispatch_state, 0 + .endm + + .macro DISPATCH_BYTECODE + ldrb r1, [jpc, #2] + ldr ip, [dispatch, r0, lsl #2] + ldrb r2, [jpc, #1] + ands lr, ip, #7 + moveq pc, ip + ldrb r1, [jpc, lr] + bic ip, ip, #7 + ldr ip, [ip, r1, lsl #2] + mov pc, ip + .endm + + .macro DISPATCH step=0 + ldrb r0, [jpc, #\step]! + ldrb r1, [jpc, #2] + ldr ip, [dispatch, r0, lsl #2] + ldrb r2, [jpc, #1] + ands lr, ip, #7 + moveq pc, ip + ldrb r1, [jpc, lr] + bic ip, ip, #7 + ldr ip, [ip, r1, lsl #2] + mov pc, ip + .endm + +#define FFI_TYPE_VOID 0 +#define FFI_TYPE_FLOAT 2 +#define FFI_TYPE_DOUBLE 3 +#define FFI_TYPE_BOOL 5 +#define FFI_TYPE_SINT8 6 +#define FFI_TYPE_UINT16 7 +#define FFI_TYPE_SINT16 8 +#define FFI_TYPE_SINT32 10 +#define FFI_TYPE_SINT64 12 +#define FFI_TYPE_POINTER 14 + + .macro _BLX reg +#ifdef ARMv4 + mov lr, pc + mov pc, \reg +#else + blx \reg +#endif + .endm +#define blx _BLX + + .macro _BX reg +#ifdef ARMv4 + mov pc, \reg +#else + bx \reg +#endif + .endm +#define bx _BX + + .macro _BXEQ reg +#ifdef ARMv4 + moveq pc, \reg +#else + bxeq \reg +#endif + .endm +#define bxeq _BXEQ + + .macro _BXNE reg +#ifdef ARMv4 + movne pc, \reg +#else + bxne \reg +#endif + .endm +#define bxne _BXNE + +#ifdef ARMv4 + .arch armv4 +#else + .arch armv7-a +#endif + .fpu softvfp + .eabi_attribute 20, 1 + .eabi_attribute 21, 1 + .eabi_attribute 23, 3 + .eabi_attribute 24, 1 + .eabi_attribute 25, 1 + .eabi_attribute 26, 2 + .eabi_attribute 30, 2 + .eabi_attribute 18, 4 + + .text + + ALIGN_CODE +build_normal: + ldr ip, [r1, #24] + tst ip, #32 + bne build_normal_synchronized +build_normal_unsynchronized: + stmfd sp!, {r4, r5, r6, r7, r8} + ldr r4, [r0, #8] + ldrh r8, [r1, #38] + ldrh ip, [r1, #40] + mov r5, #0 + sub r3, r4, #4 + str r3, [r0, #8] + str r5, [r4, #-4] + ldr r7, [r0, #8] + mov r6, r0 + sub r3, r7, #4 + str r3, [r0, #8] + mvn r0, #0x540 @ form 0xCAFEBABF in r0 + bic r0, r0, #0x14000 + bic r0, r0, #0x35000000 + mov ip, ip, asl #2 + sub ip, ip, #4 + str r0, [r7, #-4] + ldr r3, [r6, #8] + add r4, r4, ip + sub r0, r3, #68 + str r0, [r6, #8] + str r4, [r0, #8] + str r5, [r0, #44] + str r1, [r0, #16] + str r0, [r0, #64] + str r2, [r3, #-68] + ldr r3, [r1, #8] + cmp r8, r5 + add r3, r3, #48 + str r3, [r0, #4] + ldr r2, [r1, #12] + mov r3, #0 + ldr r1, [r2, #12] + str r5, [r0, #32] + str r5, [r0, #48] + str r1, [r0, #12] + str r5, [r0, #20] + str r3, [r0, #28] + ldr r3, [r6, #8] + str r3, [r0, #60] + ldr r2, [r6, #8] + str r2, [r0, #52] + ldr r3, [r6, #8] + sub r3, r3, #4 + str r3, [r0, #24] + ldrne r3, [r6, #8] + ldreq r3, [r6, #8] + subne r3, r3, r8, asl #2 + strne r3, [r6, #8] + sub r3, r3, #4 + str r3, [r0, #56] + mov r0, r7 + ldmfd sp!, {r4, r5, r6, r7, r8} + bx lr + + ALIGN_CODE +build_normal_synchronized: + stmfd sp!, {r4, r5, r6, r7, r8, sl} + ldr r6, [r0, #8] + mov r4, r0 + ldrh sl, [r1, #38] + ldrh r0, [r1, #40] + mov r5, r1 + mov ip, #0 + sub r3, r6, #4 + mvn r1, #0x540 @ form 0xCAFEBABF in r1 + bic r1, r1, #0x14000 + bic r1, r1, #0x35000000 + str r3, [r4, #8] + str ip, [r6, #-4] + ldr r7, [r4, #8] + mov r0, r0, asl #2 + sub r3, r7, #4 + str r3, [r4, #8] + str r1, [r7, #-4] + ldr r3, [r4, #8] + sub r8, r0, #4 + sub r0, r3, #68 + str r0, [r4, #8] + str r5, [r0, #16] + str ip, [r0, #44] + str r0, [r0, #64] + str r2, [r3, #-68] + add r2, r6, r8 + str r2, [r0, #8] + ldr r3, [r5, #8] + add r3, r3, #48 + str r3, [r0, #4] + ldr r2, [r5, #12] + mov r3, #0 + ldr r1, [r2, #12] + str ip, [r0, #32] + str ip, [r0, #48] + str r1, [r0, #12] + str ip, [r0, #20] + str r3, [r0, #28] + ldr r3, [r4, #8] + str r3, [r0, #60] + ldr r2, [r4, #8] + sub ip, r2, #8 + str ip, [r4, #8] + ldr r3, [r5, #24] + tst r3, #8 + ldrne r3, [r5, #12] + ldreq r1, [r6, r8] + ldrne r2, [r3, #16] + ldrne r1, [r2, #60] + cmp sl, #0 + str r1, [ip, #4] + ldr r2, [r4, #8] + str r2, [r0, #52] + ldr r3, [r4, #8] + sub r3, r3, #4 + str r3, [r0, #24] + ldrne r3, [r4, #8] + ldreq r3, [r4, #8] + subne r3, r3, sl, asl #2 + strne r3, [r4, #8] + sub r3, r3, #4 + str r3, [r0, #56] + mov r0, r7 + ldmfd sp!, {r4, r5, r6, r7, r8, sl} + bx lr + + ALIGN_CODE +build_native: + ldr ip, [r1, #24] + tst ip, #32 + bne build_native_synchronized +build_native_unsynchronized: + stmfd sp!, {r4, r5, r6, r7} + ldr r6, [r0, #8] + ldrh r4, [r1, #42] + mov r5, r0 + mov r7, #0 + sub r3, r6, #4 + mvn ip, #0x540 @ form 0xCAFEBABF in ip + bic ip, ip, #0x14000 + bic ip, ip, #0x35000000 + str r3, [r0, #8] + str r7, [r6, #-4] + ldr r0, [r0, #8] + mov r4, r4, asl #2 + sub r3, r0, #4 + str r3, [r5, #8] + str ip, [r0, #-4] + ldr r3, [r5, #8] + sub r4, r4, #4 + sub ip, r3, #68 + add r6, r6, r4 + str ip, [r5, #8] + str r2, [r3, #-68] + str r6, [ip, #8] + str r1, [ip, #16] + str ip, [ip, #64] + str r7, [ip, #44] + str r7, [ip, #4] + ldr r2, [r1, #12] + mov r3, #2 + ldr r1, [r2, #12] + str r3, [ip, #28] + str r7, [ip, #32] + str r1, [ip, #12] + str r7, [ip, #48] + str r7, [ip, #20] + ldr r3, [r5, #8] + str r3, [ip, #60] + ldr r2, [r5, #8] + str r2, [ip, #52] + ldr r3, [r5, #8] + sub r3, r3, #4 + str r3, [ip, #24] + ldr r2, [r5, #8] + sub r2, r2, #4 + str r2, [ip, #56] + ldmfd sp!, {r4, r5, r6, r7} + bx lr + + ALIGN_CODE +build_native_synchronized: + stmfd sp!, {r4, r5, r6, r7, r8} + ldr r7, [r0, #8] + mov r5, r0 + mov ip, #0 + ldrh r0, [r1, #42] + mov r6, r1 + sub r3, r7, #4 + mvn r1, #0x540 @ form 0xCAFEBABF in r1 + bic r1, r1, #0x14000 + bic r1, r1, #0x35000000 + str r3, [r5, #8] + str ip, [r7, #-4] + ldr r8, [r5, #8] + mov r0, r0, asl #2 + sub r3, r8, #4 + str r3, [r5, #8] + str r1, [r8, #-4] + ldr r3, [r5, #8] + sub r0, r0, #4 + sub r4, r3, #68 + str r4, [r5, #8] + str r6, [r4, #16] + str r4, [r4, #64] + str ip, [r4, #44] + str ip, [r4, #4] + str r2, [r3, #-68] + add r3, r7, r0 + str r3, [r4, #8] + ldr r2, [r6, #12] + mov r3, #2 + ldr r1, [r2, #12] + str r3, [r4, #28] + str ip, [r4, #32] + str r1, [r4, #12] + str ip, [r4, #48] + str ip, [r4, #20] + ldr r3, [r5, #8] + str r3, [r4, #60] + ldr r2, [r5, #8] + sub r1, r2, #8 + str r1, [r5, #8] + ldr r3, [r6, #24] + tst r3, #8 + ldrne r3, [r6, #12] + ldreq r0, [r7, r0] + ldrne r2, [r3, #16] + ldrne r0, [r2, #60] + str r0, [r1, #4] + ldr r3, [r5, #8] + mov r0, r8 + str r3, [r4, #52] + ldr r2, [r5, #8] + sub r2, r2, #4 + str r2, [r4, #24] + ldr r3, [r5, #8] + sub r3, r3, #4 + str r3, [r4, #56] + ldmfd sp!, {r4, r5, r6, r7, r8} + bx lr + + ALIGN_CODE + .global asm_generate_method_entry +asm_generate_method_entry: + cmp r0, #6 + movcs r0, #0 + adrcc ip, asm_method_table + ldrcc r0, [ip, r0, lsl #2] + bx lr +asm_method_table: + .word normal_entry + .word normal_entry_synchronized + .word native_entry + .word native_entry_synchronized + .word empty_entry + .word accessor_entry + + ALIGN_CODE + .global native_entry_synchronized +native_entry_synchronized: + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + mov r1, r0 + sub sp, sp, #60 + add r0, r2, #THREAD_JAVA_STACK_BASE + mov r7, r2 + bl build_native + ldr r3, [r7, #THREAD_TOP_ZERO_FRAME] + add r1, sp, #52 + str r1, [sp, #0] + ldr sl, .L306native_entry_synchronized +.LPIC19native_entry_synchronized: + add sl, pc, sl + str r3, [r0, #0] + ldr r2, [r7, #THREAD_STACK_SIZE] + ldr r3, [r7, #THREAD_STACK_BASE] + sub r9, r0, #72 + rsb r3, r2, r3 + str r0, [r7, #THREAD_TOP_ZERO_FRAME] + rsb r3, r3, r1 + ldr r2, [r9, #8] + cmp r3, #3072 + str r2, [sp, #4] + blt .L294native_entry_synchronized + ldr ip, [r9, #16] + ldr r3, [ip, #24] + ands r0, r3, #32 + moveq r8, r0 + bne .L295native_entry_synchronized +.L243native_entry_synchronized: + ldr r4, [ip, #84] + cmp r4, #0 + beq .L296native_entry_synchronized +.L248native_entry_synchronized: + ldr r3, .L306native_entry_synchronized+4 + ldr r2, [sl, r3] + cmp r4, r2 + beq .L297native_entry_synchronized +.L249native_entry_synchronized: + ldr r2, [r4, #4] + ldr ip, [ip, #80] + ldr r1, [r7, #THREAD_JAVA_SP] + mov r2, r2, asl #2 + rsb r2, r2, #0 + str ip, [sp, #8] + add r5, r1, r2 + str r5, [r7, #THREAD_JAVA_SP] + add r3, r7, #THREAD_JNI_ENVIRONMENT + str r3, [sp, #52] + ldr r3, [sp, #0] + add lr, r5, #4 + str r3, [r1, r2] + mov r3, #0 + str r3, [sp, #48] + ldr r2, [r9, #16] + ldr r3, [r2, #24] + tst r3, #8 + bne .L298native_entry_synchronized +.L250native_entry_synchronized: + rsb r3, r5, lr + ldr r2, [r4, #4] + mov ip, r3, asr #2 + cmp ip, r2 + bge .L299native_entry_synchronized + ldr fp, .L306native_entry_synchronized+8 + add r3, ip, #6 + add r1, r4, #24 + mov r3, r3, asl #2 + str r1, [sp, #12] + ldr r6, [sl, fp] + add r1, r4, r3 + ldr r0, [sp, #4] + b .L258native_entry_synchronized +.L257native_entry_synchronized: + cmp r3, #8 + subeq r3, r0, #4 + streq r3, [lr], #4 + ldreq r2, [r4, #4] + add ip, ip, #1 + subeq r0, r3, #4 + cmp ip, r2 + add r1, r1, #4 + bge .L252native_entry_synchronized +.L258native_entry_synchronized: + ldr r3, [r1, #0] + cmp r3, r6 + beq .L300native_entry_synchronized + ldr r3, [r3, #0] + cmp r3, #4 + bne .L257native_entry_synchronized +.L293native_entry_synchronized: + str r0, [lr], #4 +.L291native_entry_synchronized: + ldr r2, [r4, #4] + add ip, ip, #1 + cmp ip, r2 + sub r0, r0, #4 + add r1, r1, #4 + blt .L258native_entry_synchronized +.L252native_entry_synchronized: + ldr r0, [r7, #THREAD_TOP_ZERO_FRAME] + ldr r1, [sp, #8] + mov r3, r5 + str r0, [r7, #THREAD_LAST_JAVA_SP] + mov r2, #_thread_in_native + mov r0, r4 + str r2, [r7, #THREAD_STATE] + add r2, sp, #40 + bl ffi_call + ldr r2, .L306native_entry_synchronized+12 + mov r3, #_thread_in_native_trans + str r3, [r7, #THREAD_STATE] + ldr r3, [sl, r2] + ldr r1, [r3, #0] + cmp r1, #1 + ble .L259native_entry_synchronized + ldr r3, .L306native_entry_synchronized+16 + ldr r2, [sl, r3] + ldrb r1, [r2, #0] @ zero_extendqisi2 + cmp r1, #0 + bne .L301native_entry_synchronized + ldr r3, .L306native_entry_synchronized+20 + ldr r2, .L306native_entry_synchronized+24 + ldr r0, [sl, r3] + ldr r1, [sl, r2] + mov r2, #1 + ldr r3, [r0, #0] + ldr ip, [r1, #0] + and r3, r3, r7, lsr #3 + str r2, [ip, r3] +.L259native_entry_synchronized: + ldr r3, .L306native_entry_synchronized+28 + ldr r2, [sl, r3] + ldr r1, [r2, #0] + cmp r1, #0 + beq .L302native_entry_synchronized +.L261native_entry_synchronized: + mov r0, r7 + bl _ZN10JavaThread40check_special_condition_for_native_transEPS_ + .p2align 3 +.L262native_entry_synchronized: + mov r3, #_thread_in_Java + mov r2, #0 + str r3, [r7, #THREAD_STATE] + str r2, [r7, #THREAD_LAST_JAVA_SP] + ldr r0, [sp, #12] + ldr r1, [r4, #4] + ldr r2, [sl, fp] + ldr r3, [r0, r1, asl #2] + cmp r3, r2 + beq .L303native_entry_synchronized +.L263native_entry_synchronized: + ldr r2, [r7, #THREAD_ACTIVE_HANDLES] + cmp r8, #0 + mov r3, #0 + str r3, [r2, #128] + beq .L292native_entry_synchronized + ldr r1, [r7, #THREAD_PENDING_EXC] + cmp r1, #0 + beq .L304native_entry_synchronized +.L241native_entry_synchronized: + ldr r2, [r7, #THREAD_TOP_ZERO_FRAME] + cmp r1, #0 + add r1, r2, #4 + str r1, [r7, #THREAD_JAVA_SP] + ldr r3, [r2, #0] + str r3, [r7, #THREAD_TOP_ZERO_FRAME] + ldr r2, [r9, #16] + ldrh r3, [r2, #42] + mov r3, r3, asl #2 + add r4, r1, r3 + str r4, [r7, #THREAD_JAVA_SP] + beq .L305native_entry_synchronized +.L279native_entry_synchronized: + add sp, sp, #60 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L300native_entry_synchronized: + ldr r3, [r0, #0] + cmp r3, #0 + beq .L293native_entry_synchronized + ldr r3, [r7, #THREAD_JAVA_SP] + sub r2, r3, #4 + str r2, [r7, #THREAD_JAVA_SP] + str r0, [r3, #-4] + ldr r2, [r7, #THREAD_JAVA_SP] + str r2, [lr], #4 + b .L291native_entry_synchronized +.L302native_entry_synchronized: + ldr r3, [r7, #THREAD_SUSPEND_FLAGS] + cmp r3, #0 + beq .L262native_entry_synchronized + mov r0, r7 + bl _ZN10JavaThread40check_special_condition_for_native_transEPS_ + b .L262native_entry_synchronized +.L298native_entry_synchronized: + ldr r1, [r2, #12] + add r3, sp, #56 + mov r2, r9 + ldr r0, [r1, #16] + add lr, lr, #4 + ldr r1, [r0, #60] + str r1, [r2, #48]! + str r2, [r3, #-8]! + str r3, [r5, #4] + b .L250native_entry_synchronized +.L295native_entry_synchronized: + ldr r8, [r9, #52] + ldr fp, .L306native_entry_synchronized+32 + ldr r5, [r8, #4] + ldr r3, [r5, #0] + orr r4, r3, #1 + str r4, [r8, #0] + .p2align 3 +.L245native_entry_synchronized: + ldr r6, [r5, #0] + mov r0, r4 + cmp r4, r6 + mov r1, r8 + mov r2, r5 + bne .L244native_entry_synchronized + blx fp + cmp r0, #0 + bne .L245native_entry_synchronized +.L244native_entry_synchronized: + cmp r4, r6 + beq .L290native_entry_synchronized + bic r1, r4, #3 + ldr r3, [r7, #0] + mov r0, r7 + ldr ip, [r3, #THREAD_VTABLE_IS_LOCK_OWNED] + blx ip + subs r4, r0, #0 + beq .L247native_entry_synchronized + mov r3, #0 + str r3, [r8, #0] + ldr ip, [r9, #16] + b .L243native_entry_synchronized +.L304native_entry_synchronized: + ldr r6, [r8, #0] + ldr r5, [r8, #4] + cmp r6, #0 + str r1, [r8, #4] + ldrne fp, .L306native_entry_synchronized+32 + beq .L292native_entry_synchronized + .p2align 3 +.L283native_entry_synchronized: + ldr r4, [r5, #0] + mov r0, r8 + cmp r8, r4 + mov r1, r6 + mov r2, r5 + bne .L265native_entry_synchronized + blx fp + cmp r0, #0 + bne .L283native_entry_synchronized +.L265native_entry_synchronized: + cmp r8, r4 + beq .L292native_entry_synchronized + add r4, sp, #16 + mov r0, r4 + mov r1, r7 + str r5, [r8, #4] + bl _ZN10HandleMark10initializeEP6Thread + ldr r3, [r7, #THREAD_TOP_ZERO_FRAME] + mov r0, r7 + mov r1, r8 + str r3, [r7, #THREAD_LAST_JAVA_SP] + bl _ZN18InterpreterRuntime11monitorexitEP10JavaThreadP15BasicObjectLock + mov r3, #0 + mov r0, r4 + str r3, [r7, #THREAD_LAST_JAVA_SP] + bl _ZN10HandleMarkD1Ev +.L292native_entry_synchronized: + ldr r1, [r7, #4] + b .L241native_entry_synchronized +.L294native_entry_synchronized: + str r0, [r7, #THREAD_LAST_JAVA_SP] + mov r0, r7 + bl _ZN18InterpreterRuntime24throw_StackOverflowErrorEP10JavaThread + mov r3, #0 + ldr r1, [r7, #THREAD_PENDING_EXC] + str r3, [r7, #THREAD_LAST_JAVA_SP] + b .L241native_entry_synchronized +.L247native_entry_synchronized: + ldr r3, [r7, #THREAD_TOP_ZERO_FRAME] + mov r1, r8 + mov r0, r7 + str r3, [r7, #THREAD_LAST_JAVA_SP] + bl _ZN18InterpreterRuntime12monitorenterEP10JavaThreadP15BasicObjectLock + ldr r1, [r7, #THREAD_PENDING_EXC] + str r4, [r7, #THREAD_LAST_JAVA_SP] + cmp r1, #0 + bne .L241native_entry_synchronized + .p2align 3 +.L290native_entry_synchronized: + ldr ip, [r9, #16] + b .L243native_entry_synchronized +.L301native_entry_synchronized: + ldr r3, .L306native_entry_synchronized+28 + ldr r2, [sl, r3] + ldr r1, [r2, #0] + cmp r1, #0 + bne .L261native_entry_synchronized + b .L302native_entry_synchronized +.L303native_entry_synchronized: + ldr r3, [sp, #40] + cmp r3, #0 + streq r3, [r9, #48] + ldrne r3, [r3, #0] + strne r3, [r9, #48] + b .L263native_entry_synchronized +.L305native_entry_synchronized: + ldr r0, [r9, #16] + bl _ZNK13methodOopDesc11result_typeEv + ldr r2, .L306native_entry_synchronized+36 + ldr r1, [sl, r2] + ldr r3, [r1, r0, asl #2] + sub r3, r4, r3, asl #2 + str r3, [r7, #THREAD_JAVA_SP] + ldr r0, [r9, #16] + bl _ZNK13methodOopDesc11result_typeEv + sub r0, r0, #4 + cmp r0, #9 + addls pc, pc, r0, asl #2 + b .L279native_entry_synchronized +.L278native_entry_synchronized: + b .L269native_entry_synchronized + b .L270native_entry_synchronized + b .L271native_entry_synchronized + b .L272native_entry_synchronized + b .L273native_entry_synchronized + b .L274native_entry_synchronized + b .L275native_entry_synchronized + b .L276native_entry_synchronized + b .L277native_entry_synchronized + b .L277native_entry_synchronized +.L299native_entry_synchronized: + add r0, r4, #24 + ldr fp, .L306native_entry_synchronized+8 + str r0, [sp, #12] + b .L252native_entry_synchronized +.L277native_entry_synchronized: + ldr r3, [r9, #48] + ldr r0, [sp, #4] + str r3, [r0, #0] + b .L279native_entry_synchronized +.L276native_entry_synchronized: + add r3, sp, #40 + ldmia r3, {r3-r4} + ldr r0, [sp, #4] + stmda r0, {r3-r4} + b .L279native_entry_synchronized +.L275native_entry_synchronized: + ldr r3, [sp, #40] + ldr r2, [sp, #4] + str r3, [r2, #0] + b .L279native_entry_synchronized +.L274native_entry_synchronized: + ldrsh r3, [sp, #40] + ldr r1, [sp, #4] + str r3, [r1, #0] + b .L279native_entry_synchronized +.L273native_entry_synchronized: + ldrsb r3, [sp, #40] + ldr r0, [sp, #4] + str r3, [r0, #0] + b .L279native_entry_synchronized +.L272native_entry_synchronized: + add r3, sp, #40 + ldmia r3, {r3-r4} + ldr r2, [sp, #4] + stmda r2, {r3-r4} + b .L279native_entry_synchronized +.L271native_entry_synchronized: + ldr r3, [sp, #40] @ float + ldr r1, [sp, #4] + str r3, [r1, #0] @ float + b .L279native_entry_synchronized +.L270native_entry_synchronized: + ldrh r3, [sp, #40] + ldr r2, [sp, #4] + str r3, [r2, #0] + b .L279native_entry_synchronized +.L269native_entry_synchronized: + ldr r1, [sp, #4] + ldrb r3, [sp, #40] @ zero_extendqisi2 + subs r3, r3, #0 + movne r3, #1 + str r3, [r1, #0] + b .L279native_entry_synchronized +.L296native_entry_synchronized: + ldr r3, [r7, #THREAD_TOP_ZERO_FRAME] + mov r0, r7 + str r3, [r7, #THREAD_LAST_JAVA_SP] + ldr r1, [r9, #16] + bl _ZN18InterpreterRuntime19prepare_native_callEP10JavaThreadP13methodOopDesc + ldr r1, [r7, #THREAD_PENDING_EXC] + str r4, [r7, #THREAD_LAST_JAVA_SP] + cmp r1, #0 + bne .L241native_entry_synchronized + ldr ip, [r9, #16] + ldr r4, [ip, #84] + b .L248native_entry_synchronized +.L297native_entry_synchronized: + ldr r3, [r7, #THREAD_TOP_ZERO_FRAME] + mov r2, #0 + mov r0, r7 + str r3, [r7, #THREAD_LAST_JAVA_SP] + mov r3, r2 + ldr r1, [r9, #16] + bl _ZN18InterpreterRuntime22slow_signature_handlerEP10JavaThreadP13methodOopDescPiS4_ + ldr r1, [r7, #THREAD_PENDING_EXC] + mov r3, #0 + cmp r1, #0 + str r3, [r7, #THREAD_LAST_JAVA_SP] + mov r4, r0 + bne .L241native_entry_synchronized + ldr ip, [r9, #16] + b .L249native_entry_synchronized +.L307native_entry_synchronized: + ALIGN_DATA +.L306native_entry_synchronized: + .word _GLOBAL_OFFSET_TABLE_-(.LPIC19native_entry_synchronized+8) + .word _ZN18InterpreterRuntime22slow_signature_handlerEP10JavaThreadP13methodOopDescPiS4_(GOT) + .word ffi_type_pointer(GOT) + .word _ZN2os16_processor_countE(GOT) + .word UseMembar(GOT) + .word _ZN2os20_serialize_page_maskE(GOT) + .word _ZN2os19_mem_serialize_pageE(GOT) + .word _ZN20SafepointSynchronize6_stateE(GOT) + .word -61504 + .word type2size(GOT) + + ALIGN_CODE + .global empty_entry +empty_entry: + ldr r3, .L1359 + ldr r1, .L1359+4 +.LPIC19: + add r3, pc, r3 + + ldr ip, [r3, r1] + ldr r3, [ip, #0] + cmp r3, #0 + bne normal_entry_synchronized + + ldrh r3, [r0, #42] + ldr r1, [r2, #THREAD_JAVA_SP] + add r1, r1, r3, lsl #2 + str r1, [r2, #THREAD_JAVA_SP] + bx lr +.L1359: + .word _GLOBAL_OFFSET_TABLE_-(.LPIC19+8) + .word _ZN20SafepointSynchronize6_stateE(GOT) + +@ ---- START execute.s --------------------------------------------------------------------- + +#ifdef HW_NULL_PTR_CHECK + +#define uc_mcontext 20 +#define arm_registers_offset 12 +#define arm_cpsr_offset 16*4 + + .global asm_check_null_ptr +asm_check_null_ptr: + add r0, r0, #uc_mcontext + arm_registers_offset + ldr r1, [r0, #15*4] + adr ip, abort_table +abort_loop: + ldr r2, [ip], #4 + cmp r2, #0 + moveq r0, #0 + bxeq lr + cmp r2, r1 + bne abort_loop + + adr r3, abort_table+4 + sub r3, ip, r3 + + adr ip, jpc_correction_table + ldrb r3, [ip, r3, lsr #2] + + ldr ip, [r0, #5*4] + sub ip, ip, r3 + str ip, [r0, #5*4] + + adrl r3, null_ptr_exception + str r3, [r0, #15*4] +do_setcontext: + mov r0, #1 + bx lr +abort_table: + .word .abortentry5 + .word .abortentry6 + .word .abortentry7 + .word .abortentry8 + .word .abortentry9 + .word .abortentry10 + .word .abortentry11 + .word .abortentry12 + .word .abortentry13 + + .word .abortentry19 + .word .abortentry20 + .word .abortentry21 + .word .abortentry22 + .word .abortentry23 + .word .abortentry24 + .word .abortentry25 + .word .abortentry26 + .word .abortentry27 + .word .abortentry28 + .word .abortentry29 + .word .abortentry30 + .word .abortentry31 + .word .abortentry32 + + .word .abortentry38 + .word .abortentry39 + .word .abortentry40 + .word .abortentry41 + .word .abortentry42 + .word .abortentry42_1 + .word .abortentry43 + .word .abortentry44 + .word .abortentry45 + .word .abortentry46 + .word .abortentry47 + .word .abortentry48 + .word .abortentry49 + .word .abortentry50 + .word .abortentry51 + .word .abortentry52 + + .word .abortentry58 + .word .abortentry59 + .word .abortentry60 + + .word .abortentry61 + .word .abortentry62 + .word .abortentry63 + .word .abortentry64 + .word .abortentry65 + .word .abortentry66 + .word .abortentry67 + .word .abortentry68 + .word .abortentry69 + .word .abortentry70 + .word .abortentry71 + .word .abortentry72 + + .word .abortentry73 + .word .abortentry74 + .word .abortentry75 + .word .abortentry76 + .word .abortentry77 + + .word .abortentry78 + .word .abortentry79 + .word .abortentry80 + .word .abortentry81 + .word .abortentry82 + .word .abortentry83 + .word .abortentry84 + .word .abortentry85 + .word .abortentry86 + .word .abortentry87 + + .word .abortentry88 + .word .abortentry89 + .word .abortentry90 + .word .abortentry91 + .word .abortentry92 + .word .abortentry93 + .word .abortentry94 + .word .abortentry95 + .word .abortentry96 + .word .abortentry97 + .word .abortentry98 + .word .abortentry99 + .word .abortentry100 + .word .abortentry101 + .word .abortentry102 + .word .abortentry103 + .word .abortentry104 + .word .abortentry105 + .word .abortentry106 + .word .abortentry107 + .word .abortentry108 + .word .abortentry109 + .word 0 +jpc_correction_table: + .byte 1, 1, 1, 1, 1, 1, 1, 1, 1 + .byte 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 + .byte 2, 3, 4, 3, 2, 2, 0, 1, 3, 2, 0, 1, 0, 1, 0, 1 + .byte 2, 2, 2 + .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .byte 1, 1, 1, 1, 1 + .byte 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 + .byte 3, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 1, 1, 1, 1, 1 + ALIGN_WORD + +#else + .global asm_check_null_ptr +asm_check_null_ptr: + mov r0, #0 + bx lr + +#endif + + ALIGN_CODE +fast_native_entry: + ldr r2, [istate, #ISTATE_THREAD] + mov r11, tmp2 + ldrh r1, [r11, #42] + ldr r4, [r2, #THREAD_JAVA_SP] + ldr ip, [r2, #THREAD_TOP_ZERO_FRAME] + mov r0, #0 + mvn r10, #0x540 @ form 0xCAFEBABF in r10 + bic r10, r10, #0x14000 + bic r10, r10, #0x35000000 + sub r9, r4, #76 + mov r7, r9 + str r9, [r2, #THREAD_JAVA_SP] @ drop stack + sub r5, r9, #4 @ stack limit = r9 - 4 + mov r3, r9 + stmdb r4, {r0, r3, r5, r7, r9, r10, ip} + str r0, [r9, #ISTATE_CALLEE] + str r0, [r9, #ISTATE_PREV_LINK] + str r0, [r9, #ISTATE_MSG] + str r0, [r9, #ISTATE_MDX] + sub r7, r4, #4 + add r7, r7, r1, lsl #2 + mov r5, #0 + ldr r10, [r11, #12] + ldr r10, [r10, #12] + stmia r9, {r2, r5, r7, r10, r11} + add r0, r9, #72 + mov r9, r2 +.LPIC18_fast_native_entry: + ldr r2, [r9, #THREAD_STACK_SIZE] + ldr r3, [r9, #THREAD_STACK_BASE] + rsb r3, r2, r3 + rsb r3, r3, sp + cmp r3, #4096 + str r0, [r9, #THREAD_TOP_ZERO_FRAME] + blt .fast_native_entry_throw_stack_overflow + ldr r5, [r11, #84] + cmp r5, #0 + bne .fast_native_entry_got_handleraddr + str r0, [r9, #THREAD_LAST_JAVA_SP] + mov r0, r9 + mov r1, r11 + bl _ZN18InterpreterRuntime19prepare_native_callEP10JavaThreadP13methodOopDesc + ldr r11, [r9, #THREAD_TOP_ZERO_FRAME] + ldr r1, [r9, #THREAD_PENDING_EXC] + str r5, [r9, #THREAD_LAST_JAVA_SP] + ldr r11, [r11, #-72 + ISTATE_METHOD] + cmp r1, #0 + bne .fast_native_entry_exception + ldr r5, [r11, #84] +.fast_native_entry_got_handleraddr: + ldr r2, [dispatch, #InterpreterRuntime_slow_signature_handler_Address-XXX] + cmp r5, r2 + bne .fast_native_entry_get_handler + ldr r3, [r9, #THREAD_TOP_ZERO_FRAME] + mov r2, #0 + mov r0, r9 + str r3, [r9, #THREAD_LAST_JAVA_SP] + mov r3, r2 + mov r1, r11 + bl _ZN18InterpreterRuntime22slow_signature_handlerEP10JavaThreadP13methodOopDescPiS4_ + ldr r11, [r9, #THREAD_TOP_ZERO_FRAME] + ldr r1, [r9, #THREAD_PENDING_EXC] + mov r3, #0 + ldr r11, [r11, #-72 + ISTATE_METHOD] + cmp r1, #0 + str r3, [r9, #THREAD_LAST_JAVA_SP] + mov r5, r0 + bne .fast_native_entry_exception +.fast_native_entry_get_handler: + + sub ip, r7, r4 + mov ip, ip, asr #2 + add lr, ip, #4 + bic lr, lr, #1 + + add r3, r4, #ISTATE_OOP_TEMP-76 + + mov r4, arm_sp + sub arm_sp, arm_sp, #16 + sub arm_sp, arm_sp, lr, lsl #2 + mov lr, arm_sp + + add r1, r5, #24 + + add r2, r9, #THREAD_JNI_ENVIRONMENT + str r2, [lr], #4 + add r1, r1, #4 + + ldr r2, [r11, #24] + tst r2, #8 + beq .do_fast_copy_args + + ldr r2, [r11, #12] + ldr r2, [r2, #16] + ldr r2, [r2, #60] + str r2, [r3] + + str r3, [lr], #4 + add r1, r1, #4 + +.do_fast_copy_args: + cmp ip, #0 + blt .fast_no_args + +.fast_copy_args: + ldr r0, [r1], #4 + ldrh r3, [r0, #6] + cmp r3, #FFI_TYPE_DOUBLE + cmpne r3, #FFI_TYPE_SINT64 + beq .fast_copy_long + + cmp r3, #FFI_TYPE_POINTER + beq .fast_copy_ptr + + ldr r2, [r7], #-4 + str r2, [lr], #4 + subs ip, ip, #1 + bge .fast_copy_args + b .fast_no_args + +.fast_copy_long: + tst lr, #4 + addne lr, lr, #4 + ldmda r7!, {r2, r3} + stmia lr!, {r2, r3} + subs ip, ip, #2 + bge .fast_copy_args + b .fast_no_args + +.fast_copy_ptr: + ldr r2, [r7], #-4 + cmp r2, #0 + addne r2, r7, #4 + str r2, [lr], #4 + subs ip, ip, #1 + bge .fast_copy_args + +.fast_no_args: + ldr r0, [r9, #THREAD_TOP_ZERO_FRAME] + str r0, [r9, #THREAD_LAST_JAVA_SP] + + mov r2, #_thread_in_native + str r2, [r9, #THREAD_STATE] + + ldr ip, [r11, #80] + ldrh r11, [r11, #42] + ldmia arm_sp!, {r0, r1, r2, r3} + blx ip + + mov arm_sp, r4 + + mov r3, #_thread_in_native_trans + str r3, [r9, #THREAD_STATE] + + ldr r3, [dispatch, #SafePointSynchronize_state_Address-XXX] + + ldr r3, [r3, #0] + cmp r3, #0 + ldreq r3, [r9, #THREAD_SUSPEND_FLAGS] + cmpeq r3, #0 + bne .fast_native_entry_do_special + +.fast_native_entry_do_return: + mov r3, #_thread_in_Java + mov r2, #0 + str r3, [r9, #THREAD_STATE] + str r2, [r9, #THREAD_LAST_JAVA_SP] + + add r2, r5, #24 + ldr r3, [r5, #4] + + ldr r5, [r9, #THREAD_TOP_ZERO_FRAME] +@ ldr r11, [r5, #-72 + ISTATE_METHOD] + + ldr lr, [r5], #4 + + add r5, r5, r11, lsl #2 + + ldr ip, [r2, r3, asl #2] + ldrh r2, [ip, #6] + + cmp r2, #FFI_TYPE_POINTER + beq .fast_native_return_obj + + str lr, [r9, #THREAD_TOP_ZERO_FRAME] @ Defer dropping frame until after we have dealt with + @ objects + + ldr ip, [r9, #THREAD_ACTIVE_HANDLES] + mov r3, #0 @ ECN: OK, not an obj, save to clear handles + str r3, [ip, #128] + + cmp r2, #FFI_TYPE_VOID + beq .fast_native_return_void + cmp r2, #FFI_TYPE_FLOAT + cmpne r2, #FFI_TYPE_SINT32 + beq .fast_native_return_w + cmp r2, #FFI_TYPE_DOUBLE + cmpne r2, #FFI_TYPE_SINT64 + beq .fast_native_return_dw + + cmp r2, #FFI_TYPE_UINT16 + beq .fast_native_return_char + cmp r2, #FFI_TYPE_SINT16 + beq .fast_native_return_short + cmp r2, #FFI_TYPE_BOOL + beq .fast_native_return_bool + cmp r2, #FFI_TYPE_SINT8 + beq .fast_native_return_byte + + str r0, [r0, -r0] + +.fast_native_return_dw: + stmdb r5!, {r0, r1} + str r5, [r9, #THREAD_JAVA_SP] + b .fast_native_exit +.fast_native_return_byte: + mov r0, r0, lsl #24 + mov r0, r0, asr #24 + str r0, [r5, #-4]! + str r5, [r9, #THREAD_JAVA_SP] + b .fast_native_exit +.fast_native_return_char: + mov r0, r0, lsl #16 + mov r0, r0, lsr #16 + str r0, [r5, #-4]! + str r5, [r9, #THREAD_JAVA_SP] + b .fast_native_exit +.fast_native_return_bool: + ands r0, r0, #255 + movne r0, #1 + str r0, [r5, #-4]! + str r5, [r9, #THREAD_JAVA_SP] + b .fast_native_exit + +.fast_native_entry_throw_stack_overflow: + str r0, [r9, #THREAD_LAST_JAVA_SP] + mov r0, r9 + bl _ZN18InterpreterRuntime24throw_StackOverflowErrorEP10JavaThread + mov r3, #0 + ldr r1, [r9, #THREAD_PENDING_EXC] + str r3, [r9, #THREAD_LAST_JAVA_SP] +.fast_native_entry_exception: + ldr r5, [r9, #THREAD_TOP_ZERO_FRAME] + ldr r3, [r5], #4 + str r3, [r9, #THREAD_TOP_ZERO_FRAME] + + ldrh r3, [r11, #42] + add r5, r5, r3, lsl #2 + str r5, [r9, #THREAD_JAVA_SP] + b .fast_native_exit + +.fast_native_entry_do_special: + stmdb sp!, {r0, r1} + mov r0, r9 + bl _ZN10JavaThread40check_special_condition_for_native_transEPS_ + ldmia sp!, {r0, r1} + b .fast_native_entry_do_return + +.fast_native_return_obj: + cmp r0, #0 + ldrne r0, [r0] + str r0, [r5, #-4]! + + str lr, [r9, #THREAD_TOP_ZERO_FRAME] @ Defer dropping frame until after we have dealt with + @ objects + + str r5, [r9, #THREAD_JAVA_SP] + ldr r2, [r9, #THREAD_ACTIVE_HANDLES] + mov r3, #0 @ ECN: Now that the object is safe on the Java stack + str r3, [r2, #128] @ stack, with the Thread SP updated, clear the active_handles. + b .fast_native_exit +.fast_native_return_short: + mov r0, r0, lsl #16 + mov r0, r0, asr #16 +.fast_native_return_w: + str r0, [r5, #-4]! +.fast_native_return_void: + str r5, [r9, #THREAD_JAVA_SP] +.fast_native_exit: + ldr r2, [istate, #ISTATE_STACK_LIMIT] + sub r5, r5, #4 + str r5, [istate, #ISTATE_STACK] + + ldr r1, [r9, #THREAD_TOP_ZERO_FRAME] + add r2, r2, #4 + str r2, [r9, #THREAD_JAVA_SP] + str r1, [r9, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr jpc, [istate, #ISTATE_BCP] + ldr r3, [r0, #THREAD_PENDING_EXC] + DISPATCH_START 3 + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_NEXT + cmp r3, #0 + DISPATCH_NEXT + bne invokespecial_exception_fix + DISPATCH_FINISH + +#include "bytecodes.s" + + Opcode idiv + + POP2 r0, r1 +int_div: + cmp r0, #0 + beq .divc_0 + + ands a4, a1, #0x80000000 + rsbmi a1, a1, #0 + eors ip, a4, a2, ASR #32 + rsbcs a2, a2, #0 + movs a3, a1 +.s_loop: + cmp a3, a2, LSR #8 + movls a3, a3, LSL #8 + blo .s_loop + cmp a3, a2, LSR #1 + bhi .s_jump7 + cmp a3, a2, LSR #2 + bhi .s_jump6 + cmp a3, a2, LSR #3 + bhi .s_jump5 + cmp a3, a2, LSR #4 + bhi .s_jump4 + cmp a3, a2, LSR #5 + bhi .s_jump3 + cmp a3, a2, LSR #6 + bhi .s_jump2 + cmp a3, a2, LSR #7 + bhi .s_jump1 +.s_loop2: +@ not executed when falling into .s_loop2 + movhi a3, a3, LSR #8 + cmp a2, a3, LSL #7 + adc a4, a4, a4 + subcs a2, a2, a3, LSL #7 + cmp a2, a3, LSL #6 +.s_jump1: + adc a4, a4, a4 + subcs a2, a2, a3, LSL #6 + cmp a2, a3, LSL #5 +.s_jump2: + adc a4, a4, a4 + subcs a2, a2, a3, LSL #5 + cmp a2, a3, LSL #4 +.s_jump3: + adc a4, a4, a4 + subcs a2, a2, a3, LSL #4 + cmp a2, a3, LSL #3 +.s_jump4: + adc a4, a4, a4 + subcs a2, a2, a3, LSL #3 + cmp a2, a3, LSL #2 +.s_jump5: + adc a4, a4, a4 + subcs a2, a2, a3, LSL #2 + cmp a2, a3, LSL #1 +.s_jump6: + adc a4, a4, a4 + subcs a2, a2, a3, LSL #1 +.s_jump7: + cmp a2, a3 + adc a4, a4, a4 + subcs a2, a2, a3 + cmp a3, a1 + bne .s_loop2 + DISPATCH_START 1 + movs ip, ip, lsl #1 + DISPATCH_NEXT + rsbcs a4, a4, #0 + DISPATCH_NEXT + DISPATCH_NEXT + PUSH a4 + DISPATCH_FINISH + + Opcode irem + + POP2 r0, r1 +int_rem: + cmp r0, #0 + beq .remc_0 + + ands a4, a1, #0x80000000 + rsbmi a1, a1, #0 + eors ip, a4, a2, ASR #32 + rsbcs a2, a2, #0 + movs a3, a1 +.r_loop: + cmp a3, a2, LSR #8 + movls a3, a3, LSL #8 + blo .r_loop + cmp a3, a2, LSR #1 + bhi .r_jump7 + cmp a3, a2, LSR #2 + bhi .r_jump6 + cmp a3, a2, LSR #3 + bhi .r_jump5 + cmp a3, a2, LSR #4 + bhi .r_jump4 + cmp a3, a2, LSR #5 + bhi .r_jump3 + cmp a3, a2, LSR #6 + bhi .r_jump2 + cmp a3, a2, LSR #7 + bhi .r_jump1 +.r_loop2: +@ not executed when falling into .r_loop2 + movhi a3, a3, LSR #8 + cmp a2, a3, LSL #7 + adc a4, a4, a4 + subcs a2, a2, a3, LSL #7 + cmp a2, a3, LSL #6 +.r_jump1: + adc a4, a4, a4 + subcs a2, a2, a3, LSL #6 + cmp a2, a3, LSL #5 +.r_jump2: + adc a4, a4, a4 + subcs a2, a2, a3, LSL #5 + cmp a2, a3, LSL #4 +.r_jump3: + adc a4, a4, a4 + subcs a2, a2, a3, LSL #4 + cmp a2, a3, LSL #3 +.r_jump4: + adc a4, a4, a4 + subcs a2, a2, a3, LSL #3 + cmp a2, a3, LSL #2 +.r_jump5: + adc a4, a4, a4 + subcs a2, a2, a3, LSL #2 + cmp a2, a3, LSL #1 +.r_jump6: + adc a4, a4, a4 + subcs a2, a2, a3, LSL #1 +.r_jump7: + cmp a2, a3 + adc a4, a4, a4 + subcs a2, a2, a3 + cmp a3, a1 + bne .r_loop2 + DISPATCH_START 1 + movs ip, ip, lsl #1 + rsbmi a2, a2, #0 + PUSH a2 + DISPATCH_FINISH + +@ ip = branch offset +@ r0 = 1st bytecode +@ jpc has been updated + Opcode goto_safe + ldrsb r1, [jpc, #1] + ldrb ip, [jpc, #2] + orr ip, ip, r1, lsl #8 + DISPATCH_START_REG ip +branch_taken: + cmp ip, #0 + bgt branch_no_check + + ldr r3, [dispatch, #SafePointSynchronize_state_Address-XXX] + ldr r1, [r3] + cmp r1, #1 + bne branch_no_check + + ldr r3, [istate, #ISTATE_THREAD] + mov r0, sp + str r3, [sp] + bl _ZN17HandleMarkCleanerD1Ev + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN20SafepointSynchronize5blockEP10JavaThread + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp r3, #0 + ldr locals, [istate, #ISTATE_LOCALS] + bne handle_exception + DISPATCH_START 0 +branch_no_check: + DISPATCH_BYTECODE + + Opcode ifeq_safe + Opcode ifnull_safe + POP r3 + ldrsb r1, [jpc, #1] + ldrb ip, [jpc, #2] + cmp r3, #0 + orreq ip, ip, r1, lsl #8 + ldreqb r0, [jpc, ip]! + ldrneb r0, [jpc, #3]! + beq branch_taken + DISPATCH_BYTECODE + + Opcode ifne_safe + Opcode ifnonnull_safe + POP r3 + ldrsb r1, [jpc, #1] + ldrb ip, [jpc, #2] + cmp r3, #0 + orrne ip, ip, r1, lsl #8 + ldrneb r0, [jpc, ip]! + ldreqb r0, [jpc, #3]! + bne branch_taken + DISPATCH_BYTECODE + + Opcode iflt_safe + POP r3 + ldrsb r1, [jpc, #1] + ldrb ip, [jpc, #2] + cmp r3, #0 + orrlt ip, ip, r1, lsl #8 + ldrltb r0, [jpc, ip]! + ldrgeb r0, [jpc, #3]! + blt branch_taken + DISPATCH_BYTECODE + + Opcode ifge_safe + POP r3 + ldrsb r1, [jpc, #1] + ldrb ip, [jpc, #2] + cmp r3, #0 + orrge ip, ip, r1, lsl #8 + ldrgeb r0, [jpc, ip]! + ldrltb r0, [jpc, #3]! + bge branch_taken + DISPATCH_BYTECODE + + Opcode ifgt_safe + POP r3 + ldrsb r1, [jpc, #1] + ldrb ip, [jpc, #2] + cmp r3, #0 + orrgt ip, ip, r1, lsl #8 + ldrgtb r0, [jpc, ip]! + ldrleb r0, [jpc, #3]! + bgt branch_taken + DISPATCH_BYTECODE + + Opcode ifle_safe + POP r3 + ldrsb r1, [jpc, #1] + ldrb ip, [jpc, #2] + cmp r3, #0 + orrle ip, ip, r1, lsl #8 + ldrleb r0, [jpc, ip]! + ldrgtb r0, [jpc, #3]! + ble branch_taken + DISPATCH_BYTECODE + + Opcode if_icmpeq_safe + Opcode if_acmpeq_safe + POP2 r2, r3 + ldrsb r1, [jpc, #1] + ldrb ip, [jpc, #2] + cmp r3, r2 + orreq ip, ip, r1, lsl #8 + ldreqb r0, [jpc, ip]! + ldrneb r0, [jpc, #3]! + beq branch_taken + DISPATCH_BYTECODE + + Opcode if_icmpne_safe + Opcode if_acmpne_safe + POP2 r2, r3 + ldrsb r1, [jpc, #1] + ldrb ip, [jpc, #2] + cmp r3, r2 + orrne ip, ip, r1, lsl #8 + ldrneb r0, [jpc, ip]! + ldreqb r0, [jpc, #3]! + bne branch_taken + DISPATCH_BYTECODE + + Opcode if_icmplt_safe + POP2 r2, r3 + ldrsb r1, [jpc, #1] + ldrb ip, [jpc, #2] + cmp r3, r2 + orrlt ip, ip, r1, lsl #8 + ldrltb r0, [jpc, ip]! + ldrgeb r0, [jpc, #3]! + blt branch_taken + DISPATCH_BYTECODE + + Opcode if_icmpge_safe + POP2 r2, r3 + ldrsb r1, [jpc, #1] + ldrb ip, [jpc, #2] + cmp r3, r2 + orrge ip, ip, r1, lsl #8 + ldrgeb r0, [jpc, ip]! + ldrltb r0, [jpc, #3]! + bge branch_taken + DISPATCH_BYTECODE + + Opcode if_icmpgt_safe + POP2 r2, r3 + ldrsb r1, [jpc, #1] + ldrb ip, [jpc, #2] + cmp r3, r2 + orrgt ip, ip, r1, lsl #8 + ldrgtb r0, [jpc, ip]! + ldrleb r0, [jpc, #3]! + bgt branch_taken + DISPATCH_BYTECODE + + Opcode if_icmple_safe + POP2 r2, r3 + ldrsb r1, [jpc, #1] + ldrb ip, [jpc, #2] + cmp r3, r2 + orrle ip, ip, r1, lsl #8 + ldrleb r0, [jpc, ip]! + ldrgtb r0, [jpc, #3]! + ble branch_taken + DISPATCH_BYTECODE + + Opcode ireturn_safe + Opcode freturn_safe + Opcode lreturn_safe + Opcode dreturn_safe + Opcode areturn_safe + Opcode return_safe + ldr r3, [dispatch, #SafePointSynchronize_state_Address-XXX] + ldr r1, [r3] + cmp r1, #1 + bne handle_return + ldr r3, [istate, #ISTATE_THREAD] + mov r0, sp + str r3, [sp] + bl _ZN17HandleMarkCleanerD1Ev + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN20SafepointSynchronize5blockEP10JavaThread + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr jpc, [istate, #ISTATE_BCP] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr locals, [istate, #ISTATE_LOCALS] + cmp r3, #0 + beq handle_return + b handle_exception + +resolve_putstatic: + mov r1, #179 + sub jpc, jpc, #3 + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime15resolve_get_putEP10JavaThreadN9Bytecodes4CodeE + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp r3, #0 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + ldr locals, [istate, #ISTATE_LOCALS] + bne getfield_exception + ldrb r3, [jpc, #1] + ldrb r2, [jpc, #2] + DISPATCH_START 3 + orr r3, r3, r2, lsl #8 @ r3 = index + add tmp2, constpool, r3, lsl #4 @ tmp2 = cache + DISPATCH_NEXT + ldr r3, [tmp2, #4] @ r3 = object + ldr lr, [tmp2, #12] @ lr = tos_type + ldr r2, [tmp2, #8] @ r2 = offset + movs lr, lr, lsr #29 + bhi putstatic_w @ C = 1, Z = 0 => R2 == 3, 5, 7 + bcs putstatic_h @ C = 1 => R2 = 1 + beq putstatic_sb @ Z = 1 => R2 = 0 + tst lr, #2 + bne putstatic_dw + b putstatic_sh + +resolve_getstatic: + mov r1, #178 + sub jpc, jpc, #3 + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime15resolve_get_putEP10JavaThreadN9Bytecodes4CodeE + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp r3, #0 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + ldr locals, [istate, #ISTATE_LOCALS] + bne getfield_exception + ldrb r3, [jpc, #1] + ldrb r2, [jpc, #2] + DISPATCH_START 3 + orr r3, r3, r2, lsl #8 @ r3 = index + add tmp2, constpool, r3, lsl #4 @ tmp2 = cache + DISPATCH_NEXT + ldr r3, [tmp2, #4] + ldr r2, [tmp2, #12] + ldr lr, [tmp2, #8] + movs r2, r2, lsr #29 + bhi getstatic_w @ C = 1, Z = 0 => R2 == 3, 5, 7 + bcs getstatic_h @ C = 1 => R2 = 1 + beq getstatic_sb @ Z = 1 => R2 = 0 + tst r2, #2 + bne getstatic_dw + b getstatic_sh + +resolve_putfield: + mov r1, #181 + b resolve_get_put +resolve_getfield: + mov r1, #180 +resolve_get_put: + mov tmp1, lr + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime15resolve_get_putEP10JavaThreadN9Bytecodes4CodeE + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp r3, #0 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + ldr locals, [istate, #ISTATE_LOCALS] + bne getfield_exception +@ Now restart the getfield + ldrb r3, [jpc, #1] + ldrb r2, [jpc, #2] + orr r3, r3, r2, lsl #8 @ r3 = index + add tmp2, constpool, r3, lsl #4 @ tmp2 = cache + bx tmp1 + +accessor_non_w: + bcs accessor_h + beq accessor_sb + tst r0, #2 + bne accessor_dw +accessor_sh: + ldrsh r0, [r3, r1] + str r0, [ip, #0] + bx lr +accessor_h: + ldrh r0, [r3, r1] + str r0, [ip, #0] + bx lr +accessor_sb: + ldrsb r0, [r3, r1] + str r0, [ip, #0] + bx lr +accessor_dw: + add r0, r3, r1 + ldm r0, {r0, r1} + sub ip, ip, #4 + str ip, [r2, #THREAD_JAVA_SP] + stmia ip, {r0, r1} + bx lr + + Opcode getfield + add tmp2, constpool, r1, lsl #12 + ldr r3, [tmp2, r2, lsl #4]! @ tmp2 = cache, r3 = flags + and r3, r3, #0x00ff0000 + cmp r3, #180 << 16 + blne resolve_getfield + + ldr r2, [tmp2, #12] + movs r2, r2, lsr #29 + movhi r0, #opc_igetfield + bls getfield_non_w +rewrite_bytecode: + strb r0, [jpc] + DISPATCH_BYTECODE + +getfield_non_w: + bcs getfield_h @ C = 1 => R2 = 1 + beq getfield_sb @ Z = 1 => R2 = 0 + tst r2, #2 + bne getfield_dw +getfield_sh: + mov r0, #opc_sgetfield + b rewrite_bytecode +getfield_h: + mov r0, #opc_cgetfield + b rewrite_bytecode +getfield_sb: + mov r0, #opc_bgetfield + b rewrite_bytecode +getfield_dw: + mov r0, #opc_lgetfield + b rewrite_bytecode + + Opcode putfield + add tmp2, constpool, r1, lsl #12 + ldr r3, [tmp2, r2, lsl #4]! @ tmp2 = cache, r3 = flags + and r3, r3, #0xff000000 + cmp r3, #181 << 24 + blne resolve_putfield + + ldr r2, [tmp2, #12] + movs r2, r2, lsr #29 + bls putfield_non_w + mov r0, #opc_iputfield + cmp r2, #tos_atos >> 1 + moveq r0, #opc_aputfield + b rewrite_bytecode + +putfield_non_w: + bcs putfield_h + beq putfield_sb + tst r2, #2 + bne putfield_dw +putfield_sh: +putfield_h: + mov r0, #opc_cputfield + b rewrite_bytecode +putfield_sb: + mov r0, #opc_bputfield + b rewrite_bytecode +putfield_dw: + mov r0, #opc_lputfield + b rewrite_bytecode +putfield_a: + mov r0, #opc_aputfield + b rewrite_bytecode + +getstatic_sh: + DISPATCH_STATE 2 + ldrsh tmp2, [r3, lr] + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +getstatic_h: + DISPATCH_STATE 2 + ldrh tmp2, [r3, lr] + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +getstatic_sb: + DISPATCH_STATE 2 + ldrsb tmp2, [r3, lr] + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH +getstatic_dw: + DISPATCH_STATE 2 + add r3, r3, lr + ldm r3, {r2, tmp2} + DISPATCH_NEXT + PUSH2 r2, tmp2 + DISPATCH_FINISH +getstatic_w: + DISPATCH_STATE 2 + ldr tmp2, [r3, lr] + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + +putstatic_sh: +putstatic_h: + DISPATCH_STATE 2 + POP tmp2 + DISPATCH_NEXT + strh tmp2, [r3, r2] + DISPATCH_FINISH +putstatic_w: + DISPATCH_STATE 2 + cmp lr, #tos_atos >> 1 @ >> 1 due to lsr #29 above + beq putstatic_a + POP tmp2 + DISPATCH_NEXT + str tmp2, [r3, r2] + DISPATCH_FINISH +putstatic_sb: + DISPATCH_STATE 2 + POP tmp2 + DISPATCH_NEXT + strb tmp2, [r3, r2] + DISPATCH_FINISH +putstatic_dw: + DISPATCH_STATE 2 + add r2, r2, r3 + POP2 r3, tmp2 + DISPATCH_NEXT + stm r2, {r3, tmp2} + DISPATCH_FINISH +putstatic_a: + POP r1 @ r1 = value + add r0, r3, r2 + PUSH r3 + bl oop_store + ldr r3, [dispatch, #Universe_collectedHeap_Address-XXX] + DISPATCH_START 0 + POP r2 + ldr r3, [r3] + DISPATCH_NEXT + ldr r3, [r3, #12] + DISPATCH_NEXT + mov tmp2, #0 + ldr r3, [r3, #76] + strb tmp2, [r3, r2, lsr #9] + DISPATCH_FINISH + + +resolve_invokevirtual: + mov tmp1, lr + mov r1, #182 + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime14resolve_invokeEP10JavaThreadN9Bytecodes4CodeE + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp r3, #0 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + ldr locals, [istate, #ISTATE_LOCALS] + bne invokevirtual_exception + + ldrb r3, [jpc, #1] + ldrb r2, [jpc, #2] + orr r3, r3, r2, lsl #8 @ r3 = index + add r0, constpool, r3, lsl #4 @ r1 = cache + bx tmp1 + +resolve_invokestatic: + mov tmp1, lr + mov r1, #184 + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime14resolve_invokeEP10JavaThreadN9Bytecodes4CodeE + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #4] + ldr jpc, [istate, #ISTATE_BCP] + cmp r3, #0 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + ldr locals, [istate, #ISTATE_LOCALS] + bne invokestatic_exception + + ldrb r3, [jpc, #1] + ldrb r2, [jpc, #2] + orr r3, r3, r2, lsl #8 @ r3 = index + add r0, constpool, r3, lsl #4 @ r1 = cache + bx tmp1 + +resolve_invokespecial: + mov tmp1, lr + mov r1, #183 + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime14resolve_invokeEP10JavaThreadN9Bytecodes4CodeE + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp r3, #0 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + ldr locals, [istate, #ISTATE_LOCALS] + bne invokespecial_exception + + ldrb r3, [jpc, #1] + ldrb r2, [jpc, #2] + orr r3, r3, r2, lsl #8 @ r3 = index + add r0, constpool, r3, lsl #4 @ r1 = cache + bx tmp1 + + Opcode invokeinterface + ldrb r1, [jpc, #2] @ zero_extendqisi2 + ldrb r3, [jpc, #1] @ zero_extendqisi2 + mov r0, constpool + orr r3, r3, r1, asl #8 + ldr r2, [r0, r3, asl #4] + mov tmp1, r3, asl #4 + add r0, r0, tmp1 + mov r2, r2, asr #16 + and r2, r2, #255 + cmp r2, #185 + beq .invokeinterface_1 + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + ldr r0, [istate, #ISTATE_THREAD] + mov r1, #185 + bl _ZN18InterpreterRuntime14resolve_invokeEP10JavaThreadN9Bytecodes4CodeE + ldr r0, [istate, #ISTATE_THREAD] + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp r3, #0 + ldr locals, [istate, #ISTATE_LOCALS] + bne handle_exception + mov r3, constpool + add r0, r3, tmp1 +.invokeinterface_1: + ldr r3, [r0, #12] + ands tmp_vvv, r3, #16777216 + bne .invokeinterface_6 + ldr lr, [r0, #4] + ldr r3, [r0, #12] + and r3, r3, #255 + ldr r3, [stack, r3, asl #2] + cmp r3, #0 + beq null_ptr_exception + ldr sl, [r3, #4] + add r3, sl, #8 + add tmp1, sl, #304 + ldr r2, [r3, #224] + ldr ip, [r3, #228] + add r2, r2, #1 + bic r2, r2, #1 + cmp ip, #0 + mov r3, r2, asl #2 + add r1, tmp1, r3 + movle r2, tmp_vvv + ble .invokeinterface_4 + ldr r3, [tmp1, r2, asl #2] + cmp lr, r3 + movne r2, tmp_vvv + bne .invokeinterface_3 + b .invokeinterface_5 +.invokeinterface_2: + ldr r3, [r1, #0] + cmp lr, r3 + beq .invokeinterface_5 +.invokeinterface_3: + add r2, r2, #1 + cmp r2, ip + add r1, r1, #8 + blt .invokeinterface_2 +.invokeinterface_4: + cmp r2, ip + beq incompatibleclass_exception +.invokeinterface_5: + ldr r3, [r0, #8] + ldr r2, [r1, #4] + mov r3, r3, asl #2 + add r3, sl, r3 + ldr r0, [r3, r2] + cmp r0, #0 + bne .invokeinterface_7 +abstractmethod_exception: + mov r0, #VMSYMBOLS_AbstractMethodError + b raise_exception +incompatibleclass_exception: + mov r0, #VMSYMBOLS_IncompatibleClassChangeError + b raise_exception + +.invokeinterface_6: + ldr r3, [r0, #12] + mov r1, stack + and r3, r3, #255 + ldr r2, [stack, r3, asl #2] + cmp r2, #0 + beq null_ptr_exception + ldr r3, [r0, #12] + tst r3, #67108864 + ldreq r3, [r0, #12] + ldreq r2, [r0, #8] + andeq r3, r3, #255 + ldrne r0, [r0, #8] + ldreq r1, [stack, r3, asl #2] + moveq r2, r2, asl #2 + ldreq r3, [r1, #4] + addeq r3, r3, r2 + ldreq r0, [r3, #304] +.invokeinterface_7: + str r0, [istate, #ISTATE_CALLEE] + ldr r3, [r0, #76] + mov r1, #0 + str r3, [istate, #36] + str stack, [istate, #ISTATE_STACK] + str jpc, [istate, #ISTATE_BCP] + ldr lr, [istate, #ISTATE_THREAD] + str r1, [lr, #THREAD_LAST_JAVA_SP] + ldr r3, [istate, #ISTATE_STACK] + add r3, r3, #4 + str r3, [lr, #THREAD_JAVA_SP] + ldr ip, [istate, #36] + ldr r2, [istate, #ISTATE_THREAD] + mov r1, ip + ldr ip, [ip] + blx ip + ldr ip, [istate, #ISTATE_THREAD] + ldr r3, [ip, #THREAD_JAVA_SP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + sub r3, r3, #4 + str r3, [istate, #ISTATE_STACK] + ldr r1, [ip, #THREAD_TOP_ZERO_FRAME] + add r2, r2, #4 + str r2, [ip, #THREAD_JAVA_SP] + str r1, [ip, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr jpc, [istate, #ISTATE_BCP] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr locals, [istate, #ISTATE_LOCALS] + cmp r3, #0 + bne handle_exception +invokeinterface_exit: + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH 5 + + Opcode new + ldrb ip, [jpc, #1] @ zero_extendqisi2 + ldrb r2, [jpc, #2] @ zero_extendqisi2 + ldr r3, [istate, #ISTATE_METHOD] + orr r2, r2, ip, asl #8 + ldr lr, [r3, #12] + mov r2, r2, asl #16 + ldr r1, [lr, #8] + add r1, r1, #12 + ldrb r3, [r1, r2, lsr #16] @ zero_extendqisi2 + mov r2, r2, lsr #16 + and r3, r3, #255 + str r2, [sp, #52] + cmp r3, #104 + cmpne r3, #100 + beq .new_1 + mov r3, r2, asl #2 + add r3, lr, r3 + ldr r3, [r3, #32] + add r1, r3, #8 + str r3, [sp, #84] + str r1, [sp, #88] + ldr r3, [r1, #216] + cmp r3, #5 + beq .new_2 +.new_1: + ldr r3, [istate, #ISTATE_METHOD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + ldr r0, [istate, #ISTATE_THREAD] + ldr r1, [r3, #12] + ldr r2, [sp, #52] + bl _ZN18InterpreterRuntime4_newEP10JavaThreadP19constantPoolOopDesci + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr ip, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp ip, #0 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + ldr locals, [istate, #ISTATE_LOCALS] + beq new_exit + b handle_exception +.new_2: + ldr r3, [r1, #4] + tst r3, #1 + bne .new_1 + mov fp, r3, asr #2 + ldr r3, [dispatch, #UseTLAB_Address-XXX] + ldr r2, [dispatch, #ZeroTLAB_Address-XXX] + ldrb r1, [r3] + cmp r1, #0 + ldrb r0, [r2] + bne .new_9 +.new_3: + mov tmp_vvv, fp, asl #2 +.new_4: + ldr r2, [dispatch, #Universe_collectedHeap_Address-XXX] + str r2, [sp, #20] +.new_5: + ldr r1, [sp, #20] + ldr r2, [r1, #0] + mov r0, r2 + ldr r3, [r2, #UNIVERSE_VTABLE] + ldr ip, [r3, #UNIVERSE_VTABLE_TOP_ADDR] + blx ip + ldr r3, [sp, #20] + ldr r2, [r3, #0] + ldr r3, [r2, #UNIVERSE_VTABLE] + ldr tmp_xxx, [r0, #0] + mov r0, r2 + ldr ip, [r3, #UNIVERSE_VTABLE_END_ADDR] + blx ip + add sl, tmp_xxx, tmp_vvv + ldr r3, [r0, #0] + cmp sl, r3 + bhi .new_1 + ldr ip, [sp, #20] + ldr r3, [ip, #0] + mov r0, r3 + ldr r2, [r3, #UNIVERSE_VTABLE] + ldr ip, [r2, #UNIVERSE_VTABLE_TOP_ADDR] + blx ip + mov r2, tmp_xxx + mov r1, r0 + mov r0, sl + bl _ZN6Atomic11cmpxchg_ptrEPvPVvS0_ + cmp r0, tmp_xxx + bne .new_5 + subs tmp_xxx, r0, #0 + beq .new_1 +.new_6: + subs r2, fp, #2 + bne .new_10 +.new_7: + ldr r3, [dispatch, #UseBiasedLocking_Address-XXX] + ldrb r1, [r3] + cmp r1, #0 + moveq r3, #1 + ldrne r0, [sp, #88] + streq r3, [tmp_xxx, #0] + ldrne r3, [r0, #96] + add r0, tmp_xxx, #4 + strne r3, [tmp_xxx, #0] + ldr r3, [dispatch, #always_do_update_barrier_Address-XXX] + ldrb r1, [r3] @ zero_extendqisi2 + cmp r1, #0 + ldreq r2, [sp, #84] + streq r2, [tmp_xxx, #4] + beq .new_8 + ldr r1, [sp, #84] + bl oop_store +.new_8: + str tmp_xxx, [stack], #-4 + b new_exit_1 +.new_9: + ldr r1, [istate, #ISTATE_THREAD] + ldr r2, [r1, #THREAD_TLAB_TOP] + ldr r3, [r1, #THREAD_TLAB_END] + rsb r3, r2, r3 + cmp fp, r3, lsr #2 + bhi .new_3 + cmp r2, #0 + mov tmp_vvv, fp, asl #2 + add r3, r2, tmp_vvv + mov tmp_xxx, r2 + str r3, [r1, #THREAD_TLAB_TOP] + beq .new_4 + cmp r0, #0 + bne .new_7 + b .new_6 +.new_10: + mov r2, r2, asl #2 + add r0, tmp_xxx, #8 + mov r1, #0 + bl memset + b .new_7 +new_exit: + ldr r2, [r0, #THREAD_VM_RESULT] + str r2, [stack], #-4 + ldr r3, [istate, #ISTATE_THREAD] + str ip, [r3, #THREAD_VM_RESULT] +new_exit_1: + ldr locals, [istate, #ISTATE_LOCALS] + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH 3 + +bytecode_interpreter_str: + .ascii "[Bytecode Interpreter]\000" + ALIGN_WORD + + Opcode newarray + ldrb r1, [jpc, #1] @ zero_extendqisi2 + ldr r2, [stack, #4] + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime8newarrayEP10JavaThread9BasicTypei + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr ip, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp ip, #0 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + ldr locals, [istate, #ISTATE_LOCALS] + bne handle_exception + ldr r2, [r0, #THREAD_VM_RESULT] + str r2, [stack, #4] + ldr r3, [istate, #ISTATE_THREAD] + str ip, [r3, #THREAD_VM_RESULT] + DISPATCH 2 + + Opcode anewarray + ldrb r0, [jpc, #1] @ zero_extendqisi2 + ldr r3, [stack, #4] + ldr lr, [istate, #ISTATE_METHOD] + ldrb r2, [jpc, #2] @ zero_extendqisi2 + orr r2, r2, r0, asl #8 + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + ldr r1, [lr, #12] + ldr r0, [istate, #ISTATE_THREAD] + bl _ZN18InterpreterRuntime9anewarrayEP10JavaThreadP19constantPoolOopDescii + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr ip, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp ip, #0 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + ldr locals, [istate, #ISTATE_LOCALS] + bne handle_exception + ldr r2, [r0, #THREAD_VM_RESULT] + str r2, [stack, #4] + ldr r3, [istate, #ISTATE_THREAD] + str ip, [r3, #THREAD_VM_RESULT] + DISPATCH 3 + + Opcode arraylength + ldr r3, [stack, #4] + cmp r3, #0 + beq null_ptr_exception + ldr r1, [r3, #8] + str r1, [stack, #4] + DISPATCH 1 + + Opcode athrow + ldr r1, [stack, #4] + cmp r1, #0 + beq null_ptr_exception + mov r2, #0 + ldr r0, [istate, #ISTATE_THREAD] + mov r3, r2 + bl _ZN12ThreadShadow21set_pending_exceptionEP7oopDescPKci + b handle_exception + + Opcode checkcast + ldr r3, [stack, #4] + cmp r3, #0 + beq .checkcast_exit + ldrb sl, [jpc, #2] @ zero_extendqisi2 + ldrb tmp_xxx, [jpc, #1] @ zero_extendqisi2 + orr r1, sl, tmp_xxx, asl #8 + ldr r3, [istate, #ISTATE_METHOD] + mov r1, r1, asl #16 + ldr r0, [r3, #12] + mov tmp_xxx, r1, lsr #16 + ldr r2, [r0, #8] + add r2, r2, #12 + ldrb r3, [r2, r1, lsr #16] @ zero_extendqisi2 + and r3, r3, #255 + cmp r3, #104 + cmpne r3, #100 + beq .checkcast_2 +.checkcast_1: + mov r1, tmp_xxx, asl #2 + ldr r0, [stack, #4] + ldr r2, [istate, #ISTATE_METHOD] + ldr r0, [r0, #4] + ldr r3, [r2, #12] + add r3, r3, r1 + ldr tmp_vvv, [r3, #32] + cmp tmp_vvv, r0 + beq .checkcast_exit + add tmp_xxx, r0, #8 + mov r0, tmp_xxx + mov r1, tmp_vvv + bl _ZNK5Klass13is_subtype_ofEP12klassOopDesc + cmp r0, #0 + bne .checkcast_exit + mov r0, tmp_xxx + add sl, sp, #216 + ldr r3, [istate, #ISTATE_THREAD] + ldr fp, [r3, #144] @ THREAD_RESOURCE_AREA + ldr r1, [fp, #4] + str r1, [sp, #112] + ldr r2, [fp, #8] + str r2, [sp, #116] + ldr r3, [fp, #12] + str r3, [sp, #120] + bl _ZNK5Klass13external_nameEv + mov tmp_xxx, r0 + add r0, tmp_vvv, #8 + bl _ZNK5Klass13external_nameEv + mov r1, r0 + mov r0, tmp_xxx + bl _ZN13SharedRuntime27generate_class_cast_messageEPKcS1_ + ldr tmp_xxx, [dispatch, #VmSymbols_symbols_Address-XXX] + ldr ip, [istate, #ISTATE_THREAD] + adrl r1, bytecode_interpreter_str + mov r2, #99 + mov r3, #_thread_in_vm + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + str ip, [sl, #-72]! + str r3, [ip, #THREAD_STATE] + ldr r3, [tmp_xxx, #VMSYMBOLS_ClassCastException * 4] + ldr ip, [istate, #ISTATE_THREAD] + str r0, [sp, #0] + mov r0, ip + bl _ZN10Exceptions10_throw_msgEP6ThreadPKciP13symbolOopDescS3_ + mov r0, sl + bl _ZN18ThreadInVMfromJavaD1Ev + ldr r0, [sp, #112] + ldr r3, [r0, #0] + ldr stack, [istate, #ISTATE_STACK] + cmp r3, #0 + ldr jpc, [istate, #ISTATE_BCP] + beq 1f + bl _ZN5Chunk9next_chopEv +1: + ldr r2, [sp, #120] + str r2, [fp, #12] + ldr r3, [sp, #112] + str r3, [fp, #4] + ldr ip, [sp, #116] + str ip, [fp, #8] + b handle_exception +.checkcast_2: + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime13quicken_io_ccEP10JavaThread + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp r3, #0 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + beq .checkcast_1 + b handle_exception +.checkcast_exit: + ldr locals, [istate, #ISTATE_LOCALS] + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH 3 + + Opcode instanceof + ldr r3, [stack, #4] + cmp r3, #0 + beq .instanceof_exit + ldrb tmp1, [jpc, #1] @ zero_extendqisi2 + ldr r3, [istate, #ISTATE_METHOD] + ldrb r2, [jpc, #2] @ zero_extendqisi2 + ldr ip, [r3, #12] + orr r2, r2, tmp1, asl #8 + ldr r1, [ip, #8] + mov r2, r2, asl #16 + add r1, r1, #12 + mov tmp1, r2, lsr #16 + ldrb r3, [r1, r2, lsr #16] @ zero_extendqisi2 + and r3, r3, #255 + cmp r3, #104 + cmpne r3, #100 + bne .instanceof_1 + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime13quicken_io_ccEP10JavaThread + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp r3, #0 + ldr locals, [istate, #ISTATE_LOCALS] + bne handle_exception +.instanceof_1: + mov r1, tmp1, asl #2 + ldr r0, [stack, #4] + ldr r2, [istate, #ISTATE_METHOD] + ldr r0, [r0, #4] + ldr r3, [r2, #12] + add r3, r3, r1 + ldr r1, [r3, #32] + cmp r1, r0 + beq .instanceof_2 + add r0, r0, #8 + bl _ZNK5Klass13is_subtype_ofEP12klassOopDesc + cmp r0, #0 + streq r0, [stack, #4] + beq .instanceof_exit +.instanceof_2: + mov r3, #1 + str r3, [stack, #4] +.instanceof_exit: + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH 3 + + Opcode monitorenter + ldr r1, [stack, #4] + cmp r1, #0 + beq .monitorenter_4 + ldr r0, [istate, #ISTATE_MONITOR_BASE] + ldr r2, [istate, #ISTATE_STACK_BASE] + cmp r2, r0 + beq .monitorenter_5 + mov sl, #0 +.monitorenter_1: + ldr r3, [r2, #4] + cmp r3, #0 + moveq sl, r2 + beq .monitorenter_2 + cmp r1, r3 + beq .monitorenter_3 +.monitorenter_2: + add r2, r2, #8 + cmp r2, r0 + bne .monitorenter_1 +.monitorenter_3: + cmp sl, #0 + beq .monitorenter_5 + str r1, [sl, #4] + ldr r3, [r1, #0] + mov r0, sl + orr tmp1, r3, #1 + mov r2, tmp1 + str tmp1, [sl, #0] + bl _ZN6Atomic11cmpxchg_ptrEPvPVvS0_ + cmp r0, tmp1 + beq .monitorenter_exit + bic r1, tmp1, #3 + ldr r2, [istate, #ISTATE_THREAD] + mov r0, r2 + ldr r3, [r2, #0] + ldr ip, [r3, #THREAD_VTABLE_IS_LOCK_OWNED] + blx ip + cmp r0, #0 + movne lr, #0 + strne lr, [sl, #0] + bne .monitorenter_exit + mov r1, sl + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + ldr r0, [istate, #ISTATE_THREAD] + bl _ZN18InterpreterRuntime12monitorenterEP10JavaThreadP15BasicObjectLock + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr jpc, [istate, #ISTATE_BCP] + ldr r3, [r0, #THREAD_PENDING_EXC] + cmp r3, #0 + ldr locals, [istate, #ISTATE_LOCALS] + beq .monitorenter_exit + b handle_exception +.monitorenter_4: + b null_ptr_exception +.monitorenter_5: + mov lr, #0 + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + ldr r3, [istate, #ISTATE_THREAD] + ldr ip, [istate, #ISTATE_THREAD] + ldr r1, [r3, #THREAD_JAVA_SP] + ldr r3, [r3, #THREAD_JAVA_STACK_BASE] + str lr, [ip, #THREAD_LAST_JAVA_SP] + rsb r3, r3, r1 + cmp r3, #7 + ble vm_fatal_error + sub r3, r1, #8 + ldr r1, [istate, #ISTATE_THREAD] + str r3, [r1, #THREAD_JAVA_SP] + ldr r2, [istate, #ISTATE_STACK] + ldr r1, [istate, #ISTATE_STACK_BASE] + add r3, r2, #4 + cmp r1, r3 + bls .monitorenter_7 + add r0, r2, #8 +.monitorenter_6: + ldr r3, [r0, #-4] + mov r2, r0 + str r3, [r0, #-12] + add r0, r0, #4 + ldr r1, [istate, #ISTATE_STACK_BASE] + cmp r1, r2 + bhi .monitorenter_6 + ldr r2, [istate, #ISTATE_STACK] +.monitorenter_7: + sub r1, r1, #8 + sub r2, r2, #8 + ldr r3, [istate, #ISTATE_STACK_LIMIT] + str r1, [istate, #ISTATE_STACK_BASE] + str r2, [istate, #ISTATE_STACK] + sub r3, r3, #8 + mov r0, #0 + str r3, [istate, #ISTATE_STACK_LIMIT] + str r0, [r1, #4] + ldr r1, [istate, #ISTATE_THREAD] + ldr r3, [r1, #THREAD_TOP_ZERO_FRAME] + str r3, [r1, #THREAD_LAST_JAVA_SP] + ldr stack, [istate, #ISTATE_STACK] + ldr sl, [istate, #ISTATE_STACK_BASE] + ldr jpc, [istate, #ISTATE_BCP] + ldr r3, [stack, #4] + ldr locals, [istate, #ISTATE_LOCALS] + mov r1, r3 + str r3, [sl, #4] + ldr r2, [r3, #0] + mov r0, sl + orr tmp1, r2, #1 + mov r2, tmp1 + str tmp1, [sl, #0] + bl _ZN6Atomic11cmpxchg_ptrEPvPVvS0_ + cmp r0, tmp1 + beq .monitorenter_exit + bic r1, tmp1, #3 + ldr r2, [istate, #ISTATE_THREAD] + mov r0, r2 + ldr r3, [r2, #0] + ldr ip, [r3, #THREAD_VTABLE_IS_LOCK_OWNED] + blx ip + cmp r0, #0 + movne ip, #0 + strne ip, [sl, #0] + bne .monitorenter_exit + mov r1, sl + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime12monitorenterEP10JavaThreadP15BasicObjectLock + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp r3, #0 + ldr locals, [istate, #ISTATE_LOCALS] + beq .monitorenter_exit + b handle_exception +.monitorenter_exit: + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + add stack, stack, #4 + DISPATCH 1 + + Opcode monitorexit + ldr sl, [stack, #4] + cmp sl, #0 + beq .monitorexit_3 + ldr r2, [istate, #ISTATE_MONITOR_BASE] + ldr tmp1, [istate, #ISTATE_STACK_BASE] + cmp tmp1, r2 + bne .monitorexit_2 + b .monitorexit_4 +.monitorexit_1: + add tmp1, tmp1, #8 + cmp tmp1, r2 + beq .monitorexit_4 +.monitorexit_2: + ldr r3, [tmp1, #4] + cmp sl, r3 + bne .monitorexit_1 + ldr r0, [tmp1, #0] + mov lr, #0 + cmp r0, lr + str lr, [tmp1, #4] + beq .monitorexit_exit + mov r1, sl + mov r2, tmp1 + bl _ZN6Atomic11cmpxchg_ptrEPvPVvS0_ + cmp tmp1, r0 + beq .monitorexit_exit + str sl, [tmp1, #4] + mov r1, tmp1 + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + ldr r0, [istate, #ISTATE_THREAD] + bl _ZN18InterpreterRuntime11monitorexitEP10JavaThreadP15BasicObjectLock + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr jpc, [istate, #ISTATE_BCP] + ldr r3, [r0, #THREAD_PENDING_EXC] + cmp r3, #0 + ldr locals, [istate, #ISTATE_LOCALS] + beq .monitorexit_exit + b handle_exception +.monitorexit_3: + b null_ptr_exception +.monitorexit_4: + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime37throw_illegal_monitor_state_exceptionEP10JavaThread + b handle_exception_with_bcp +.monitorexit_exit: + add stack, stack, #4 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH 1 + +vm_fatal_error: + adr r0, .fatal_filename + mov r1, #99 + bl _Z28report_should_not_reach_herePKci + b breakpoint +.fatal_filename: + .ascii "[Optimsed Assembler Interpreter Loop]\000" + ALIGN_WORD + + Opcode aastore + ldr tmp1, [stack, #12] + ldr tmp_vvv, [stack, #8] + cmp tmp1, #0 + ldr sl, [stack, #4] + beq null_ptr_exception + ldr r3, [tmp1, #8] + cmp tmp_vvv, r3 + bcs array_bounds_exception + cmp sl, #0 + beq .aastore_exit + ldr r3, [tmp1, #4] + ldr r0, [sl, #4] + ldr r1, [r3, #136] + cmp r0, r1 + beq .aastore_exit + add r0, r0, #8 + bl _ZNK5Klass13is_subtype_ofEP12klassOopDesc + cmp r0, #0 + moveq r0, #VMSYMBOLS_ArrayStoreException + beq raise_exception +.aastore_exit: + ldr r2, [dispatch, #Universe_collectedHeap_Address-XXX] + add r1, tmp1, #12 + str sl, [r1, tmp_vvv, asl #2]! + ldr r3, [r2] + mov lr, #0 + ldr r3, [r3, #12] + add stack, stack, #12 + ldr r3, [r3, #76] + strb lr, [r3, r1, lsr #9] + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH 1 + + Opcode wide + ldrb r2, [jpc, #1] + ldrb r1, [jpc, #2] @ zero_extendqisi2 + ldrb r3, [jpc, #3] @ zero_extendqisi2 + + sub lr, r2, #opc_aload+1 + cmp lr, #opc_istore - (opc_aload+1) + bcc wide_undef_opc_exception + + sub lr, r2, #opc_iload + cmp r2, #opc_istore + subcs lr, lr, #opc_istore - (opc_aload+1) + cmp r2, #opc_astore+1 + + orr r1, r3, r1, asl #8 + adr r3, wide_case_table + ldrcc pc, [r3, lr, lsl #2] + + cmp r2, #opc_ret + beq do_wide_ret + cmp r2, #opc_iinc + beq do_wide_iinc +wide_undef_opc_exception: + mov r0, #VMSYMBOLS_InternalError + adr r1, undef_opcode_msg + b raise_exception_with_msg +undef_opcode_msg: + .ascii "undefined opcode\000" + ALIGN_WORD + +wide_case_table: + .word case_wide_iload + .word case_wide_lload + .word case_wide_fload + .word case_wide_dload + .word case_wide_aload + .word case_wide_istore + .word case_wide_lstore + .word case_wide_fstore + .word case_wide_dstore + .word case_wide_astore + +case_wide_iload: +case_wide_fload: +case_wide_aload: + ldr r2, [locals, -r1, lsl #2] + PUSH r2 + DISPATCH 4 +case_wide_istore: +case_wide_fstore: + POP r2 + str r2, [locals, -r1, lsl #2] + DISPATCH 4 +case_wide_dload: +case_wide_lload: + sub r1, locals, r1, lsl #2 + ldmda r1, {r1, r2} + PUSH2 r1, r2 + DISPATCH 4 +case_wide_dstore: +case_wide_lstore: + POP2 r2, r3 + sub r1, locals, r1, lsl #2 + stmda r1, {r2, r3} + DISPATCH 4 +case_wide_astore: + mov r3, r1 + mov r0, stack + mvn r1, #0 + mov r2, locals + bl _ZN19BytecodeInterpreter6astoreEPiiS0_i + DISPATCH 4 +do_wide_ret: + ldr r2, [istate, #ISTATE_METHOD] + ldr r2, [r2, #8] + ldr r1, [locals, -r1, lsl #2] + add jpc, r2, r1 + DISPATCH 48 +do_wide_iinc: + ldrsb r2, [jpc, #4] + ldrb r3, [jpc, #5] + orr r2, r3, r2, lsl #8 + ldr r3, [locals, -r1, lsl #2] + add r3, r3, r2 + str r3, [locals, -r1, lsl #2] + DISPATCH 6 + + Opcode multianewarray + ldrb tmp1, [jpc, #3] @ zero_extendqisi2 + ldr r0, [istate, #ISTATE_THREAD] + add r1, stack, tmp1, lsl #2 + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime14multianewarrayEP10JavaThreadPi + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r1, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp r1, #0 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + ldr locals, [istate, #ISTATE_LOCALS] + bne handle_exception + ldr r3, [r0, #THREAD_VM_RESULT] + str r3, [stack, tmp1, asl #2] + ldr r2, [istate, #ISTATE_THREAD] + mov r3, tmp1, asl #2 + sub r3, r3, #4 + str r1, [r2, #THREAD_VM_RESULT] + add stack, stack, r3 + DISPATCH 4 + + Opcode jsr_w + ldr r3, [istate, #ISTATE_METHOD] + ldr r1, [r3, #8] + rsb r2, r1, jpc + sub r2, r2, #43 + str r2, [stack], #-4 + b do_goto_w + + Opcode goto_w + add r2, jpc, #1 + ldrb tmp1, [jpc, #1] @ zero_extendqisi2 + ldrb r3, [r2, #3] @ zero_extendqisi2 + ldrb r0, [r2, #1] @ zero_extendqisi2 + ldrb ip, [r2, #2] @ zero_extendqisi2 + orr r3, r3, tmp1, asl #24 + orr r3, r3, r0, asl #16 + orr r3, r3, ip, asl #8 + cmp r3, #0 + add jpc, jpc, r3 + bgt 1f + + ldr r3, [dispatch, #SafePointSynchronize_state_Address-XXX] + ldr r1, [r3] + cmp r1, #1 + bne 1f + ldr r3, [istate, #ISTATE_THREAD] + mov r0, sp + str r3, [sp] + bl _ZN17HandleMarkCleanerD1Ev + ldr r0, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN20SafepointSynchronize5blockEP10JavaThread + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp r3, #0 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + ldr locals, [istate, #ISTATE_LOCALS] + bne handle_exception +1: + DISPATCH 0 + + Opcode breakpoint + mov r2, jpc + str stack, [istate, #ISTATE_STACK] + str jpc, [istate, #ISTATE_BCP] + ldr r0, [istate, #ISTATE_THREAD] + ldr r1, [istate, #ISTATE_METHOD] + bl _ZN18InterpreterRuntime24get_original_bytecode_atEP10JavaThreadP13methodOopDescPh + ldr stack, [istate, #ISTATE_STACK] + ldmib istate, {jpc, locals} @ phole ldm + mov tmp1, r0 + ldr r0, [istate, #ISTATE_THREAD] + ldr r3, [r0, #THREAD_PENDING_EXC] + cmp r3, #0 + bne handle_exception + str stack, [istate, #ISTATE_STACK] + str jpc, [istate, #ISTATE_BCP] + mov r2, jpc + ldr r1, [istate, #ISTATE_METHOD] + bl _ZN18InterpreterRuntime11_breakpointEP10JavaThreadP13methodOopDescPh + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr jpc, [istate, #ISTATE_BCP] + cmp r3, #0 + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + ldr locals, [istate, #ISTATE_LOCALS] + bne handle_exception + and r0, tmp1, #255 + DISPATCH_BYTECODE + + Opcode undefined + ldr r2, [dispatch, #Bytecodes_name_Address-XXX] + ldrb r3, [jpc, #0] @ zero_extendqisi2 + adrl r0, bytecode_interpreter_str + cmp r3, #last_implemented_bytecode+1 + adrcs ip, unknown_bytecode + ldrcc ip, [r2, r3, asl #2] + adr r2, unimplemented_opcode_msg + mov r1, #99 + str ip, [sp, #0] + bl _Z19report_fatal_varargPKciS0_z + b breakpoint +unimplemented_opcode_msg: + .ascii "\011*** Unimplemented opcode: %d = %s\012\000" +unknown_bytecode: + .ascii "<unknown>\000" + ALIGN_WORD + + Opcode return_register_finalizer + ldr r1, [locals, #0] + ldr r3, [r1, #4] + ldr r2, [r3, #84] + tst r2, #1073741824 + beq handle_return + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + ldr r0, [istate, #ISTATE_THREAD] + bl _ZN18InterpreterRuntime18register_finalizerEP10JavaThreadP7oopDesc + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr jpc, [istate, #ISTATE_BCP] + ldr r3, [r0, #THREAD_PENDING_EXC] + ldr locals, [istate, #ISTATE_LOCALS] + cmp r3, #0 + beq handle_return + b handle_exception + +@ ECN: normal_entry_synchronized doesn't really mean synchronized. It means +@ may or may not be synchronized. So we still have to check the synchronized +@ flag in the synchronized path, otherwise we may get an IllegalMonitor. +normal_entry_synchronized: + stmfd sp!, {regset, lr} + sub sp, sp, #220 + mov sl, r0 + mov tmp1, r2 + ldrh r2, [sl, #40] + ldrh r3, [sl, #42] + rsb tmp_zzz, r3, r2 + cmp tmp_zzz, #0 + ble .normal_entry_synchronized_no_locals + + mov r2, #0 + ldr r1, [tmp1, #THREAD_JAVA_SP] +.zero_locals_synchronized: + subs tmp_zzz, tmp_zzz, #1 + str r2, [r1, #-4]! + bgt .zero_locals_synchronized + str r1, [tmp1, #THREAD_JAVA_SP] + +.normal_entry_synchronized_no_locals: + mov r2, tmp1 + mov r1, sl + add r0, tmp1, #THREAD_JAVA_STACK_BASE + bl build_normal +@ add lr, sp, #192 +@ str r0, [sp, #56] + mov tmp_vvv, r0 + ldr r3, [tmp1, #THREAD_TOP_ZERO_FRAME] + sub r0, r0, #72 +@ str lr, [sp, #32] + mov istate, r0 +@ str r0, [sp, #60] + str r3, [tmp_vvv, #0] + ldr r0, [tmp1, #THREAD_STACK_SIZE] + ldr r3, [tmp1, #THREAD_STACK_BASE] + ldr r2, [tmp1, #THREAD_JAVA_SP] + ldr r1, [tmp1, #THREAD_JAVA_STACK_BASE] + adrl ip, dispatch_init_adcon + rsb r3, r0, r3 + rsb r2, r1, r2 + ldmia ip, {r0, r1} + rsb r3, r3, sp + cmp r2, #4096 + cmpge r3, #32768 + add r0, r0, ip + str tmp_vvv, [tmp1, #THREAD_TOP_ZERO_FRAME] + str tmp_vvv, [tmp1, #THREAD_LAST_JAVA_SP] + add dispatch, r1, r0 + blt .throw_stack_overflow + ldr stack, [istate, #ISTATE_STACK] + ldmib istate, {jpc, locals} @ phole ldm + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [r0, #24] + tst r3, #32 + bne normal_do_synchronization + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH 0 + +do_execute_java_bytecodes_restore_locals_and_jpc: + ldr jpc, [istate, #ISTATE_BCP] +do_execute_java_bytecodes_restore_locals: + ldr locals, [istate, #ISTATE_LOCALS] + ldr constpool, [istate, #ISTATE_CONSTANTS] + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH 0 + +normal_do_synchronization: + tst r3, #8 + ldrne r3, [r0, #12] + ldreq sl, [locals, #0] + ldrne r2, [r3, #16] + ldr r3, [dispatch, #UseBiasedLocking_Address-XXX] + ldr ip, [istate, #ISTATE_MONITOR_BASE] + ldrne sl, [r2, #60] + str ip, [sp, #100] + ldrb r1, [r3] + cmp r1, #0 + beq .normal_do_synchronisation_1 + ldr tmp_xxx, [sl, #0] + and r3, tmp_xxx, #7 + cmp r3, #5 + beq .normal_do_synchronisation_4 +.normal_do_synchronisation_1: + ldr r0, [sp, #100] + ldr r3, [sl, #0] + sub fp, r0, #8 + orr tmp_xxx, r3, #1 + str tmp_xxx, [r0, #-8] +.normal_do_synchronisation_2: + ldr tmp_vvv, [sl, #0] + cmp tmp_xxx, tmp_vvv + bne .normal_do_synchronisation_3 + mov r0, tmp_xxx + mov r1, fp + mov r2, sl + mov r3, #0xffffffc0 + bic r3, r3, #0xf000 + blx r3 + cmp r0, #0 + bne .normal_do_synchronisation_2 +.normal_do_synchronisation_3: + cmp tmp_xxx, tmp_vvv + beq do_execute_java_bytecodes_restore_locals + bic r1, tmp_xxx, #3 + ldr r2, [istate, #ISTATE_THREAD] + mov r0, r2 + ldr r3, [r2, #0] + ldr ip, [r3, #THREAD_VTABLE_IS_LOCK_OWNED] + blx ip + cmp r0, #0 + beq .handle_exception_28 + ldr r0, [sp, #100] + mov r3, #0 + str r3, [r0, #-8] + b do_execute_java_bytecodes_restore_locals +.normal_do_synchronisation_4: + ldr r2, [sl, #4] + ldr r2, [r2, #104] + ldr r0, [istate, #ISTATE_THREAD] + eor r3, r2, r0 + eor r3, r3, tmp_xxx + bics ip, r3, #120 + beq do_execute_java_bytecodes_restore_locals + mov r0, r2 + mov r1, sl + mov r2, tmp_xxx + bl _ZN6Atomic11cmpxchg_ptrEPvPVvS0_ + cmp tmp_xxx, r0 + beq .normal_do_synchronisation_1 + b do_execute_java_bytecodes_restore_locals + +# r2 = [jpc, #1] +# r1 = [jpc, #2] + Opcode invokevirtual + add r0, constpool, r1, lsl #12 + ldr r2, [r0, r2, asl #4]! @ r0 = cache + and r2, r2, #0xff000000 + cmp r2, #182 << 24 + blne resolve_invokevirtual + ldr r3, [r0, #12] + mov r0, #opc_invokeresolved + tst r3, #67108864 + movne r0, #opc_invokevfinal + b rewrite_bytecode + + Opcode invokespecial + add r0, constpool, r1, lsl #12 + ldr r2, [r0, r2, asl #4]! @ r0 = cache + and r2, r2, #0x00ff0000 + cmp r2, #183 << 16 + blne resolve_invokespecial + mov r0, #opc_invokespecialresolved + b rewrite_bytecode + + Opcode invokestatic + add r0, constpool, r1, lsl #12 + ldr r2, [r0, r2, asl #4]! @ r0 = cache + and r2, r2, #0x00ff0000 + cmp r2, #184 << 16 + blne resolve_invokestatic + mov r0, #opc_invokestaticresolved + b rewrite_bytecode + +# r2 = [jpc, #1] +# r1 = [jpc, #2] + Opcode invokevfinal + str stack, [istate, #ISTATE_STACK] + add r0, constpool, r1, lsl #12 + str jpc, [istate, #ISTATE_BCP] + add r0, r2, asl #4 + ldr r3, [r0, #12] + ldr tmp1, [istate, #ISTATE_THREAD] + and r1, r3, #255 + ldr r2, [stack, r1, asl #2] + mov r1, #0 + cmp r2, #0 + beq null_ptr_exception + + ldr tmp2, [r0, #8] + + str tmp2, [istate, #ISTATE_CALLEE] + ldr ip, [tmp2, #76] + str r1, [tmp1, #THREAD_LAST_JAVA_SP] + str ip, [istate, #36] + + add stack, stack, #4 + str stack, [tmp1, #THREAD_JAVA_SP] + + ldr r3, [ip, #0] + adr lr, normal_entry + cmp r3, lr + beq fast_normal_entry + adr lr, native_entry + cmp r3, lr + beq fast_native_entry + adr lr, accessor_entry + cmp r3, lr + beq fast_accessor_entry + b normal_dispatch_and_return + +# r2 = [jpc, #1] +# r1 = [jpc, #2] + Opcode invokeresolved + str stack, [istate, #ISTATE_STACK] + add r0, constpool, r1, lsl #12 + str jpc, [istate, #ISTATE_BCP] + add r0, r0, r2, asl #4 + ldr r3, [r0, #12] + ldr tmp1, [istate, #ISTATE_THREAD] + and r1, r3, #255 + ldr r2, [stack, r1, asl #2] + mov r1, #0 +#ifndef HW_NULL_PTR_CHECK + cmp r2, #0 + beq null_ptr_exception_jpc_0 +#endif + + ldr tmp2, [r0, #8] +.abortentry104: + ldr r3, [r2, #4] + add r3, r3, tmp2, lsl #2 + ldr tmp2, [r3, #304] + + str tmp2, [istate, #ISTATE_CALLEE] + ldr ip, [tmp2, #76] + str r1, [tmp1, #THREAD_LAST_JAVA_SP] + str ip, [istate, #36] + + add stack, stack, #4 + str stack, [tmp1, #THREAD_JAVA_SP] + + ldr r3, [ip, #0] + adr lr, normal_entry + cmp r3, lr + beq fast_normal_entry + adr lr, native_entry + cmp r3, lr + beq fast_native_entry + adr lr, accessor_entry + cmp r3, lr + beq fast_accessor_entry + +normal_dispatch_and_return: + mov r0, tmp2 + mov r1, ip + ldr r2, [istate, #ISTATE_THREAD] + blx r3 + + ldr ip, [istate, #ISTATE_THREAD] + ldr r3, [ip, #THREAD_JAVA_SP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + sub r3, r3, #4 + str r3, [istate, #ISTATE_STACK] + + ldr r1, [ip, #THREAD_TOP_ZERO_FRAME] + add r2, r2, #4 + str r2, [ip, #THREAD_JAVA_SP] + str r1, [ip, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr jpc, [istate, #ISTATE_BCP] + ldr r3, [r0, #4] + DISPATCH_START 3 + ldr locals, [istate, #ISTATE_LOCALS] + ldr constpool, [istate, #ISTATE_CONSTANTS] + DISPATCH_NEXT + DISPATCH_NEXT + add constpool, constpool, #CONST_POOL_OFFSET + cmp r3, #0 + DISPATCH_NEXT + bne invokespecial_exception_fix + DISPATCH_FINISH + + Opcode invokestaticresolved + str stack, [istate, #ISTATE_STACK] + add r0, constpool, r1, lsl #12 + str jpc, [istate, #ISTATE_BCP] + add r0, r2, asl #4 + + ldr tmp2, [r0, #4] + mov r1, #0 + str tmp2, [istate, #ISTATE_CALLEE] + ldr r3, [tmp2, #76] + ldr tmp1, [istate, #ISTATE_THREAD] + str r3, [istate, #36] + str r1, [tmp1, #THREAD_LAST_JAVA_SP] + + add stack, stack, #4 + str stack, [tmp1, #THREAD_JAVA_SP] + + ldr ip, [istate, #36] + ldr r3, [ip, #0] + adr lr, normal_entry + cmp r3, lr + beq fast_normal_entry + adr lr, native_entry + cmp r3, lr + beq fast_native_entry + adr lr, accessor_entry + cmp r3, lr + beq fast_accessor_entry + b normal_dispatch_and_return + + Opcode invokespecialresolved + str stack, [istate, #ISTATE_STACK] + add r0, constpool, r1, lsl #12 + str jpc, [istate, #ISTATE_BCP] + add r0, r2, asl #4 + + ldr r3, [r0, #12] + ldr tmp1, [istate, #ISTATE_THREAD] + and r3, r3, #255 + ldr r2, [stack, r3, asl #2] + mov r1, #0 + cmp r2, #0 + beq null_ptr_exception + + ldr tmp2, [r0, #4] + + str tmp2, [istate, #ISTATE_CALLEE] + ldr ip, [tmp2, #76] + str r1, [tmp1, #THREAD_LAST_JAVA_SP] + str ip, [istate, #36] + + add stack, stack, #4 + str stack, [tmp1, #THREAD_JAVA_SP] + + ldr r3, [ip, #0] + adr lr, normal_entry + cmp r3, lr + beq fast_normal_entry + adr lr, native_entry + cmp r3, lr + beq fast_native_entry + adr lr, accessor_entry + cmp r3, lr + beq fast_accessor_entry + b normal_dispatch_and_return + + ALIGN_CODE +accessor_entry: + adrl ip, dispatch_init_adcon + ldr r3, [ip] + add r3, r3, ip + ldr ip, [ip, #12] + ldr ip, [r3, ip] + ldr r1, [r0, #8] + ldr ip, [ip, #0] + ldrb r3, [r1, #50] + ldrb r1, [r1, #51] + cmp ip, #0 + ldr ip, [r0, #12] + bne normal_entry + ldr ip, [ip, #12] + orr r3, r3, r1, lsl #8 @ r3 = index + + add r1, ip, #16 + ldr r3, [r1, r3, lsl #4]! @ r1 = cache, r3 = flags + ldr ip, [r2, #THREAD_JAVA_SP] @ ip == stack + and r3, r3, #0x00ff0000 + cmp r3, #180 << 16 + ldr r3, [ip, #0] + bne normal_entry + + cmp r3, #0 + beq normal_entry + + ldr r0, [r1, #12] + ldr r1, [r1, #8] + movs r0, r0, lsr #29 + bls accessor_non_w + + ldr r0, [r3, r1] + str r0, [ip, #0] + bx lr + + ALIGN_CODE +normal_entry: + adrl ip, dispatch_init_adcon + stmfd sp!, {regset, lr} + mov tmp2, r0 + ldmia ip, {r0, r1} + sub sp, sp, #220 + + mov istate, #ISTATE_THREAD + add dispatch, ip, r3 + + add r0, r0, ip + add dispatch, r1, r0 + + ldrh r1, [tmp2, #40] + ldrh r3, [tmp2, #42] + mov tmp1, r2 + + rsb tmp_xxx, r3, r1 + ldr stack, [tmp1, #THREAD_JAVA_SP] + movs tmp_xxx, tmp_xxx, asr #1 + mov r0, #0 + mov ip, #0 + strcs r0, [stack, #-4]! +.zero_locals: + subs tmp_xxx, tmp_xxx, #1 + stmgedb stack!, {r0, ip} + bgt .zero_locals + +@ r11 = thread +@ r10 = method + ldrh r2, [r10, #38] + mvn tmp_vvv, #0x540 @ form 0xCAFEBABF + bic tmp_vvv, tmp_vvv, #0x14000 + bic tmp_vvv, tmp_vvv, #0x35000000 + str istate, [stack, #-76 + ISTATE_SAVED_ISTATE] + sub istate, stack, #76 @ istate == istate + mov r7, istate @ monitor_base == istate + sub r5, istate, r2, lsl #2 + str r5, [tmp1, #THREAD_JAVA_SP] @ drop stack now + sub r5, r5, #4 @ stack limit = istate - stackwords - 4 + mov r3, istate + stmdb stack, {r0, r3, r5, r7, istate, tmp_vvv, ip} @ + + str ip, [istate, #ISTATE_CALLEE] + str ip, [istate, #ISTATE_MDX] + str ip, [istate, #ISTATE_PREV_LINK] + + sub locals, stack, #4 + add locals, locals, r1, lsl #2 @ locals == r7 + + ldr jpc, [r10, #8] @ jpc == r5 + ldr constpool, [r10, #12] @ + + sub stack, istate, #ISTATE_BCP @ stack == r4 + str stack, [istate, #ISTATE_STACK] + + add jpc, jpc, #48 + + ldr constpool, [constpool, #12] + + str tmp1, [istate, #ISTATE_THREAD] + stmib istate, {jpc, locals, constpool, r10} + + add constpool, constpool, #CONST_POOL_OFFSET + + str stack, [istate, #ISTATE_STACK] + + add tmp2, istate, #72 + + ldr r3, [tmp1, #THREAD_TOP_ZERO_FRAME] + str r3, [istate, #72] @ Fill in prev_link + ldr r0, [tmp1, #THREAD_STACK_SIZE] + ldr r3, [tmp1, #THREAD_STACK_BASE] + ldr r2, [tmp1, #THREAD_JAVA_SP] + ldr r1, [tmp1, #THREAD_JAVA_STACK_BASE] + rsb r3, r0, r3 + DISPATCH_START 0 + rsb r2, r1, r2 + rsb r3, r3, sp + DISPATCH_NEXT + cmp r2, #4096 + cmpge r3, #32768 + DISPATCH_NEXT + str tmp2, [tmp1, #THREAD_TOP_ZERO_FRAME] + str tmp2, [tmp1, #THREAD_LAST_JAVA_SP] + DISPATCH_NEXT + blt .throw_stack_overflow + DISPATCH_FINISH + + ALIGN_CODE +native_entry: + adrl ip, dispatch_init_adcon + stmfd sp!, {r3, r4, r5, r7, r9, r10, r11, lr} +@--- + ldmia ip, {dispatch, r7} + mov r11, r0 + ldrh r1, [r11, #42] + add dispatch, dispatch, ip + ldr r4, [r2, #THREAD_JAVA_SP] + add dispatch, dispatch, r7 + ldr ip, [r2, #THREAD_TOP_ZERO_FRAME] + mov r0, #0 + mvn r10, #0x540 @ form 0xCAFEBABF in r10 + bic r10, r10, #0x14000 + bic r10, r10, #0x35000000 + sub r9, r4, #76 + mov r7, r9 + str r9, [r2, #THREAD_JAVA_SP] @ drop stack + sub r5, r9, #4 @ stack limit = r9 - 4 + mov r3, r9 + stmdb r4, {r0, r3, r5, r7, r9, r10, ip} + str r0, [r9, #ISTATE_CALLEE] + str r0, [r9, #ISTATE_PREV_LINK] + str r0, [r9, #ISTATE_MSG] + str r0, [r9, #ISTATE_MDX] + sub r7, r4, #4 + add r7, r7, r1, lsl #2 + mov r5, #0 + ldr r10, [r11, #12] + ldr r10, [r10, #12] + stmia r9, {r2, r5, r7, r10, r11} + add r0, r9, #72 + mov r9, r2 +@--- +.LPIC18_native_entry: + ldr r2, [r9, #THREAD_STACK_SIZE] + ldr r3, [r9, #THREAD_STACK_BASE] + rsb r3, r2, r3 + rsb r3, r3, sp + cmp r3, #4096 + str r0, [r9, #THREAD_TOP_ZERO_FRAME] + blt .native_entry_throw_stack_overflow + ldr r5, [r11, #84] + cmp r5, #0 + bne .native_entry_got_handleraddr + str r0, [r9, #THREAD_LAST_JAVA_SP] + mov r0, r9 + mov r1, r11 + bl _ZN18InterpreterRuntime19prepare_native_callEP10JavaThreadP13methodOopDesc + ldr r1, [r9, #THREAD_PENDING_EXC] + str r5, [r9, #THREAD_LAST_JAVA_SP] + cmp r1, #0 + bne .native_entry_exception + ldr r5, [r11, #84] +.native_entry_got_handleraddr: + ldr r2, [dispatch, #InterpreterRuntime_slow_signature_handler_Address-XXX] + cmp r5, r2 + bne .native_entry_get_handler + ldr r3, [r9, #THREAD_TOP_ZERO_FRAME] + mov r2, #0 + mov r0, r9 + str r3, [r9, #THREAD_LAST_JAVA_SP] + mov r3, r2 + mov r1, r11 + bl _ZN18InterpreterRuntime22slow_signature_handlerEP10JavaThreadP13methodOopDescPiS4_ + ldr r1, [r9, #THREAD_PENDING_EXC] + mov r3, #0 + cmp r1, #0 + str r3, [r9, #THREAD_LAST_JAVA_SP] + mov r5, r0 + bne .native_entry_exception +.native_entry_get_handler: + + sub ip, r7, r4 + mov ip, ip, asr #2 + add lr, ip, #4 + bic lr, lr, #1 + + add r3, r4, #ISTATE_OOP_TEMP-76 + + mov r4, sp + sub sp, sp, #16 + sub sp, sp, lr, lsl #2 + mov lr, sp + + add r1, r5, #24 + + add r2, r9, #THREAD_JNI_ENVIRONMENT + str r2, [lr], #4 + add r1, r1, #4 + + ldr r2, [r11, #24] + tst r2, #8 + beq .do_copy_args + + ldr r2, [r11, #12] + ldr r2, [r2, #16] + ldr r2, [r2, #60] + str r2, [r3] + + str r3, [lr], #4 + add r1, r1, #4 + +.do_copy_args: + cmp ip, #0 + blt .no_args + +.copy_args: + ldr r0, [r1], #4 + ldrh r3, [r0, #6] + cmp r3, #FFI_TYPE_DOUBLE + cmpne r3, #FFI_TYPE_SINT64 + beq .copy_long + + cmp r3, #FFI_TYPE_POINTER + beq .copy_ptr + + ldr r2, [r7], #-4 + str r2, [lr], #4 + subs ip, ip, #1 + bge .copy_args + b .no_args + +.copy_long: + tst lr, #4 + addne lr, lr, #4 + ldmda r7!, {r2, r3} + stmia lr!, {r2, r3} + subs ip, ip, #2 + bge .copy_args + b .no_args + +.copy_ptr: + ldr r2, [r7], #-4 + cmp r2, #0 + addne r2, r7, #4 + str r2, [lr], #4 + subs ip, ip, #1 + bge .copy_args + +.no_args: + ldr r0, [r9, #THREAD_TOP_ZERO_FRAME] + str r0, [r9, #THREAD_LAST_JAVA_SP] + + mov r2, #_thread_in_native + str r2, [r9, #THREAD_STATE] + + ldr ip, [r11, #80] + ldrh r11, [r11, #42] + ldmia sp!, {r0, r1, r2, r3} + blx ip + + mov sp, r4 + + mov r3, #_thread_in_native_trans + str r3, [r9, #THREAD_STATE] + +.L206_native_entry: + ldr r3, [dispatch, #SafePointSynchronize_state_Address-XXX] + ldr r3, [r3, #0] + cmp r3, #0 + ldreq r3, [r9, #THREAD_SUSPEND_FLAGS] + cmpeq r3, #0 + bne .native_entry_do_special + +.native_entry_do_return: + mov r3, #_thread_in_Java + mov r2, #0 + str r3, [r9, #THREAD_STATE] + str r2, [r9, #THREAD_LAST_JAVA_SP] + + add r2, r5, #24 + ldr r3, [r5, #4] + + ldr r5, [r9, #THREAD_TOP_ZERO_FRAME] + ldr ip, [r5], #4 + str ip, [r9, #THREAD_TOP_ZERO_FRAME] + + add r5, r5, r11, lsl #2 + + ldr ip, [r2, r3, asl #2] + ldrh r2, [ip, #6] + + cmp r2, #FFI_TYPE_POINTER + beq .native_return_obj + + ldr ip, [r9, #THREAD_ACTIVE_HANDLES] + mov r3, #0 @ ECN: OK, not an obj, save to clear handles + str r3, [ip, #128] + + cmp r2, #FFI_TYPE_VOID + beq .native_return_void + cmp r2, #FFI_TYPE_FLOAT + cmpne r2, #FFI_TYPE_SINT32 + beq .native_return_w + cmp r2, #FFI_TYPE_DOUBLE + cmpne r2, #FFI_TYPE_SINT64 + beq .native_return_dw + + cmp r2, #FFI_TYPE_UINT16 + beq .native_return_char + cmp r2, #FFI_TYPE_SINT16 + beq .native_return_short + cmp r2, #FFI_TYPE_BOOL + beq .native_return_bool + cmp r2, #FFI_TYPE_SINT8 + beq .native_return_byte + + str r0, [r0, -r0] + +.native_return_obj: + cmp r0, #0 + ldrne r0, [r0] + str r0, [r5, #-4]! + str r5, [r9, #THREAD_JAVA_SP] + ldr r2, [r9, #THREAD_ACTIVE_HANDLES] + mov r3, #0 @ ECN: Now that the object is safe on the Java stack + str r3, [r2, #128] @ stack, with the Thread SP updated, clear the active_handles. + ldmfd sp!, {r3, r4, r5, r7, r9, r10, r11, pc} +.native_return_short: + mov r0, r0, lsl #16 + mov r0, r0, asr #16 +.native_return_w: + str r0, [r5, #-4]! +.native_return_void: + str r5, [r9, #THREAD_JAVA_SP] + ldmfd sp!, {r3, r4, r5, r7, r9, r10, r11, pc} +.native_return_dw: + stmdb r5!, {r0, r1} + str r5, [r9, #THREAD_JAVA_SP] + ldmfd sp!, {r3, r4, r5, r7, r9, r10, r11, pc} +.native_return_byte: + mov r0, r0, lsl #24 + mov r0, r0, asr #24 + str r0, [r5, #-4]! + str r5, [r9, #THREAD_JAVA_SP] + ldmfd sp!, {r3, r4, r5, r7, r9, r10, r11, pc} +.native_return_char: + mov r0, r0, lsl #16 + mov r0, r0, lsr #16 + str r0, [r5, #-4]! + str r5, [r9, #THREAD_JAVA_SP] + ldmfd sp!, {r3, r4, r5, r7, r9, r10, r11, pc} +.native_return_bool: + ands r0, r0, #255 + movne r0, #1 + str r0, [r5, #-4]! + str r5, [r9, #THREAD_JAVA_SP] + ldmfd sp!, {r3, r4, r5, r7, r9, r10, r11, pc} + +.native_entry_throw_stack_overflow: + str r0, [r9, #THREAD_LAST_JAVA_SP] + mov r0, r9 + bl _ZN18InterpreterRuntime24throw_StackOverflowErrorEP10JavaThread + mov r3, #0 + ldr r1, [r9, #THREAD_PENDING_EXC] + str r3, [r9, #THREAD_LAST_JAVA_SP] +.native_entry_exception: + ldr r5, [r9, #THREAD_TOP_ZERO_FRAME] + ldr r3, [r5], #4 + str r3, [r9, #THREAD_TOP_ZERO_FRAME] + + ldrh r3, [r11, #42] + add r5, r5, r3, lsl #2 + str r5, [r9, #THREAD_JAVA_SP] + + ldmfd sp!, {r3, r4, r5, r7, r9, r10, r11, pc} +.native_entry_do_special: + stmdb sp!, {r0, r1} + mov r0, r9 + bl _ZN10JavaThread40check_special_condition_for_native_transEPS_ + ldmia sp!, {r0, r1} + b .native_entry_do_return + + ALIGN_CODE +fast_normal_entry: + ldrh r0, [tmp2, #40] + mov r1, #0 + ldrh r3, [tmp2, #42] + mvn ip, #0x540 @ form 0xCAFEBABF in ip + ldrh r2, [tmp2, #38] + bic ip, ip, #0x35000000 + sub r7, r0, r3 + subs r5, r7, #2 + tst r7, #1 + bic ip, ip, #0x14000 + strne r1, [stack, #-4]! + bcc 3f +1: + str r1, [stack, #-4] + str r1, [stack, #-8]! + subs r5, r5, #2 + bcs 1b +3: + ldr lr, [tmp1, #THREAD_TOP_ZERO_FRAME] + str istate, [stack, #-76 + ISTATE_SAVED_ISTATE] + sub istate, stack, #76 @ istate == istate + sub r2, istate, r2, lsl #2 + str r1, [stack, #-76 + ISTATE_MDX] + mov r7, istate @ monitor_base == istate + str r2, [tmp1, #THREAD_JAVA_SP] + sub r5, r2, #4 @ stack limit = istate - stackwords - 4 + mov r3, istate + stmdb stack, {r1, r3, r5, r7, istate, ip, lr} @ + sub locals, stack, #4 + add locals, locals, r0, lsl #2 @ locals == r7 + ldr r3, [tmp1, #THREAD_JAVA_STACK_BASE] + sub stack, istate, #4 @ stack == r4 + ldr jpc, [tmp2, #8] + ldr constpool, [tmp2, #12] @ + str stack, [istate, #ISTATE_STACK] + add ip, istate, #72 + DISPATCH_START 48 + mov lr, #0 @ ECN: FIXME - r1 already 0 + ldr constpool, [constpool, #12] + str ip, [tmp1, #THREAD_TOP_ZERO_FRAME] + rsb r2, r3, r2 + str ip, [tmp1, #THREAD_LAST_JAVA_SP] + DISPATCH_NEXT + str tmp1, [istate, #ISTATE_THREAD] + stmib istate, {jpc, locals, constpool, r10} + DISPATCH_NEXT + cmp r2, #4096 + add constpool, constpool, #CONST_POOL_OFFSET + str lr, [istate, #ISTATE_PREV_LINK] + blt .throw_stack_overflow + DISPATCH_NEXT + str lr, [istate, #ISTATE_CALLEE] + DISPATCH_FINISH + +handle_return: + + ldr tmp2, [istate, #ISTATE_MONITOR_BASE] @ tmp2 = base + + ldr tmp1, [istate, #ISTATE_STACK_BASE] @ tmp1 = end + ldr tmp_xxx, [istate, #ISTATE_THREAD] + + cmp tmp1, tmp2 + blcc return_check_monitors + + mov r3, #0 + ldrb ip, [jpc, #0] + + ldr r2, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + str r3, [tmp_xxx, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_METHOD] + ldr r3, [r2, #0] + ldrh r0, [r0, #40] + add r1, r2, #4 + str r3, [tmp_xxx, #THREAD_TOP_ZERO_FRAME] + + add r1, r1, r0, lsl #2 + + cmp ip, #opc_lreturn + cmpne ip, #opc_dreturn + ldreq r0, [stack, #8] + streq r0, [r1, #-4]! + cmpne ip, #opc_ireturn + cmpne ip, #opc_freturn + cmpne ip, #opc_areturn + ldreq r0, [stack, #4] + streq r0, [r1, #-4]! + + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + + str r1, [tmp_xxx, #THREAD_JAVA_SP] + + cmp istate, #ISTATE_THREAD + + addeq sp, sp, #220 + ldmeqfd sp!, {regset, pc} + +fast_handle_return: + ldr ip, [istate, #ISTATE_THREAD] + ldr r3, [ip, #THREAD_JAVA_SP] + ldr r2, [istate, #ISTATE_STACK_LIMIT] + sub r3, r3, #4 + str r3, [istate, #ISTATE_STACK] + + ldr r1, [ip, #THREAD_TOP_ZERO_FRAME] + add r2, r2, #4 + str r2, [ip, #THREAD_JAVA_SP] + str r1, [ip, #THREAD_LAST_JAVA_SP] + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr jpc, [istate, #ISTATE_BCP] + ldr r3, [r0, #THREAD_PENDING_EXC] + DISPATCH_START 3 + ldr constpool, [istate, #ISTATE_CONSTANTS] + ldr locals, [istate, #ISTATE_LOCALS] + DISPATCH_NEXT + add constpool, constpool, #CONST_POOL_OFFSET + DISPATCH_NEXT + cmp r3, #0 + DISPATCH_NEXT + bne return_exception + DISPATCH_FINISH + +normal_return: + add sp, sp, #220 + str stack, [tmp_xxx, #THREAD_JAVA_SP] + ldmfd sp!, {regset, pc} + +return_check_monitors: + ldr r2, [istate, #ISTATE_METHOD] + ldr r0, [r2, #24] + tst r0, #1<<5 + subne tmp2, tmp2, #8 + cmp tmp1, tmp2 + bcs .return_unlock +1: + ldr r3, [tmp1, #4] + cmp r3, #0 + bne return_throw_illegal_monitor_state + add tmp1, tmp1, #8 + cmp tmp1, tmp2 + bcc 1b + +.return_unlock: + tst r0, #1<<5 + bxeq lr + + ldr tmp1, [tmp2, #4] @ base->obj == NULL + cmp tmp1, #0 + beq return_throw_illegal_monitor_state + + ldr r0, [tmp2, #0] @ r0 = header + mov r3, #0 + cmp r0, #0 + str r3, [tmp2, #4] @ base->obj = NULL + bxeq lr + + mov tmp_vvv, lr + mov r1, tmp1 + mov r2, tmp2 + bl _ZN6Atomic11cmpxchg_ptrEPvPVvS0_ + cmp tmp2, r0 + bxeq tmp_vvv + + str tmp1, [tmp2, #4] + add r0, sp, #144 + mov r1, tmp_xxx + bl _ZN10HandleMark10initializeEP6Thread + mov r1, tmp2 + mov r0, tmp_xxx + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime11monitorexitEP10JavaThreadP15BasicObjectLock + ldr stack, [istate, #ISTATE_STACK] + ldr jpc, [istate, #ISTATE_BCP] + add r0, sp, #144 + bl _ZN10HandleMarkD1Ev + ldr r3, [tmp_xxx, #THREAD_PENDING_EXC] + cmp r3, #0 + bne handle_exception + bx tmp_vvv + +return_throw_illegal_monitor_state: + add r0, sp, #144 + mov r1, tmp_xxx + bl _ZN10HandleMark10initializeEP6Thread + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + mov r0, tmp_xxx + bl _ZN18InterpreterRuntime37throw_illegal_monitor_state_exceptionEP10JavaThread + add r0, sp, #144 + bl _ZN10HandleMarkD1Ev + b handle_exception_with_bcp + +@ ---------------------------------------------------------------------------------------- +.throw_stack_overflow: + ldr r0, [istate, #ISTATE_THREAD] + bl _ZN18InterpreterRuntime24throw_StackOverflowErrorEP10JavaThread + ldr r3, [istate, #ISTATE_THREAD] + ldr ip, [istate, #ISTATE_THREAD] + ldr r2, [r3, #THREAD_TOP_ZERO_FRAME] + mov r3, #0 + add r1, r2, #4 + str r3, [ip, #THREAD_LAST_JAVA_SP] + str r1, [ip, #THREAD_JAVA_SP] + ldr r3, [r2, #0] + str r3, [ip, #THREAD_TOP_ZERO_FRAME] + ldr r2, [istate, #ISTATE_METHOD] + ldrh r3, [r2, #40] + mov r3, r3, asl #2 + add r1, r1, r3 + str r1, [ip, #THREAD_JAVA_SP] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + cmp istate, #ISTATE_THREAD + addeq sp, sp, #220 + ldmeqfd sp!, {regset, pc} + b fast_handle_return + +handle_exception_do_not_unlock: + mov r3, #1 + strb r3, [r2, #THREAD_DO_NOT_UNLOCK] + b handle_exception + +raise_exception: + adr r1, null_str +raise_exception_with_msg: + str r1, [sp] + ldr r3, [dispatch, #VmSymbols_symbols_Address-XXX] + ldr r3, [r3, r0, lsl #2] + ldr tmp1, [istate, #ISTATE_THREAD] + str jpc, [istate, #ISTATE_BCP] + str stack, [istate, #ISTATE_STACK] + mov ip, #_thread_in_vm + str ip, [tmp1, #THREAD_STATE] + mov r2, #99 + ldr r0, [istate, #ISTATE_THREAD] + adrl r1, bytecode_interpreter_str + bl _ZN10Exceptions10_throw_msgEP6ThreadPKciP13symbolOopDescS3_ + mov r0, sp + str tmp1, [sp] + bl _ZN18ThreadInVMfromJavaD1Ev + b handle_exception_with_bcp +null_str: + .byte 0 + ALIGN_WORD + +invokespecial_exception_fix: +invokestatic_exception_fix: +invokevirtual_exception_fix: +return_exception: + sub jpc, jpc, #3 +invokespecial_exception: +invokestatic_exception: +invokevirtual_exception: +putfield_exception: +getfield_exception: +handle_exception: + str jpc, [istate, #ISTATE_BCP] +handle_exception_with_bcp: + ldr stack, [istate, #ISTATE_STACK_BASE] + sub stack, stack, #4 + str stack, [istate, #ISTATE_STACK] + add r1, sp, #168 + str r1, [sp, #36] + ldr r0, [istate, #ISTATE_THREAD] +handle_exception_1: + ldr sl, [r0, #4] + str r0, [sp, #124] + cmp sl, #0 + moveq tmp_yyy, sl + beq .handle_exception_3 + ldr r0, [r0, #THREAD_HANDLE_AREA] + ldr r1, [r0, #8] + ldr r3, [r0, #12] + add r2, r1, #4 + cmp r2, r3 + movls r3, r1 + strls r2, [r0, #8] + bls .handle_exception_2 + mov r1, #4 + bl _ZN5Arena4growEj + mov r3, r0 +.handle_exception_2: + str sl, [r3, #0] + mov tmp_yyy, r3 + ldr r0, [istate, #ISTATE_THREAD] +.handle_exception_3: + mov r1, r0 + ldr r0, [sp, #36] + bl _ZN10HandleMark10initializeEP6Thread + ldr r0, [istate, #ISTATE_THREAD] + bl _ZN12ThreadShadow23clear_pending_exceptionEv + ldr r1, [istate, #ISTATE_STACK_BASE] + ldr r0, [istate, #ISTATE_THREAD] + cmp tmp_yyy, #0 + sub stack, r1, #4 + moveq r1, tmp_yyy + str stack, [istate, #ISTATE_STACK] + ldrne r1, [tmp_yyy, #0] + bl _ZN18InterpreterRuntime31exception_handler_for_exceptionEP10JavaThreadP7oopDesc + ldr stack, [istate, #ISTATE_STACK] + mov sl, r0 + ldr r0, [istate, #ISTATE_THREAD] + ldr r3, [r0, #THREAD_PENDING_EXC] + cmp r3, #0 + beq .handle_exception_5 + ldr r0, [sp, #36] + bl _ZN10HandleMarkD1Ev + ldr r1, [sp, #124] + ldr tmp_yyy, [r1, #THREAD_LAST_HANDLE_MARK] + ldr r0, [tmp_yyy, #8] + ldr sl, [tmp_yyy, #4] + ldr r3, [r0, #0] + cmp r3, #0 + beq .handle_exception_4 + bl _ZN5Chunk9next_chopEv + ldr r0, [tmp_yyy, #8] +.handle_exception_4: + str r0, [sl, #4] + ldr r3, [tmp_yyy, #12] + str r3, [sl, #8] + ldr r2, [tmp_yyy, #16] + str r2, [sl, #12] + ldr r0, [istate, #ISTATE_THREAD] + b handle_exception_1 +.handle_exception_5: + ldr tmp_yyy, [r0, #THREAD_VM_RESULT] + cmp tmp_yyy, #0 + moveq r1, tmp_yyy + beq .handle_exception_7 + ldr r3, [dispatch, #ThreadLocalStorage_thread_index-XXX] + ldr r0, [r3] + bl pthread_getspecific + ldr r0, [r0, #THREAD_HANDLE_AREA] + ldr r1, [r0, #8] + ldr r3, [r0, #12] + add r2, r1, #4 + cmp r2, r3 + movls r3, r1 + strls r2, [r0, #8] + bls .handle_exception_6 + mov r1, #4 + bl _ZN5Arena4growEj + mov r3, r0 +.handle_exception_6: + str tmp_yyy, [r3, #0] + mov r1, r3 + ldr r0, [istate, #ISTATE_THREAD] +.handle_exception_7: + cmp sl, #0 + mov r3, #0 + str r3, [r0, #THREAD_VM_RESULT] + blt .handle_exception_9 + cmp r1, r3 + moveq r0, r1 + ldrne r0, [r1, #0] + str r0, [stack, #0] + sub stack, stack, #4 + ldr r3, [istate, #ISTATE_METHOD] + ldr r0, [sp, #36] + ldr r2, [r3, #8] + add r2, r2, #48 + add ip, r2, sl + str ip, [istate, #ISTATE_BCP] + bl _ZN10HandleMarkD1Ev + ldr r1, [sp, #124] + ldr tmp_yyy, [r1, #THREAD_LAST_HANDLE_MARK] + ldr r0, [tmp_yyy, #8] + ldr sl, [tmp_yyy, #4] + ldr r3, [r0, #0] + cmp r3, #0 + beq .handle_exception_8 + bl _ZN5Chunk9next_chopEv + ldr r0, [tmp_yyy, #8] +.handle_exception_8: + str r0, [sl, #4] + ldr r3, [tmp_yyy, #12] + str r3, [sl, #8] + ldr r2, [tmp_yyy, #16] + str r2, [sl, #12] + b do_execute_java_bytecodes_restore_locals_and_jpc +.handle_exception_9: + cmp r1, #0 + ldr r0, [istate, #ISTATE_THREAD] + mov r2, #0 + ldrne r1, [r1, #0] + mov r3, r2 + bl _ZN12ThreadShadow21set_pending_exceptionEP7oopDescPKci + ldr r0, [istate, #ISTATE_THREAD] + ldr tmp_yyy, [r0, #4] + cmp tmp_yyy, #0 + streq tmp_yyy, [sp, #48] + beq .handle_exception_11 + ldr r0, [r0, #THREAD_HANDLE_AREA] + ldr r1, [r0, #8] + ldr r3, [r0, #12] + add r2, r1, #4 + cmp r2, r3 + movls r3, r1 + strls r2, [r0, #8] + bls .handle_exception_10 + mov r1, #4 + bl _ZN5Arena4growEj + mov r3, r0 +.handle_exception_10: + str tmp_yyy, [r3, #0] + ldr r0, [istate, #ISTATE_THREAD] + str r3, [sp, #48] +.handle_exception_11: + bl _ZN12ThreadShadow23clear_pending_exceptionEv + mov r1, #0 + ldr r0, [istate, #ISTATE_THREAD] + str r1, [sp, #44] + ldrb r3, [r0, #THREAD_DO_NOT_UNLOCK] @ zero_extendqisi2 + cmp r3, r1 + beq .handle_exception_15 + strb r1, [r0, #THREAD_DO_NOT_UNLOCK] + ldr r0, [istate, #ISTATE_THREAD] +.handle_exception_12: + ldr r1, [sp, #48] + cmp r1, #0 + movne r2, r1 + ldrne r1, [r2, #0] +.handle_exception_13: + mov r2, #0 + mov r3, r2 + bl _ZN12ThreadShadow21set_pending_exceptionEP7oopDescPKci + mov r3, #0 + ldr r2, [istate, #ISTATE_BCP] + ldrb r2, [r2, #0] @ zero_extendqisi2 + str stack, [istate, #ISTATE_STACK] + str r2, [istate, #ISTATE_CALLEE] + ldr lr, [istate, #ISTATE_THREAD] + ldr r1, [lr, #THREAD_TOP_ZERO_FRAME] + str r3, [lr, #THREAD_LAST_JAVA_SP] + add r2, r1, #4 + str r2, [lr, #THREAD_JAVA_SP] + ldr r3, [r1, #0] + str r3, [lr, #THREAD_TOP_ZERO_FRAME] + ldr r1, [istate, #ISTATE_METHOD] + ldrh r3, [r1, #40] + ldr r0, [sp, #36] + mov r3, r3, asl #2 + add r2, r2, r3 + str r2, [lr, #THREAD_JAVA_SP] + bl _ZN10HandleMarkD1Ev + ldr r0, [sp, #124] + ldr tmp_yyy, [r0, #THREAD_LAST_HANDLE_MARK] + ldr r0, [tmp_yyy, #8] + ldr sl, [tmp_yyy, #4] + ldr r3, [r0, #0] + cmp r3, #0 + beq .handle_exception_14 + bl _ZN5Chunk9next_chopEv + ldr r0, [tmp_yyy, #8] +.handle_exception_14: + str r0, [sl, #4] + ldr r3, [tmp_yyy, #12] + str r3, [sl, #8] + ldr r2, [tmp_yyy, #16] + str r2, [sl, #12] + ldr istate, [istate, #ISTATE_SAVED_ISTATE] + cmp istate, #ISTATE_THREAD + bne fast_handle_return + add sp, sp, #220 + ldmfd sp!, {regset, pc} +.handle_exception_15: + ldr ip, [istate, #ISTATE_MONITOR_BASE] + ldr r2, [istate, #ISTATE_METHOD] + str ip, [sp, #92] + ldr tmp_vvv, [istate, #ISTATE_STACK_BASE] + ldr r3, [r2, #24] + mov r3, r3, lsr #5 + ands r3, r3, #1 + subne ip, ip, #8 + strne ip, [sp, #92] + ldr lr, [sp, #92] + str r3, [sp, #96] + cmp tmp_vvv, lr + bcs .handle_exception_21 + add r0, sp, #144 + add r1, sp, #212 + str r0, [sp, #28] + str r1, [sp, #24] + .p2align 3 +.handle_exception_16: + ldr tmp_yyy, [tmp_vvv, #4] + cmp tmp_yyy, #0 + beq .handle_exception_20 + ldr fp, [tmp_vvv, #0] + mov r2, #0 + cmp fp, r2 + str r2, [tmp_vvv, #4] + beq .handle_exception_19 + .p2align 3 +.handle_exception_17: + ldr sl, [tmp_yyy, #0] + cmp tmp_vvv, sl + bne .handle_exception_18 + mov r0, tmp_vvv + mov r1, fp + mov r2, tmp_yyy + mov r3, #0xffffffc0 + bic r3, r3, #0xf000 + blx r3 + cmp r0, #0 + bne .handle_exception_17 +.handle_exception_18: + cmp tmp_vvv, sl + beq .handle_exception_19 + str tmp_yyy, [tmp_vvv, #4] + ldr r0, [sp, #28] + ldr r1, [istate, #ISTATE_THREAD] + bl _ZN10HandleMark10initializeEP6Thread + mov r1, tmp_vvv + ldr r0, [istate, #ISTATE_THREAD] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime11monitorexitEP10JavaThreadP15BasicObjectLock + ldr stack, [istate, #ISTATE_STACK] + ldr r0, [sp, #28] + bl _ZN10HandleMarkD1Ev +.handle_exception_19: + ldr r1, [sp, #44] + cmp r1, #0 + beq .handle_exception_27 + ldr r3, [r1, #0] + cmp r3, #0 + beq .handle_exception_27 +.handle_exception_20: + ldr r3, [sp, #92] + add tmp_vvv, tmp_vvv, #8 + cmp tmp_vvv, r3 + bcc .handle_exception_16 +.handle_exception_21: + ldr ip, [sp, #96] + cmp ip, #0 + beq .handle_exception_23 + ldr r0, [sp, #92] + ldr sl, [r0, #4] + cmp sl, #0 + beq .handle_exception_26 + mov ip, r0 + ldr r0, [r0, #0] + mov r3, #0 + cmp r0, #0 + str r3, [ip, #4] + beq .handle_exception_23 + mov r1, sl + ldr r2, [sp, #92] + bl _ZN6Atomic11cmpxchg_ptrEPvPVvS0_ + ldr r1, [sp, #92] + cmp r1, r0 + beq .handle_exception_22 + ldr r3, [sp, #92] + add tmp_yyy, sp, #144 + mov r0, tmp_yyy + str sl, [r3, #4] + ldr r1, [istate, #ISTATE_THREAD] + bl _ZN10HandleMark10initializeEP6Thread + ldr r1, [sp, #92] + ldr r0, [istate, #ISTATE_THREAD] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime11monitorexitEP10JavaThreadP15BasicObjectLock + mov r0, tmp_yyy + ldr stack, [istate, #ISTATE_STACK] + bl _ZN10HandleMarkD1Ev + ldr r0, [istate, #ISTATE_THREAD] + ldr r1, [r0, #4] + cmp r1, #0 + beq .handle_exception_24 + add r0, sp, #204 + bl _ZN6HandleC1EP7oopDesc + ldr r1, [sp, #204] + ldr r0, [istate, #ISTATE_THREAD] + str r1, [sp, #44] + bl _ZN12ThreadShadow23clear_pending_exceptionEv +.handle_exception_22: + ldr r0, [istate, #ISTATE_THREAD] + b .handle_exception_24 +.handle_exception_23: + ldr r0, [istate, #ISTATE_THREAD] +.handle_exception_24: + ldr r3, [sp, #44] + cmp r3, #0 + beq .handle_exception_12 +.handle_exception_25: + ldr lr, [sp, #44] + ldr r1, [lr, #0] + cmp r1, #0 + bne .handle_exception_13 + b .handle_exception_12 +.handle_exception_26: + ldr r1, [sp, #44] + cmp r1, #0 + beq .handle_exception_29 + ldr r3, [r1, #0] + cmp r3, #0 + beq .handle_exception_29 + ldr r0, [istate, #ISTATE_THREAD] + b .handle_exception_25 + +.handle_exception_27: + ldr r0, [sp, #28] + ldr r1, [istate, #ISTATE_THREAD] + bl _ZN10HandleMark10initializeEP6Thread + ldr r0, [istate, #ISTATE_THREAD] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime37throw_illegal_monitor_state_exceptionEP10JavaThread + ldr r0, [sp, #28] + ldr stack, [istate, #ISTATE_STACK] + bl _ZN10HandleMarkD1Ev + ldr r0, [sp, #24] + ldr r3, [istate, #ISTATE_THREAD] + ldr r1, [r3, #4] + bl _ZN6HandleC1EP7oopDesc + ldr r2, [sp, #212] + ldr r0, [istate, #ISTATE_THREAD] + str r2, [sp, #44] + bl _ZN12ThreadShadow23clear_pending_exceptionEv + b .handle_exception_20 +.handle_exception_28: + mov r1, fp + str stack, [istate, #ISTATE_STACK] + ldr r0, [istate, #ISTATE_THREAD] + bl _ZN18InterpreterRuntime12monitorenterEP10JavaThreadP15BasicObjectLock + ldr r0, [istate, #ISTATE_THREAD] + ldr stack, [istate, #ISTATE_STACK] + ldr r3, [r0, #THREAD_PENDING_EXC] + cmp r3, #0 + mov r2, r0 + beq do_execute_java_bytecodes_restore_locals_and_jpc + b handle_exception_do_not_unlock +.handle_exception_29: + add tmp_yyy, sp, #144 + mov r0, tmp_yyy + ldr r1, [istate, #ISTATE_THREAD] + bl _ZN10HandleMark10initializeEP6Thread + ldr r0, [istate, #ISTATE_THREAD] + str stack, [istate, #ISTATE_STACK] + bl _ZN18InterpreterRuntime37throw_illegal_monitor_state_exceptionEP10JavaThread + mov r0, tmp_yyy + ldr stack, [istate, #ISTATE_STACK] + bl _ZN10HandleMarkD1Ev + ldr r3, [istate, #ISTATE_THREAD] + add r0, sp, #208 + ldr r1, [r3, #4] + bl _ZN6HandleC1EP7oopDesc + ldr r2, [sp, #208] + ldr r0, [istate, #ISTATE_THREAD] + str r2, [sp, #44] + bl _ZN12ThreadShadow23clear_pending_exceptionEv + ldr r0, [istate, #ISTATE_THREAD] + b .handle_exception_24 +opclabels_data_adcon: + .word opclabels_data(GOTOFF) + + ALIGN_CODE +fast_accessor_entry: + ldr ip, [dispatch, #SafePointSynchronize_state_Address-XXX] + ldr r3, [tmp2, #8] + ldr ip, [ip, #0] + ldrb lr, [r3, #50] + ldrb r3, [r3, #51] + cmp ip, #0 + ldr ip, [tmp2, #12] + bne fast_normal_entry + ldr ip, [ip, #12] + + DISPATCH_START 3 + + orr lr, lr, r3, lsl #8 @ lr = index + add r3, ip, #16 + ldr lr, [r3, lr, lsl #4]! @ r3 = cache, lr = flags + + DISPATCH_NEXT + + cmp lr, #180 << 16 + GET_STACK 0, lr + bne fast_normal_entry + + cmp lr, #0 + beq fast_normal_entry + + + ldr r2, [r3, #12] + ldr r3, [r3, #8] + movs r2, r2, lsr #29 + bls .fast_accessor_non_w + + DISPATCH_NEXT + + ldr tmp1, [lr, r3] + + DISPATCH_NEXT + DISPATCH_NEXT + + PUT_STACK 0, tmp1 + + DISPATCH_FINISH + +.fast_accessor_non_w: + bcs .fast_accessor_h + beq .fast_accessor_sb + tst r2, #2 + bne .fast_accessor_dw +.fast_accessor_sh: + DISPATCH_STATE 2 + DISPATCH_NEXT + ldrsh tmp1, [lr, r3] + DISPATCH_NEXT + DISPATCH_NEXT + PUT_STACK 0, tmp1 + DISPATCH_FINISH +.fast_accessor_h: + DISPATCH_STATE 2 + DISPATCH_NEXT + ldrh tmp1, [lr, r3] + DISPATCH_NEXT + DISPATCH_NEXT + PUT_STACK 0, tmp1 + DISPATCH_FINISH +.fast_accessor_sb: + DISPATCH_STATE 2 + DISPATCH_NEXT + ldrsb tmp1, [lr, r3] + DISPATCH_NEXT + DISPATCH_NEXT + PUT_STACK 0, tmp1 + DISPATCH_FINISH +.fast_accessor_dw: + DISPATCH_STATE 2 + add tmp1, lr, r3 + DISPATCH_NEXT + ldm tmp1, {tmp2, tmp1} + DISPATCH_NEXT + PUT_STACK 0, tmp1 + DISPATCH_NEXT + PUSH tmp2 + DISPATCH_FINISH + +.iconst_div_rem_0: + sub jpc, jpc, #1 @ Point to idiv +.lrem_0: +.ldiv_0: +.remc_0: +.divc_0: +divide_by_zero_exception: + mov r0, #VMSYMBOLS_ArithmeticException + adr r1, div_zero_msg + b raise_exception_with_msg +div_zero_msg: + .ascii "/ by int zero\000" + ALIGN_WORD + +array_bound_exception_jpc_4_r3: + sub jpc, jpc, #1 +array_bound_exception_jpc_3_r3: + sub jpc, jpc, #1 +array_bound_exception_jpc_2_r3: + sub jpc, jpc, #1 +array_bound_exception_jpc_1_r3: + sub jpc, jpc, #1 +array_bound_exception_jpc_0_r3: + mov r2, r3 + b array_bounds_exception +array_bound_exception_jpc_1_tmp2: + sub jpc, jpc, #1 +array_bound_exception_jpc_0_tmp2: + mov r2, tmp2 + b array_bounds_exception +array_bound_exception_jpc_3: + sub jpc, jpc, #1 +array_bound_exception_jpc_2: + sub jpc, jpc, #1 +array_bound_exception_jpc_1: + sub jpc, jpc, #1 +array_bound_exception_jpc_0: +array_bounds_exception: + adr r1, percent_d_str + add r0, sp, #168 + bl sprintf + add r1, sp, #168 + mov r0, #VMSYMBOLS_ArrayIndexOutOfBounds + b raise_exception_with_msg +percent_d_str: + .ascii "%d\000" + ALIGN_WORD + +#ifndef HW_NULL_PTR_CHECK +null_ptr_exception_jpc_5: + sub jpc, jpc, #1 +null_ptr_exception_jpc_4: + sub jpc, jpc, #1 +null_ptr_exception_jpc_3: + sub jpc, jpc, #1 +null_ptr_exception_jpc_2: + sub jpc, jpc, #1 +null_ptr_exception_jpc_1: + sub jpc, jpc, #1 +null_ptr_exception_jpc_0: +#endif +null_ptr_exception: + mov r0, #VMSYMBOLS_NullPointerException + b raise_exception + +@ ==== Fast SW FP emulation =============================================================== + +#define al r0 +#define ah r1 +#define bl r2 +#define bh r3 +#define tmp tmp1 +#define sh r12 +#define ex_add r14 + +@ TOS = TOSM1 + TOS +@ What we actually do is TOS = TOS + TOSM1 +@ --- do_dadd_vtos ------------------------------------------------- + Opcode dadd + POP4 al, ah, bl, bh + mov tmp, #0xff000000 + orr tmp, tmp, #0x00e00000 + bics ex_add, tmp, ah, LSL #1 + bicnes ex_add, tmp, bh, LSL #1 + beq .dadd_naninf + teq ah, bh + eormi bh, bh, #1 << 31 + bmi ._dsub1 +._dadd1: + subs ex_add, al, bl + sbcs sh, ah, bh + bhs .dadd_swapped + adds bl, bl, ex_add + adc bh, bh, sh + subs al, al, ex_add + sbc ah, ah, sh +.dadd_swapped: + mov ex_add, ah, LSR #20 + sub sh, ex_add, bh, LSR #20 + tst tmp, bh, LSL #1 + beq .dadd_uncommon + bic ah, ah, ex_add, LSL #20 + bic bh, bh, tmp + orr bh, bh, #1 << 20 +.dadd_doadd: + rsbs tmp, sh, #32 + blo .dadd_bigshift +.dadd_smallshift: + adds al, al, bl, LSR sh + adc ah, ah, bh, LSR sh + adds al, al, bh, LSL tmp + adcs ah, ah, #0 + cmp ah, #1 << 20 + bhs .dadd_carry + add ah, ah, ex_add, LSL #20 @ add exponent +.dadd_nocarry: + movs bl, bl, LSL tmp @ round and sticky bits + bpl .dadd_exit + adds al, al, #1 + movccs bl, bl, LSL #1 @ is sticky bit zero? + bne .dadd_exit +.dadd_roundeven: + cmp al, #0 + bicne al, al, #1 @ RTE if carry didn't occur + adceq ah, ah, #0 @ increment high word if it did +.dadd_check_overflow_inx: + mov bh, ah, LSL #1 + cmp bh, #0xFFE00000 + blo .dadd_exit + subhs ah, ah, #3<<29 @ bias exponent + b .return_double_Inf +.dadd_bigshift: + cmp bl, #1 + adc bl, bh, bh + sub sh, sh, #32 @ nonzero + rsbs tmp, sh, #31 @ sets C if within a word + movlo tmp, #0 @ C clear if sh > 31 + addhss al, al, bh, LSR sh + adc ah, ah, ex_add, LSL #20 + cmp ex_add, ah, LSR #20 + beq .dadd_nocarry + sub ah, ah, ex_add, LSL #20 +.dadd_carry: + add ah, ah, #1 << 20 + movs ah, ah, LSR #1 + add ah, ah, ex_add, LSL #20 + movs al, al, RRX + bcc .dadd_check_overflow_exact + adcs al, al, #0 + movccs tmp, bl, LSL tmp @EQ = round to even + bne .dadd_check_overflow_exact + b .dadd_roundeven +.dadd_rnearup_carry: + adds al, al, #1 + movccs bl, bl, LSL #1 @ is sticky bit zero? + bne .dadd_check_overflow_inx + b .dadd_roundeven +.dadd_check_overflow_exact: + mov bh, ah, LSL #1 + cmp bh, #0xFFE00000 + blo .dadd_exit + sub ah, ah, #3<<29 @ bias exponent + +.return_double_Inf: + and a3, ah, #0x80000000 +.return_double_Inf_1: + mov al, #0 + mov ah, #0x7f000000 + orr ah, ah, #0x00f00000 + orr ah,ah,a3 +.dadd_exit: + PUSH2 al, ah + DISPATCH 1 + +.dadd_uncommon: + orrs tmp, bl, bh, LSL #1 @ Is b zero or denormal? + beq .dadd_bzero + movs tmp, ex_add, LSL #21 + bic ah, ah, ex_add, LSL #20 + bicne bh, bh, #1 << 31 + subne sh, sh, #1 @ adjust exponent to fake exp_b = 1 + bne .dadd_doadd + adds al, al, bl + adc ah, ah, bh + b .daddsub_denorm +.dadd_bzero: + movs tmp, ex_add, LSL #21 @ is a denormal? + bne .dadd_exit + orrs tmp, al, ah, LSL #1 @ a zero? + beq .dadd_exit + b .daddsub_denorm + +.dadd_naninf: + cmp al, #1 @ sets C if al!=0 + adc ex_add, ah, ah + cmp bl, #1 + adc sh, bh, bh + cmp ex_add, tmp @ HI if a is NaN + cmpls sh, tmp @ HI if either is NaN + bhi .return_double_NaN + cmp ex_add, sh + beq .dadd_twoinf + cmp ex_add, tmp @ EQ if a is Inf + movne ah, bh + movne al, bl + b .dadd_exit +.dadd_twoinf: + teq ah, bh + bpl .dadd_exit + b .return_double_NaN + +@ ECN: load 1st arg off stack and do a reverse subtract +@ ECN: We want TOSM1 - TOS, but args end up in wrong order so do rsb +@ --- do_dsub_itos ------------------------------------------------- + Opcode dsub + POP4 al, ah, bl, bh + mov tmp, #0xff000000 + orr tmp, tmp, #0x00e00000 + bics ex_add, tmp, ah, LSL #1 + bicnes ex_add, tmp, bh, LSL #1 + beq .drsb_naninf + teq ah, bh + eor ah, ah, #1 << 31 + bmi ._dadd1 + eor bh, bh, #1 << 31 +._dsub1: + subs ex_add, al, bl + sbcs sh, ah, bh + bhs .dsub_swapped +.dsub_do_swap: + eor sh, sh, #1 << 31 @ negate a and b as a - b == -b - -a + adds bl, bl, ex_add + adc bh, bh, sh + subs al, al, ex_add + sbc ah, ah, sh +.dsub_swapped: + mov ex_add, ah, LSR #20 + sub sh, ex_add, bh, LSR #20 + tst tmp, bh, LSL #1 + beq .dsub_uncommon + bic ah, ah, ex_add, LSL #20 + bic bh, bh, tmp, ASR #1 + rsbs bl, bl, #0 + rsc bh, bh, tmp, ASR #1 @ 0xffe00000 >> 1 = -(1 << 20) +.dsub_dosub: + rsbs tmp, sh, #32 + blo .dsub_bigshift +.dsub_smallshift: + adds al, al, bl, LSR sh + adc ah, ah, bh, ASR sh + adds al, al, bh, LSL tmp + adcs ah, ah, #0 + bmi .dsub_borrow +.dsub_noborrow: + add ah, ah, ex_add, LSL #20 + movs bl, bl, LSL tmp +.dsub_dorounding: + bpl .dsub_exit + adds al, al, #1 @ Z flag set if carry to high word + cmpne bl, #0x80000000 @ check we don't have to round to even + bne .dsub_exit + cmp al, #0 + addeq ah, ah, #1 + bicne al, al, #1 + b .dsub_exit +.dsub_bigshift: + cmp bl, #1 + adc bl, bh, bh + sub sh, sh, #32 + rsbs tmp, sh, #31 + blo .dsub_hugeshift + adds al, al, bh, ASR sh + adcs ah, ah, #-1 + bpl .dsub_noborrow +.dsub_borrow: + add tmp, tmp, #1 + movs tmp, bl, LSL tmp + adcs al, al, al @ shift al,ah left including guard bit + adc ah, ah, ah + add sh, ah, ex_add, LSL #21 @ ah = 0xFFE00000 + fraction. Adding + movs sh, sh, LSR #21 @ C-bit is clear if bit 20 of ah + bls .dsub_renormalize @ clear, so 2 bits or more + add ah, ah, ex_add, LSL #20 + adds al, al, tmp, LSR #31 @ C and Z flag are set if carry over + cmpcc tmp, #0x80000000 @ check that we don't have to round + bne .dsub_exit + cmp al, #0 + addeq ah, ah, #1 + bicne al, al, #1 + b .dsub_exit +.dsub_renormalize: + bcs .dsub_ex_one + adds ah, ah, #1 << 21 + cmpeq al, #0 + beq .dsub_retzero @ go and deal with it, if so + mov sh, ex_add, LSR #11 + bic ex_add, ex_add, #1 << 11 + sub ex_add, ex_add, #2 @ for leading bit +.dsub_renormloop: @ TODO: add loop for 8 bit per cycle renorm + adds al, al, al + adc ah, ah, ah + sub ex_add, ex_add, #1 + tst ah, #1 << 20 + beq .dsub_renormloop + add ah, ah, sh, LSL #31 + add ah, ah, ex_add, LSL #20 + cmp ex_add, #0 + bgt .dsub_exit + add ah, ah, #3 << 29 @ bias exponent + @ Rounding direction indicator is zero (denormal results are exact) + mov ip, #0 + b .__dunder +.dsub_hugeshift: +.dsub_return: + add ah, ah, ex_add, LSL #20 +.dsub_return1: +.dsub_exit: + PUSH2 al, ah + DISPATCH 1 +.dsub_ex_one: @ underflow when ex = 1 - shift back to denorm + movs ah, ah, ASR #1 + mov al, al, RRX + add ah, ah, ex_add, LSL #20 + b .dsub_denorm +.dsub_uncommon: + orrs tmp, bl, bh, LSL #12 @ is b zero or denorm? + beq .dsub_bzero + movs tmp, ex_add, LSL #21 + bic ah, ah, ex_add, LSL #20 + beq .dsub_both_denorm + bic bh, bh, #1 << 31 + sub sh, sh, #1 + rsbs bl, bl,#0 + rsc bh, bh,#0 + b .dsub_dosub +.dsub_both_denorm: + subs al, al, bl + sbc ah, ah, bh + b .dsub_denorm +.dsub_bzero: + orrs tmp, al, ah, LSL #1 + bne .dsub_denorm @ return a@ but it might be denormal +.dsub_retzero: + mov ah, #0 @ clear sign bit (al is already 0) + b .dsub_exit +.dsub_denorm: +.daddsub_denorm: + movs bl, ah, LSL #1 @ discard sign bit + tsteq al, al @ do we have a zero? + beq .dsub_retzero @ yes@ go and ensure the right sign + b .dsub_exit +.drsb_naninf: + @ Handle NaNs and infinities in reverse subtraction. We + @ just swap the operands and go to dsub_naninf. + eor ah, ah, bh + eor al, al, bl + eor bh, bh, ah + eor bl, bl, al + eor ah, ah, bh + eor al, al, bl +.dsub_naninf: + cmp al, #1 @ sets C if al!=0 + adc ex_add, ah, ah + cmp bl, #1 + adc sh, bh, bh + cmp ex_add, tmp @ HI if a is NaN + cmpls sh, tmp @ HI if either is NaN + bhi .return_double_NaN + cmp ex_add, sh + beq .dsub_twoinf + cmp ex_add, tmp @ EQ if a is Inf + eorne ah, bh, #0x80000000 + movne al, bl + b .dsub_exit +.dsub_twoinf: + teq ah, bh + bmi .dsub_exit + +.return_double_NaN: + and a3, ah, #0x80000000 + mov al, #0 + mov ah, #0x7f000000 + orr ah, ah, #0x00f80000 + orr ah,ah,a3 + b .dsub_exit + +@ === underflow handler ================================================ + +#define INX_pos 30 +#define INX_bit (1<<30) + +#define exp r2 +#define temp r3 + +.__dunder: + tst ah, ah + orrmi ip, ip, #1<<16 + mov temp, #0x600 + mov exp, ah, LSR #20 @ find the exponent + add temp, temp, #1 + bic ah, ah, exp, LSL #20 @ remove exponent from mantissa + bic exp, exp, #0x800 @ lose the sign bit + sub exp, temp, exp + orr ah, ah, #1<<20 @ put on mantissa leading bit + cmp exp, #53 + bhi .dunder_stickyonly + beq .dunder_roundbit + cmp exp, #21 + blo .dunder_hiword + subs exp, exp, #32 + bls .dunder_hiloword +.dunder_loloword: + rsb temp, exp, #32 + cmp al, #0 + mov al, ah, LSR exp + mov exp, ah, LSL temp + orrne exp, exp, #1 + mov ah, #0 + b .dunder_round +.dunder_hiloword: + rsb temp, exp, #0 + add exp, exp, #32 + mov ah, ah, LSL temp + orr ah, ah, al, LSR exp + mov exp, al, LSL temp + mov al, ah + mov ah, #0 + b .dunder_round +.dunder_hiword: + rsb temp, exp, #32 + mov tmp, al, LSL temp + mov temp, ah, LSL temp + orr al, temp, al, LSR exp + mov ah, ah, LSR exp + mov exp, tmp + b .dunder_round +.dunder_roundbit: + orrs exp, al, ah, LSL #12 + mov al, #0 + mov ah, #0 + mov exp, #0x80000000 + addne exp, exp, #1 + b .dunder_round +.dunder_stickyonly: + mov exp, #1 + mov ah, #0 + mov al, #0 +.dunder_round: + tst ip, #1<<16 + bic ip, ip, #1<<16 + orrne ah, ah, #0x80000000 + tst exp, exp + beq .dsub_exit + movs exp, exp, LSL #1 @ round bit in C, sticky in ~Z + bcc .dunder_rerounded @ if no round bit, we're done + beq .dunder_roundeven @ RTE is tricky due to rerounding +.dunder_roundup: + adds al, al, #1 @ round up + adc ah, ah, #0 +.dunder_rerounded: + b .dsub_exit +.dunder_roundeven: + movs exp, ip, ASR #INX_pos @ get -1, 0, +1 from direction bits + bmi .dunder_roundup @ if -1, round up unconditionally + bne .dunder_rerounded @ if +1, round down unconditionally + adds al, al, #1 @ round up ... + adc ah, ah, #0 + bic al, al, #1 @ ... and then to even + b .dunder_rerounded + +@ === MULTIPLY Double =================================================== + +#define ex_m r14 +#define uh r12 +#define ul r4 +#define rs r4 +#define th r5 +#define tl r11 + +@ --- do_dmul_itos ------------------------------------------------- + Opcode dmul + POP4 al, ah, bl, bh + stmdb sp!, {r4, r5} + mov tmp, #0x7f00000 + orr tmp, tmp, #0x00f0000 + bics ex_m, tmp, ah, LSR #4 @ test for Infs or NaNs + bicnes ex_m, tmp, bh, LSR #4 + beq .dmul_naninf + and ex_m, tmp, ah, LSR #4 @ get exponent of a + eor th, ah, bh @ compute sign of result + orr ex_m, ex_m, th, LSR #31 @ and save it at bottom of ex + ands th, tmp, bh, LSR #4 @ get exponent of b, and test + tstne ah, tmp, LSL #4 @ for zeros/denorms ... + beq .dmul_zerodenorm @ go and renormalise if we got any +.dmul_normalised: + add ex_m, ex_m, th @ calculate exponent of result + sub ex_m, ex_m, #0x3FC0000 @ rebias exponent mostly + bic ah, ah, tmp, LSL #5 @ clear sign and all but lo bit of exp + bic bh, bh, tmp, LSL #5 + orr ah, ah, #1<<20 @ set leading bit on mantissa + orr bh, bh, #1<<20 @ set leading bit on mantissa +.dmul_mantmul: + umull ul, uh, ah, bl + umull tl, th, al, bh + adds tl, tl, ul + adcs th, th, uh @ carry from here is used below + umull ul, uh, ah, bh @ uh:ul is top part + adc bh, uh, #0 @ get carry from above addition + umull ah, uh, al, bl @ uh:ah is bottom part + adds tl, tl, uh + adcs th, th, ul + adcs bh, bh, #0 + tst ah, ah + orrne tl, tl, #1 @ don't lose sticky bit + mov bl, #-4 + mov uh, #32-12 @ uh will be corresponding right shift + cmp bh, #0x200 @ C set if it's 11 bits + adc uh, uh, #0 + adc bl, bl, ex_m, ASR #16 @ increment exponent correspondingly + rsb ul, uh, #32 @ ul is left shift + mov ah, bh, LSL ul + mov al, th, LSL ul + orr ah, ah, th, LSR uh + orr al, al, tl, LSR uh + add ah, ah, bl, LSL #20 @ put exponent back on (may wrap + eor ah, ah, ex_m, LSL #31 @ put sign back on (with EOR so that + movs rs, tl, LSL ul @ compute the round word + beq .dmul_exact + movs uh, rs, LSL #1 @ rs is already in place + movcc rs, #-INX_bit @ direction indicator: rounded down + bcc .dmul_rounded + orreq bh, bh, #1<<31 @ save the round-to-even bit + adcs al, al, #0 @ round up if necessary + adc ah, ah, #0 + mov rs, #INX_bit @ direction indicator: rounded up + tst al, bh, LSR #31 @ does RTE do anything? + bic al, al, bh, LSR #31 @ perform RTE + movne rs, #-INX_bit @ if RTE had effect, we rounded down +.dmul_exact: +.dmul_rounded: + teq ah, ex_m, LSL #31 @ do the signs agree? + mov uh, #0x70000000 @ even if so, need to test exp 0/7FF + orr uh, uh, #0x0ff00000 + bmi .dmul_outflow @ if not, UFL or OFL + tst ah, uh + bicnes uh, uh, ah @ is exp 0 or 7FF? + beq .dmul_outflow +.dmul_exit: + ldmia sp!, {r4, r5} + PUSH2 al, ah + DISPATCH 1 + +.dmul_rdirect: + movs ul, ex_m, LSL #31 @ put sign bit in N + tstpl uh, #2 << 22 @ if +ve: EQ iff round up. Keeps PL + tstmi uh, #1 << 22 @ if -ve: EQ iff round up. + moveq rs, #INX_bit @ rounded up + movne rs, #-INX_bit @ rounded down + addeqs al, al, #1 @ may set C + adc ah, ah, #0 + b .dmul_rounded + +.dmul_outflow: + cmp ex_m, #0x400<<16 @ Which ballpark are we in? + addle ah, ah, #0x60000000 @ Bias up if underflow + subge ah, ah, #0x60000000 @ Bias down if overflow + mov ip, rs + ldmia sp!, {r4, r5} + ble .__dunder @ underflow + b .return_double_Inf + +.dmul_zerodenorm: + orrs ul, al, ah, LSL #1 @ is a zero? + orrnes ul, bl, bh, LSL #1 @ or is b zero? + beq .dmul_zero @ Return zero if so + + tst th, th @ is b denormal? + beq .dmul_renorm_op2 +.dmul_done_op2: + bics ul, ex_m, #1 @ is a denormal? (careful of sign bit) + beq .dmul_renorm_op1 + b .dmul_normalised +.dmul_zero: + mov al, #0 @ clear low word + mov ah, ex_m, LSL #31 @ get sign of result and clear hi word + b .dmul_exit + +.dmul_renorm_op1: + add ex_m, ex_m, #1<<16 @ correct the exponent + bic ah, ah, #0x80000000 @ this will get in our way + orrs tl, ah, al, LSR #12 @ is highest set bit in low twelve? + moveq al, al, LSL #20 @ if so, move it up + subeq ex_m, ex_m, #20<<16 @ and adjust exponent + tst ah, ah @ is highest set bit in low word? + moveq ah, al, LSR #12 @ if so, move up by 20 + moveq al, al, LSL #20 + subeq ex_m, ex_m, #20<<16 @ and adjust exponent + mov ul, #0 @ shift of top word + movs tl, ah, LSR #(21-16) @ is highest set bit within 16 of top? + moveq ah, ah, LSL #16 @ if not, move up + addeq ul, ul, #16 @ and adjust exponent + movs tl, ah, LSR #(21-8) @ is highest set bit within 8 of top? + moveq ah, ah, LSL #8 @ if not, move up + addeq ul, ul, #8 @ and adjust exponent + movs tl, ah, LSR #(21-4) @ is highest set bit within 4 of top? + moveq ah, ah, LSL #4 @ if not, move up + addeq ul, ul, #4 @ and adjust exponent + movs tl, ah, LSR #(21-2) @ is highest set bit within 2 of top? + moveq ah, ah, LSL #2 @ if not, move up + addeq ul, ul, #2 @ and adjust exponent + movs tl, ah, LSR #(21-1) @ is highest set bit within 1 of top? + moveq ah, ah, LSL #1 @ if not, move up + addeq ul, ul, #1 @ and adjust exponent + + sub ex_m, ex_m, ul, LSL #16 @ calculate final pseudo exponent + mov tl, al, LSL ul @ shift low word up by same amout + rsb ul, ul, #32 @ compute reverse shift for al + orr ah, ah, al, LSR ul @ put in high end of low word + mov al, tl + +@ ECN: Reload tmp + mov tmp, #0x7f00000 + orr tmp, tmp, #0x00f0000 + + b .dmul_normalised + +.dmul_renorm_op2: + add th, th, #1<<16 @ correct the exponent + bic bh, bh, #0x80000000 @ this will get in our way + orrs tl, bh, bl, LSR #12 @ is highest set bit in low twelve? + moveq bl, bl, LSL #20 @ if so, move it up + subeq th, th, #20<<16 @ and adjust exponent + tst bh, bh @ is highest set bit in low word? + moveq bh, bl, LSR #12 @ if so, move up by 20 + moveq bl, bl, LSL #20 + subeq th, th, #20<<16 @ and adjust exponent + mov ul, #0 @ shift of top word + movs tl, bh, LSR #(21-16) @ is highest set bit within 16 of top? + moveq bh, bh, LSL #16 @ if not, move up + addeq ul, ul, #16 @ and adjust exponent + movs tl, bh, LSR #(21-8) @ is highest set bit within 8 of top? + moveq bh, bh, LSL #8 @ if not, move up + addeq ul, ul, #8 @ and adjust exponent + movs tl, bh, LSR #(21-4) @ is highest set bit within 4 of top? + moveq bh, bh, LSL #4 @ if not, move up + addeq ul, ul, #4 @ and adjust exponent + movs tl, bh, LSR #(21-2) @ is highest set bit within 2 of top? + moveq bh, bh, LSL #2 @ if not, move up + addeq ul, ul, #2 @ and adjust exponent + movs tl, bh, LSR #(21-1) @ is highest set bit within 1 of top? + moveq bh, bh, LSL #1 @ if not, move up + addeq ul, ul, #1 @ and adjust exponent + + sub th, th, ul, LSL #16 @ calculate final pseudo exponent + mov tl, bl, LSL ul @ shift low word up by same amout + rsb ul, ul, #32 @ compute reverse shift for bl + orr bh, bh, bl, LSR ul @ put in high end of low word + mov bl, tl + +@ ECN: Reload tmp + mov tmp, #0x7f00000 + orr tmp, tmp, #0x00f0000 + + b .dmul_done_op2 + +.dmul_naninf: + mov uh, ah, LSL #1 @ discard sign bit on a + mov ul, bh, LSL #1 @ and on b + cmp uh, tmp, LSL #5 @ HI if ah shows a to be NaN + cmpeq al, #0 @ now HI if a is NaN + cmpls ul, tmp, LSL #5 @ another chance to set HI ... + cmpeq bl, #0 @ ... if b is NaN + bhi .dmul_ivo + orrs ul, al, ah, LSL #1 @ is a zero? + orrnes ul, bl, bh, LSL #1 @ or is b zero? + beq .dmul_ivo + eor ah, ah, bh + mov al, #0 + and ah, ah, #0x80000000 + orr ah, ah, tmp, LSL #4 + b .dmul_exit + +.dmul_ivo: + ldmia sp!, {r4, r5} + b .return_double_NaN + +#undef al +#undef ah +#undef bl +#undef bh +#undef tmp +#undef sh +#undef ex_add + +#undef INX_pos +#undef INX_bit + +#undef exp +#undef temp + +#undef ex_m +#undef uh +#undef ul +#undef rs +#undef th +#undef tl + +@ --- ignore_safepoints --------------------------------------------------------------------------- + .global _ZN14CppInterpreter17ignore_safepointsEv + .type _ZN14CppInterpreter17ignore_safepointsEv, %function +_ZN14CppInterpreter17ignore_safepointsEv: + adrl ip, dispatch_init_adcon + ldmia ip, {r2, r3} + add r2, r2, ip + add ip, r3, r2 + ldr r2, [ip, #AbstractInterpreter_notice_safepoints-XXX] + ldrb r1, [r2, #0] @ zero_extendqisi2 + cmp r1, #0 + bxeq lr + mov r3, #0 + strb r3, [r2, #0] + adrl r3, main_dispatch_table + mov r2, #256 +1: + ldr r1, [r3], #4 + str r1, [ip], #4 + subs r2, r2, #1 + bne 1b + + bx lr + +@ --- notice_safepoints --------------------------------------------------------------------------- + .global _ZN14CppInterpreter17notice_safepointsEv + .type _ZN14CppInterpreter17notice_safepointsEv, %function +_ZN14CppInterpreter17notice_safepointsEv: + adrl ip, dispatch_init_adcon + ldmia ip, {r2, r3} + add r2, r2, ip + add ip, r3, r2 + ldr r2, [ip, #AbstractInterpreter_notice_safepoints-XXX] + ldrb r1, [r2, #0] @ zero_extendqisi2 + cmp r1, #0 + bxne lr + mov r3, #1 + strb r3, [r2, #0] + adrl r3, safe_dispatch_table + mov r2, #256 +1: + ldr r1, [r3], #4 + str r1, [ip], #4 + subs r2, r2, #1 + bne 1b + + bx lr + +@ --- END execute.s ---------------------------------------------------------------------------- + +bci_init: + adr r3, dispatch_init_adcon + ldmia r3, {r0, r1} + add r0, r0, r3 + add r1, r1, r0 + adr r2, adcon_init_table + mov r3, r1 +1: + ldr ip, [r2], #4 + cmp ip, #0 + ldrne ip, [r0, ip] + strne ip, [r1, #-4]! + bne 1b + adr r2, main_dispatch_table + mov r1, #256 +2: + ldr ip, [r2], #4 + str ip, [r3], #4 + subs r1, r1, #1 + bne 2b + + bx lr + + ALIGN_DATA +dispatch_init_adcon: + .word _GLOBAL_OFFSET_TABLE_-dispatch_init_adcon, opclabels_data(GOTOFF) +adcon_init_table: + .word _ZN18InterpreterRuntime22slow_signature_handlerEP10JavaThreadP13methodOopDescPiS4_(GOT) + .word _ZN20SafepointSynchronize6_stateE(GOT) + .word _ZN9vmSymbols8_symbolsE(GOT) + .word always_do_update_barrier(GOT) + .word UseBiasedLocking(GOT) + .word _ZN8Universe14_collectedHeapE(GOT) + .word ZeroTLAB(GOT) + .word UseTLAB(GOT) + .word _ZN9Bytecodes5_nameE(GOT) + .word _ZN19AbstractInterpreter18_notice_safepointsE(GOT) + .word _ZN18ThreadLocalStorage13_thread_indexE(GOT) + .word 0 + + ALIGN_DATA +main_dispatch_table: + MAIN_DISPATCH_TABLE +safe_dispatch_table: + .word do_nop + .word do_u4const_0 + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_iconst_N + .word do_u8const_0 + .word do_lconst_1 + .word do_u4const_0 + .word do_fconst_1 + .word do_fconst_2 + .word do_u8const_0 + .word do_dconst_1 + .word do_bipush + .word do_sipush + .word do_ldc + .word do_ldc_w + .word do_ldc2_w + .word do_u4load + .word do_u8load + .word do_u4load + .word do_u8load + .word do_u4load + .word do_iload_0 + .word do_iload_0 + .word do_iload_0 + .word do_iload_0 + .word do_u8load_0 + .word do_u8load_1 + .word do_u8load_2 + .word do_u8load_3 + .word do_fload_0 + .word do_fload_0 + .word do_fload_0 + .word do_fload_0 + .word do_u8load_0 + .word do_u8load_1 + .word do_u8load_2 + .word do_u8load_3 + .word do_aload_0 + .word do_aload_0 + .word do_aload_0 + .word do_aload_0 + .word do_u4aload + .word do_u8aload + .word do_u4aload + .word do_u8aload + .word do_u4aload + .word do_baload + .word do_caload + .word do_saload + .word do_u4store + .word do_u8store + .word do_u4store + .word do_u8store + .word do_u4store + .word do_u4store_0 + .word do_u4store_1 + .word do_u4store_2 + .word do_u4store_3 + .word do_u8store_0 + .word do_u8store_1 + .word do_u8store_2 + .word do_u8store_3 + .word do_u4store_0 + .word do_u4store_1 + .word do_u4store_2 + .word do_u4store_3 + .word do_u8store_0 + .word do_u8store_1 + .word do_u8store_2 + .word do_u8store_3 + .word do_u4store_0 + .word do_u4store_1 + .word do_u4store_2 + .word do_u4store_3 + .word do_u4astore + .word do_u8astore + .word do_u4astore + .word do_u8astore + .word do_aastore + .word do_bastore + .word do_u2astore + .word do_u2astore + .word do_jpop + .word do_jpop2 + .word do_dup + .word do_dup_x1 + .word do_dup_x2 + .word do_dup2 + .word do_dup2_x1 + .word do_dup2_x2 + .word do_swap + .word do_iadd + .word do_ladd + .word do_fadd + .word do_dadd + .word do_isub + .word do_lsub + .word do_fsub + .word do_dsub + .word do_imul + .word do_lmul + .word do_fmul + .word do_dmul + .word do_idiv + .word do_ldiv + .word do_fdiv + .word do_ddiv + .word do_irem + .word do_lrem + .word do_frem + .word do_drem + .word do_ineg + .word do_lneg + .word do_fneg + .word do_dneg + .word do_ishl + .word do_lshl + .word do_ishr + .word do_lshr + .word do_iushr + .word do_lushr + .word do_iand + .word do_land + .word do_ior + .word do_lor + .word do_ixor + .word do_lxor + .word do_iinc + .word do_i2l + .word do_i2f + .word do_i2d + .word do_l2i + .word do_l2f + .word do_l2d + .word do_f2i + .word do_f2l + .word do_f2d + .word do_d2i + .word do_d2l + .word do_d2f + .word do_i2b + .word do_i2c + .word do_i2s + .word do_lcmp + .word do_fcmpl + .word do_fcmpg + .word do_dcmpl + .word do_dcmpg + .word do_ifeq_safe + .word do_ifne_safe + .word do_iflt_safe + .word do_ifge_safe + .word do_ifgt_safe + .word do_ifle_safe + .word do_if_icmpeq_safe + .word do_if_icmpne_safe + .word do_if_icmplt_safe + .word do_if_icmpge_safe + .word do_if_icmpgt_safe + .word do_if_icmple_safe + .word do_if_icmpeq_safe + .word do_if_icmpne_safe + .word do_goto_safe + .word do_jsr + .word do_ret + .word do_tableswitch + .word do_lookupswitch + .word do_ireturn_safe + .word do_lreturn_safe + .word do_ireturn_safe + .word do_lreturn_safe + .word do_ireturn_safe + .word do_return_safe + .word do_getstatic + .word do_putstatic + .word do_getfield + .word do_putfield + .word do_invokevirtual + .word do_invokespecial + .word do_invokestatic + .word do_invokeinterface + .word do_undefined + .word do_new + .word do_newarray + .word do_anewarray + .word do_arraylength + .word do_athrow + .word do_checkcast + .word do_instanceof + .word do_monitorenter + .word do_monitorexit + .word do_wide + .word do_multianewarray + .word do_ifeq_safe + .word do_ifne_safe + .word do_goto_w + .word do_jsr_w + .word do_breakpoint + .word do_undefined + .word do_bgetfield + .word do_cgetfield + .word do_undefined + .word do_undefined + .word do_igetfield + .word do_lgetfield + .word do_sgetfield + .word do_aputfield + .word do_bputfield + .word do_cputfield + .word do_undefined + .word do_undefined + .word do_iputfield + .word do_lputfield + .word do_undefined + .word do_iaccess_0 + .word do_iaccess_0 + .word do_iaccess_0 + .word do_iaccess_0 + .word do_undefined + .word do_undefined + .word do_undefined + .word do_invokevfinal + .word do_undefined + .word do_undefined + .word do_return_register_finalizer + .word do_undefined + .word do_iload_0_iconst_N + .word do_iload_0_iconst_N + .word do_iload_0_iconst_N + .word do_iload_0_iconst_N + .word do_iload_iconst_N + .word do_invokeresolved + .word do_iadd_istore_N + .word do_isub_istore_N + .word do_iand_istore_N + .word do_ior_istore_N + .word do_ixor_istore_N + .word do_iadd_u4store + .word do_isub_u4store + .word do_iand_u4store + .word do_ior_u4store + .word do_ixor_u4store + .word do_invokespecialresolved + .word do_invokestaticresolved + .word do_undefined + .word do_undefined + .word do_undefined + .word do_undefined + .word do_undefined + .word do_undefined + .word do_undefined + + SUB_DISPATCH_TABLES + + .section .init_array,"aw",%init_array + .word bci_init(target1) + + .data + ALIGN_DATA + .word 0, 0, 0, 0, 0 +ThreadLocalStorage_thread_index: .word 0 +AbstractInterpreter_notice_safepoints: .word 0 +Bytecodes_name_Address: .word 0 +UseTLAB_Address: .word 0 +ZeroTLAB_Address: .word 0 +Universe_collectedHeap_Address: .word 0 +UseBiasedLocking_Address: .word 0 +always_do_update_barrier_Address: .word 0 +VmSymbols_symbols_Address: .word 0 +SafePointSynchronize_state_Address: .word 0 +InterpreterRuntime_slow_signature_handler_Address: .word 0 +XXX: +opclabels_data: + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +#endif // HOTSPOT_ASM
--- a/ports/hotspot/src/cpu/zero/vm/cppInterpreter_zero.cpp Thu Aug 13 15:48:51 2009 +0100 +++ b/ports/hotspot/src/cpu/zero/vm/cppInterpreter_zero.cpp Fri Aug 21 13:35:04 2009 +0200 @@ -721,11 +721,25 @@ return generate_entry(CppInterpreter::normal_entry); } +#if defined(PRODUCT) && defined(HOTSPOT_ASM) +typedef void (*BCI_ENTRY)(methodOopDesc*, intptr_t, Thread*); +extern "C" BCI_ENTRY asm_generate_method_entry(AbstractInterpreter::MethodKind kind); +#endif // HOTSPOT_ASM + address AbstractInterpreterGenerator::generate_method_entry( AbstractInterpreter::MethodKind kind) { address entry_point = NULL; +#if defined(PRODUCT) && defined(HOTSPOT_ASM) + if (!UseCompiler && !TaggedStackInterpreter && !JvmtiExport::can_post_interpreter_events() + && !PrintCommandLineFlags) { + BCI_ENTRY asm_entry = asm_generate_method_entry(kind); + if (asm_entry) + return ((InterpreterGenerator*)this)->generate_entry(asm_entry); + } +#endif // HOTSPOT_ASM + switch (kind) { case Interpreter::zerolocals: case Interpreter::zerolocals_synchronized:
--- a/ports/hotspot/src/os_cpu/linux_zero/vm/os_linux_zero.cpp Thu Aug 13 15:48:51 2009 +0100 +++ b/ports/hotspot/src/os_cpu/linux_zero/vm/os_linux_zero.cpp Fri Aug 21 13:35:04 2009 +0200 @@ -78,6 +78,10 @@ Unimplemented(); } +#if defined(PRODUCT) && defined(HOTSPOT_ASM) +extern "C" int asm_check_null_ptr(ucontext_t *uc); +#endif // HOTSPOT_ASM + extern "C" int JVM_handle_linux_signal(int sig, siginfo_t* info, @@ -86,6 +90,12 @@ { ucontext_t* uc = (ucontext_t*) ucVoid; +#if defined(PRODUCT) && defined(HOTSPOT_ASM) + if (sig == SIGSEGV) { + if (asm_check_null_ptr(uc)) return 1; + } +#endif // HOTSPOT_ASM + Thread* t = ThreadLocalStorage::get_thread_slow(); SignalHandlerMark shm(t);