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changeset 10815:7caa24d952f7 icedtea-3.17.0

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8248219, PR3797: aarch64: missing memory barrier in fast_storefield and fast_accessfield Reviewed-by: aph Contributed-by: songyaofei2@huawei.com
author fyang
date Mon, 06 Jul 2020 06:58:59 +0800
parents 0f519a0fd1da
children dec52e41e748
files src/cpu/aarch64/vm/templateTable_aarch64.cpp
diffstat 1 files changed, 7 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/src/cpu/aarch64/vm/templateTable_aarch64.cpp	Mon Jun 22 20:26:02 2020 +0800
+++ b/src/cpu/aarch64/vm/templateTable_aarch64.cpp	Mon Jul 06 06:58:59 2020 +0800
@@ -2888,6 +2888,9 @@
   // access constant pool cache
   __ get_cache_and_index_at_bcp(r2, r1, 1);
 
+  // Must prevent reordering of the following cp cache loads with bytecode load
+  __ membar(MacroAssembler::LoadLoad);
+
   // test for volatile with r3
   __ ldrw(r3, Address(r2, in_bytes(base +
 				   ConstantPoolCacheEntry::flags_offset())));
@@ -2979,6 +2982,10 @@
 
   // access constant pool cache
   __ get_cache_and_index_at_bcp(r2, r1, 1);
+
+  // Must prevent reordering of the following cp cache loads with bytecode load
+  __ membar(MacroAssembler::LoadLoad);
+
   __ ldr(r1, Address(r2, in_bytes(ConstantPoolCache::base_offset() +
                                   ConstantPoolCacheEntry::f2_offset())));
   __ ldrw(r3, Address(r2, in_bytes(ConstantPoolCache::base_offset() +