Mercurial > hg > icedtea8-forest > hotspot
changeset 10839:bc185d95c9f5
8253284: Zero OrderAccess barrier mappings are incorrect
Reviewed-by: dholmes, aph, andrew
| author | shade |
|---|---|
| date | Tue, 22 Sep 2020 08:33:42 +0000 |
| parents | 321a84a5e5b8 |
| children | 1dde8affa7e6 |
| files | src/os_cpu/bsd_zero/vm/orderAccess_bsd_zero.inline.hpp src/os_cpu/linux_zero/vm/orderAccess_linux_zero.inline.hpp |
| diffstat | 2 files changed, 35 insertions(+), 27 deletions(-) [+] |
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--- a/src/os_cpu/bsd_zero/vm/orderAccess_bsd_zero.inline.hpp Fri Dec 21 16:56:40 2018 +0100 +++ b/src/os_cpu/bsd_zero/vm/orderAccess_bsd_zero.inline.hpp Tue Sep 22 08:33:42 2020 +0000 @@ -29,7 +29,7 @@ #include "runtime/orderAccess.hpp" #include "vm_version_zero.hpp" -#ifdef ARM +#if defined(ARM) // ---------------------------------------------------- /* * ARM Kernel helper for memory barrier. @@ -40,32 +40,36 @@ typedef void (__kernel_dmb_t) (void); #define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0) -#define FULL_MEM_BARRIER __kernel_dmb() -#define READ_MEM_BARRIER __kernel_dmb() +#define READ_MEM_BARRIER __kernel_dmb() #define WRITE_MEM_BARRIER __kernel_dmb() +#define FULL_MEM_BARRIER __kernel_dmb() -#else // ARM - -#define FULL_MEM_BARRIER __sync_synchronize() - -#ifdef PPC +#elif defined(PPC) // ---------------------------------------------------- #ifdef __NO_LWSYNC__ -#define READ_MEM_BARRIER __asm __volatile ("sync":::"memory") +#define READ_MEM_BARRIER __asm __volatile ("sync":::"memory") #define WRITE_MEM_BARRIER __asm __volatile ("sync":::"memory") #else -#define READ_MEM_BARRIER __asm __volatile ("lwsync":::"memory") +#define READ_MEM_BARRIER __asm __volatile ("lwsync":::"memory") #define WRITE_MEM_BARRIER __asm __volatile ("lwsync":::"memory") #endif +#define FULL_MEM_BARRIER __sync_synchronize() -#else // PPC +#elif defined(X86) // ---------------------------------------------------- -#define READ_MEM_BARRIER __asm __volatile ("":::"memory") +#define READ_MEM_BARRIER __asm __volatile ("":::"memory") #define WRITE_MEM_BARRIER __asm __volatile ("":::"memory") +#define FULL_MEM_BARRIER __sync_synchronize() -#endif // PPC +#else // ---------------------------------------------------- + +// Default to strongest barriers for correctness. -#endif // ARM +#define READ_MEM_BARRIER __sync_synchronize() +#define WRITE_MEM_BARRIER __sync_synchronize() +#define FULL_MEM_BARRIER __sync_synchronize() + +#endif // ---------------------------------------------------- inline void OrderAccess::loadload() { acquire(); }
--- a/src/os_cpu/linux_zero/vm/orderAccess_linux_zero.inline.hpp Fri Dec 21 16:56:40 2018 +0100 +++ b/src/os_cpu/linux_zero/vm/orderAccess_linux_zero.inline.hpp Tue Sep 22 08:33:42 2020 +0000 @@ -29,7 +29,7 @@ #include "runtime/orderAccess.hpp" #include "vm_version_zero.hpp" -#ifdef ARM +#if defined(ARM) // ---------------------------------------------------- /* * ARM Kernel helper for memory barrier. @@ -40,31 +40,35 @@ typedef void (__kernel_dmb_t) (void); #define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0) -#define FULL_MEM_BARRIER __kernel_dmb() -#define READ_MEM_BARRIER __kernel_dmb() +#define READ_MEM_BARRIER __kernel_dmb() #define WRITE_MEM_BARRIER __kernel_dmb() - -#else // ARM +#define FULL_MEM_BARRIER __kernel_dmb() -#define FULL_MEM_BARRIER __sync_synchronize() +#elif defined(PPC) // ---------------------------------------------------- -#ifdef PPC - -#define READ_MEM_BARRIER __asm __volatile ("isync":::"memory") +#define READ_MEM_BARRIER __asm __volatile ("isync":::"memory") #ifdef __NO_LWSYNC__ #define WRITE_MEM_BARRIER __asm __volatile ("sync":::"memory") #else #define WRITE_MEM_BARRIER __asm __volatile ("lwsync":::"memory") #endif +#define FULL_MEM_BARRIER __sync_synchronize() -#else // PPC +#elif defined(X86) // ---------------------------------------------------- -#define READ_MEM_BARRIER __asm __volatile ("":::"memory") +#define READ_MEM_BARRIER __asm __volatile ("":::"memory") #define WRITE_MEM_BARRIER __asm __volatile ("":::"memory") +#define FULL_MEM_BARRIER __sync_synchronize() -#endif // PPC +#else // ---------------------------------------------------- + +// Default to strongest barriers for correctness. -#endif // ARM +#define READ_MEM_BARRIER __sync_synchronize() +#define WRITE_MEM_BARRIER __sync_synchronize() +#define FULL_MEM_BARRIER __sync_synchronize() + +#endif // ---------------------------------------------------- inline void OrderAccess::loadload() { acquire(); }