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view src/share/vm/opto/regmask.hpp @ 10905:f57189b7648d
8257192: Integrate AArch64 JIT port into 8u
7009641: Don't fail VM when CodeCache is full
8073108: [AArch64] Use x86 and SPARC CPU instructions for GHASH acceleration
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space (AArch64 changes)
8131779: AARCH64: add Montgomery multiply intrinsic
8132875: AArch64: Fix error introduced into AArch64 CodeCache by commit for 8130309
8135018: AARCH64: Missing memory barriers for CMS collector
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
8148328: aarch64: redundant lsr instructions in stub code.
8148783: aarch64: SEGV running SpecJBB2013
8148948: aarch64: generate_copy_longs calls align() incorrectly
8149080: AArch64: Recognise disjoint array copy in stub code
8149365: aarch64: memory copy does not prefetch on backwards copy
8149907: aarch64: use load/store pair instructions in call_stub
8150038: aarch64: make use of CBZ and CBNZ when comparing narrow pointer with zero
8150045: arraycopy causes segfaults in SATB during garbage collection
8150082: aarch64: optimise small array copy
8150229: aarch64: pipeline class for several instructions is not set correctly
8150313: aarch64: optimise array copy using SIMD instructions
8150394: aarch64: add support for 8.1 LSE CAS instructions
8150652: Remove unused code in AArch64 back end
8151340: aarch64: prefetch the destination word for write prior to ldxr/stxr loops.
8151502: optimize pd_disjoint_words and pd_conjoint_words
8151775: aarch64: add support for 8.1 LSE atomic operations
8152537: aarch64: Make use of CBZ and CBNZ when comparing unsigned values with zero.
8152840: aarch64: improve _unsafe_arraycopy stub routine
8153172: aarch64: hotspot crashes after the 8.1 LSE patch is merged
8153713: aarch64: improve short array clearing using store pair
8153797: aarch64: Add Arrays.fill stub code
8154413: AArch64: Better byte behaviour
8154537: AArch64: some integer rotate instructions are never emitted
8154739: AArch64: TemplateTable::fast_xaccess loads in wrong mode
8155015: Aarch64: bad assert in spill generation code
8155100: AArch64: Relax alignment requirement for byte_map_base
8155612: Aarch64: vector nodes need to support misaligned offset
8155617: aarch64: ClearArray does not use DC ZVA
8155627: Enable SA on AArch64
8155653: TestVectorUnalignedOffset.java not pushed with 8155612
8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
8157841: aarch64: prefetch ignores cache line size
8157906: aarch64: some more integer rotate instructions are never emitted
8158913: aarch64: SEGV running Spark terasort
8159052: aarch64: optimise unaligned copies in pd_disjoint_words and pd_conjoint_words
8159063: aarch64: optimise unaligned array copy long
8160748: [AArch64] Inconsistent types for ideal_reg
8161072: AArch64: jtreg compiler/uncommontrap/TestDeoptOOM failure
8161190: AArch64: Fix overflow in immediate cmp instruction
8164113: AArch64: follow-up the fix for 8161598
8165673: AArch64: Fix JNI floating point argument handling
8167200: AArch64: Broken stack pointer adjustment in interpreter
8167421: AArch64: in one core system, fatal error: Illegal threadstate encountered
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
8168699: Validate special case invocations [AArch64 support]
8168888: Port 8160591: Improve internal array handling to AArch64.
8170100: AArch64: Crash in C1-compiled code accessing References
8170188: jtreg test compiler/types/TestMeetIncompatibleInterfaceArrays.java causes JVM crash
8170873: PPC64/aarch64: Poor StrictMath performance due to non-optimized compilation
8171537: aarch64: compiler/c1/Test6849574.java generates guarantee failure in C1
8172881: AArch64: assertion failure: the int pressure is incorrect
8173472: AArch64: C1 comparisons with null only use 32-bit instructions
8176100: [AArch64] [REDO][REDO] G1 Needs pre barrier on dereference of weak JNI handles
8177661: Correct ad rule output register types from iRegX to iRegXNoSp
8179954: AArch64: C1 and C2 volatile accesses are not sequentially consistent
8182581: aarch64: fix for crash caused by earlyret of compiled method
8183925: [AArch64] Decouple crash protection from watcher thread
8186325: AArch64: jtreg test hotspot/test/gc/g1/TestJNIWeakG1/TestJNIWeakG1.java SEGV
8187224: aarch64: some inconsistency between aarch64_ad.m4 and aarch64.ad
8189170: [AArch64] Add option to disable stack overflow checking in primordial thread for use with JNI_CreateJavaJVM
8193133: Assertion failure because 0xDEADDEAD can be in-heap
8195685: AArch64 port of 8174962: Better interface invocations
8195859: AArch64: vtableStubs gtest fails after 8174962
8196136: AArch64: Correct register use in patch for JDK-8194686
8196221: AArch64: Mistake in committed patch for JDK-8195859
8199712: [AArch64] Flight Recorder
8203481: Incorrect constraint for unextended_sp in frame:safe_for_sender
8203699: java/lang/invoke/SpecialInterfaceCall fails with SIGILL on aarch64
8205421: AARCH64: StubCodeMark should be placed after alignment
8206163: AArch64: incorrect code generation for StoreCM
8207345: Trampoline generation code reads from uninitialized memory
8207838: AArch64: Float registers incorrectly restored in JNI call
8209413: AArch64: NPE in clhsdb jstack command
8209414: [AArch64] method handle invocation does not respect JVMTI interp_only mode
8209415: Fix JVMTI test failure HS202
8209420: Track membars for volatile accesses so they can be properly optimized
8209835: Aarch64: elide barriers on all volatile operations
8210425: [AArch64] sharedRuntimeTrig/sharedRuntimeTrans compiled without optimization
8211064: [AArch64] Interpreter and c1 don't correctly handle jboolean results in native calls
8211233: MemBarNode::trailing_membar() and MemBarNode::leading_membar() need to handle dying subgraphs better
8213134: AArch64: vector shift failed with MaxVectorSize=8
8213419: [AArch64] C2 may hang in MulLNode::Ideal()/MulINode::Ideal() with gcc 8.2.1
8214857: "bad trailing membar" assert failure at memnode.cpp:3220
8215951: AArch64: jtreg test vmTestbase/nsk/jvmti/PopFrame/popframe005 segfaults
8215961: jdk/jfr/event/os/TestCPUInformation.java fails on AArch64
8216350: AArch64: monitor unlock fast path not called
8216989: CardTableBarrierSetAssembler::gen_write_ref_array_post_barrier() does not check for zero length on AARCH64
8217368: AArch64: C2 recursive stack locking optimisation not triggered
8218185: aarch64: missing LoadStore barrier in TemplateTable::putfield_or_static
8219011: Implement MacroAssembler::warn method on AArch64
8219635: aarch64: missing LoadStore barrier in TemplateTable::fast_storefield
8221220: AArch64: Add StoreStore membar explicitly for Volatile Writes in TemplateTable
8221658: aarch64: add necessary predicate for ubfx patterns
8224671: AArch64: mauve System.arraycopy test failure
8224828: aarch64: rflags is not correct after safepoint poll
8224851: AArch64: fix warnings and errors with Clang and GCC 8.3
8224880: AArch64: java/javac error with AllocatePrefetchDistance
8228400: Remove built-in AArch64 simulator
8228406: Superfluous change in chaitin.hpp
8228593: Revert explicit JDK 7 support additions
8228716: Revert InstanceKlass::print_on debug additions
8228718: Revert incorrect backport of JDK-8129757 to 8-aarch64
8228725: AArch64: Purge method call format support
8228747: Revert "unused" attribute from test_arraycopy_func
8228767: Revert ResourceMark additions
8228770: Revert development hsdis changes
8229123: Revert build fixes for aarch64/zero
8229124: Revert disassembler.cpp changes
8229145: Revert TemplateTable::bytecode() visibility change
8233839: aarch64: missing memory barrier in NewObjectArrayStub and NewTypeArrayStub
8237512: AArch64: aarch64TestHook leaks a BufferBlob
8246482: Build failures with +JFR -PCH
8247979: aarch64: missing side effect of killing flags for clearArray_reg_reg
8248219: aarch64: missing memory barrier in fast_storefield and fast_accessfield
Reviewed-by: shade, aph
author | andrew |
---|---|
date | Mon, 01 Feb 2021 03:48:36 +0000 |
parents | ddce0b7cee93 |
children | f79e943d15a7 |
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/* * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * */ #ifndef SHARE_VM_OPTO_REGMASK_HPP #define SHARE_VM_OPTO_REGMASK_HPP #include "code/vmreg.hpp" #include "libadt/port.hpp" #include "opto/optoreg.hpp" #if defined ADGLOBALS_MD_HPP # include ADGLOBALS_MD_HPP #elif defined TARGET_ARCH_MODEL_x86_32 # include "adfiles/adGlobals_x86_32.hpp" #elif defined TARGET_ARCH_MODEL_x86_64 # include "adfiles/adGlobals_x86_64.hpp" #elif defined TARGET_ARCH_MODEL_aarch64 # include "adfiles/adGlobals_aarch64.hpp" #elif defined TARGET_ARCH_MODEL_sparc # include "adfiles/adGlobals_sparc.hpp" #elif defined TARGET_ARCH_MODEL_zero # include "adfiles/adGlobals_zero.hpp" #elif defined TARGET_ARCH_MODEL_ppc_64 # include "adfiles/adGlobals_ppc_64.hpp" #endif // Some fun naming (textual) substitutions: // // RegMask::get_low_elem() ==> RegMask::find_first_elem() // RegMask::Special ==> RegMask::Empty // RegMask::_flags ==> RegMask::is_AllStack() // RegMask::operator<<=() ==> RegMask::Insert() // RegMask::operator>>=() ==> RegMask::Remove() // RegMask::Union() ==> RegMask::OR // RegMask::Inter() ==> RegMask::AND // // OptoRegister::RegName ==> OptoReg::Name // // OptoReg::stack0() ==> _last_Mach_Reg or ZERO in core version // // numregs in chaitin ==> proper degree in chaitin //-------------Non-zero bit search methods used by RegMask--------------------- // Find lowest 1, or return 32 if empty int find_lowest_bit( uint32 mask ); // Find highest 1, or return 32 if empty int find_hihghest_bit( uint32 mask ); //------------------------------RegMask---------------------------------------- // The ADL file describes how to print the machine-specific registers, as well // as any notion of register classes. We provide a register mask, which is // just a collection of Register numbers. // The ADLC defines 2 macros, RM_SIZE and FORALL_BODY. // RM_SIZE is the size of a register mask in words. // FORALL_BODY replicates a BODY macro once per word in the register mask. // The usage is somewhat clumsy and limited to the regmask.[h,c]pp files. // However, it means the ADLC can redefine the unroll macro and all loops // over register masks will be unrolled by the correct amount. class RegMask VALUE_OBJ_CLASS_SPEC { union { double _dummy_force_double_alignment[RM_SIZE>>1]; // Array of Register Mask bits. This array is large enough to cover // all the machine registers and all parameters that need to be passed // on the stack (stack registers) up to some interesting limit. Methods // that need more parameters will NOT be compiled. On Intel, the limit // is something like 90+ parameters. int _A[RM_SIZE]; }; enum { _WordBits = BitsPerInt, _LogWordBits = LogBitsPerInt, _RM_SIZE = RM_SIZE // local constant, imported, then hidden by #undef }; public: enum { CHUNK_SIZE = RM_SIZE*_WordBits }; // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits. // Also, consider the maximum alignment size for a normally allocated // value. Since we allocate register pairs but not register quads (at // present), this alignment is SlotsPerLong (== 2). A normally // aligned allocated register is either a single register, or a pair // of adjacent registers, the lower-numbered being even. // See also is_aligned_Pairs() below, and the padding added before // Matcher::_new_SP to keep allocated pairs aligned properly. // If we ever go to quad-word allocations, SlotsPerQuad will become // the controlling alignment constraint. Note that this alignment // requirement is internal to the allocator, and independent of any // particular platform. enum { SlotsPerLong = 2, SlotsPerVecS = 1, SlotsPerVecD = 2, SlotsPerVecX = 4, SlotsPerVecY = 8 }; // A constructor only used by the ADLC output. All mask fields are filled // in directly. Calls to this look something like RM(1,2,3,4); RegMask( # define BODY(I) int a##I, FORALL_BODY # undef BODY int dummy = 0 ) { # define BODY(I) _A[I] = a##I; FORALL_BODY # undef BODY } // Handy copying constructor RegMask( RegMask *rm ) { # define BODY(I) _A[I] = rm->_A[I]; FORALL_BODY # undef BODY } // Construct an empty mask RegMask( ) { Clear(); } // Construct a mask with a single bit RegMask( OptoReg::Name reg ) { Clear(); Insert(reg); } // Check for register being in mask int Member( OptoReg::Name reg ) const { assert( reg < CHUNK_SIZE, "" ); return _A[reg>>_LogWordBits] & (1<<(reg&(_WordBits-1))); } // The last bit in the register mask indicates that the mask should repeat // indefinitely with ONE bits. Returns TRUE if mask is infinite or // unbounded in size. Returns FALSE if mask is finite size. int is_AllStack() const { return _A[RM_SIZE-1] >> (_WordBits-1); } // Work around an -xO3 optimization problme in WS6U1. The old way: // void set_AllStack() { _A[RM_SIZE-1] |= (1<<(_WordBits-1)); } // will cause _A[RM_SIZE-1] to be clobbered, not updated when set_AllStack() // follows an Insert() loop, like the one found in init_spill_mask(). Using // Insert() instead works because the index into _A in computed instead of // constant. See bug 4665841. void set_AllStack() { Insert(OptoReg::Name(CHUNK_SIZE-1)); } // Test for being a not-empty mask. int is_NotEmpty( ) const { int tmp = 0; # define BODY(I) tmp |= _A[I]; FORALL_BODY # undef BODY return tmp; } // Find lowest-numbered register from mask, or BAD if mask is empty. OptoReg::Name find_first_elem() const { int base, bits; # define BODY(I) if( (bits = _A[I]) != 0 ) base = I<<_LogWordBits; else FORALL_BODY # undef BODY { base = OptoReg::Bad; bits = 1<<0; } return OptoReg::Name(base + find_lowest_bit(bits)); } // Get highest-numbered register from mask, or BAD if mask is empty. OptoReg::Name find_last_elem() const { int base, bits; # define BODY(I) if( (bits = _A[RM_SIZE-1-I]) != 0 ) base = (RM_SIZE-1-I)<<_LogWordBits; else FORALL_BODY # undef BODY { base = OptoReg::Bad; bits = 1<<0; } return OptoReg::Name(base + find_hihghest_bit(bits)); } // Find the lowest-numbered register pair in the mask. Return the // HIGHEST register number in the pair, or BAD if no pairs. // Assert that the mask contains only bit pairs. OptoReg::Name find_first_pair() const; // Clear out partial bits; leave only aligned adjacent bit pairs. void clear_to_pairs(); // Smear out partial bits; leave only aligned adjacent bit pairs. void smear_to_pairs(); // Verify that the mask contains only aligned adjacent bit pairs void verify_pairs() const { assert( is_aligned_pairs(), "mask is not aligned, adjacent pairs" ); } // Test that the mask contains only aligned adjacent bit pairs bool is_aligned_pairs() const; // mask is a pair of misaligned registers bool is_misaligned_pair() const { return Size()==2 && !is_aligned_pairs(); } // Test for single register int is_bound1() const; // Test for a single adjacent pair int is_bound_pair() const; // Test for a single adjacent set of ideal register's size. int is_bound(uint ireg) const { if (is_vector(ireg)) { if (is_bound_set(num_registers(ireg))) return true; } else if (is_bound1() || is_bound_pair()) { return true; } return false; } // Find the lowest-numbered register set in the mask. Return the // HIGHEST register number in the set, or BAD if no sets. // Assert that the mask contains only bit sets. OptoReg::Name find_first_set(const int size) const; // Clear out partial bits; leave only aligned adjacent bit sets of size. void clear_to_sets(const int size); // Smear out partial bits to aligned adjacent bit sets. void smear_to_sets(const int size); // Verify that the mask contains only aligned adjacent bit sets void verify_sets(int size) const { assert(is_aligned_sets(size), "mask is not aligned, adjacent sets"); } // Test that the mask contains only aligned adjacent bit sets bool is_aligned_sets(const int size) const; // mask is a set of misaligned registers bool is_misaligned_set(int size) const { return (int)Size()==size && !is_aligned_sets(size);} // Test for a single adjacent set int is_bound_set(const int size) const; static bool is_vector(uint ireg); static int num_registers(uint ireg); // Fast overlap test. Non-zero if any registers in common. int overlap( const RegMask &rm ) const { return # define BODY(I) (_A[I] & rm._A[I]) | FORALL_BODY # undef BODY 0 ; } // Special test for register pressure based splitting // UP means register only, Register plus stack, or stack only is DOWN bool is_UP() const; // Clear a register mask void Clear( ) { # define BODY(I) _A[I] = 0; FORALL_BODY # undef BODY } // Fill a register mask with 1's void Set_All( ) { # define BODY(I) _A[I] = -1; FORALL_BODY # undef BODY } // Insert register into mask void Insert( OptoReg::Name reg ) { assert( reg < CHUNK_SIZE, "" ); _A[reg>>_LogWordBits] |= (1<<(reg&(_WordBits-1))); } // Remove register from mask void Remove( OptoReg::Name reg ) { assert( reg < CHUNK_SIZE, "" ); _A[reg>>_LogWordBits] &= ~(1<<(reg&(_WordBits-1))); } // OR 'rm' into 'this' void OR( const RegMask &rm ) { # define BODY(I) this->_A[I] |= rm._A[I]; FORALL_BODY # undef BODY } // AND 'rm' into 'this' void AND( const RegMask &rm ) { # define BODY(I) this->_A[I] &= rm._A[I]; FORALL_BODY # undef BODY } // Subtract 'rm' from 'this' void SUBTRACT( const RegMask &rm ) { # define BODY(I) _A[I] &= ~rm._A[I]; FORALL_BODY # undef BODY } // Compute size of register mask: number of bits uint Size() const; #ifndef PRODUCT void print() const { dump(); } void dump(outputStream *st = tty) const; // Print a mask #endif static const RegMask Empty; // Common empty mask static bool can_represent(OptoReg::Name reg) { // NOTE: -1 in computation reflects the usage of the last // bit of the regmask as an infinite stack flag and // -7 is to keep mask aligned for largest value (VecY). return (int)reg < (int)(CHUNK_SIZE-1); } static bool can_represent_arg(OptoReg::Name reg) { // NOTE: -SlotsPerVecY in computation reflects the need // to keep mask aligned for largest value (VecY). return (int)reg < (int)(CHUNK_SIZE-SlotsPerVecY); } }; // Do not use this constant directly in client code! #undef RM_SIZE #endif // SHARE_VM_OPTO_REGMASK_HPP