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view src/share/vm/opto/regmask.cpp @ 10905:f57189b7648d
8257192: Integrate AArch64 JIT port into 8u
7009641: Don't fail VM when CodeCache is full
8073108: [AArch64] Use x86 and SPARC CPU instructions for GHASH acceleration
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space (AArch64 changes)
8131779: AARCH64: add Montgomery multiply intrinsic
8132875: AArch64: Fix error introduced into AArch64 CodeCache by commit for 8130309
8135018: AARCH64: Missing memory barriers for CMS collector
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
8148328: aarch64: redundant lsr instructions in stub code.
8148783: aarch64: SEGV running SpecJBB2013
8148948: aarch64: generate_copy_longs calls align() incorrectly
8149080: AArch64: Recognise disjoint array copy in stub code
8149365: aarch64: memory copy does not prefetch on backwards copy
8149907: aarch64: use load/store pair instructions in call_stub
8150038: aarch64: make use of CBZ and CBNZ when comparing narrow pointer with zero
8150045: arraycopy causes segfaults in SATB during garbage collection
8150082: aarch64: optimise small array copy
8150229: aarch64: pipeline class for several instructions is not set correctly
8150313: aarch64: optimise array copy using SIMD instructions
8150394: aarch64: add support for 8.1 LSE CAS instructions
8150652: Remove unused code in AArch64 back end
8151340: aarch64: prefetch the destination word for write prior to ldxr/stxr loops.
8151502: optimize pd_disjoint_words and pd_conjoint_words
8151775: aarch64: add support for 8.1 LSE atomic operations
8152537: aarch64: Make use of CBZ and CBNZ when comparing unsigned values with zero.
8152840: aarch64: improve _unsafe_arraycopy stub routine
8153172: aarch64: hotspot crashes after the 8.1 LSE patch is merged
8153713: aarch64: improve short array clearing using store pair
8153797: aarch64: Add Arrays.fill stub code
8154413: AArch64: Better byte behaviour
8154537: AArch64: some integer rotate instructions are never emitted
8154739: AArch64: TemplateTable::fast_xaccess loads in wrong mode
8155015: Aarch64: bad assert in spill generation code
8155100: AArch64: Relax alignment requirement for byte_map_base
8155612: Aarch64: vector nodes need to support misaligned offset
8155617: aarch64: ClearArray does not use DC ZVA
8155627: Enable SA on AArch64
8155653: TestVectorUnalignedOffset.java not pushed with 8155612
8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
8157841: aarch64: prefetch ignores cache line size
8157906: aarch64: some more integer rotate instructions are never emitted
8158913: aarch64: SEGV running Spark terasort
8159052: aarch64: optimise unaligned copies in pd_disjoint_words and pd_conjoint_words
8159063: aarch64: optimise unaligned array copy long
8160748: [AArch64] Inconsistent types for ideal_reg
8161072: AArch64: jtreg compiler/uncommontrap/TestDeoptOOM failure
8161190: AArch64: Fix overflow in immediate cmp instruction
8164113: AArch64: follow-up the fix for 8161598
8165673: AArch64: Fix JNI floating point argument handling
8167200: AArch64: Broken stack pointer adjustment in interpreter
8167421: AArch64: in one core system, fatal error: Illegal threadstate encountered
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
8168699: Validate special case invocations [AArch64 support]
8168888: Port 8160591: Improve internal array handling to AArch64.
8170100: AArch64: Crash in C1-compiled code accessing References
8170188: jtreg test compiler/types/TestMeetIncompatibleInterfaceArrays.java causes JVM crash
8170873: PPC64/aarch64: Poor StrictMath performance due to non-optimized compilation
8171537: aarch64: compiler/c1/Test6849574.java generates guarantee failure in C1
8172881: AArch64: assertion failure: the int pressure is incorrect
8173472: AArch64: C1 comparisons with null only use 32-bit instructions
8176100: [AArch64] [REDO][REDO] G1 Needs pre barrier on dereference of weak JNI handles
8177661: Correct ad rule output register types from iRegX to iRegXNoSp
8179954: AArch64: C1 and C2 volatile accesses are not sequentially consistent
8182581: aarch64: fix for crash caused by earlyret of compiled method
8183925: [AArch64] Decouple crash protection from watcher thread
8186325: AArch64: jtreg test hotspot/test/gc/g1/TestJNIWeakG1/TestJNIWeakG1.java SEGV
8187224: aarch64: some inconsistency between aarch64_ad.m4 and aarch64.ad
8189170: [AArch64] Add option to disable stack overflow checking in primordial thread for use with JNI_CreateJavaJVM
8193133: Assertion failure because 0xDEADDEAD can be in-heap
8195685: AArch64 port of 8174962: Better interface invocations
8195859: AArch64: vtableStubs gtest fails after 8174962
8196136: AArch64: Correct register use in patch for JDK-8194686
8196221: AArch64: Mistake in committed patch for JDK-8195859
8199712: [AArch64] Flight Recorder
8203481: Incorrect constraint for unextended_sp in frame:safe_for_sender
8203699: java/lang/invoke/SpecialInterfaceCall fails with SIGILL on aarch64
8205421: AARCH64: StubCodeMark should be placed after alignment
8206163: AArch64: incorrect code generation for StoreCM
8207345: Trampoline generation code reads from uninitialized memory
8207838: AArch64: Float registers incorrectly restored in JNI call
8209413: AArch64: NPE in clhsdb jstack command
8209414: [AArch64] method handle invocation does not respect JVMTI interp_only mode
8209415: Fix JVMTI test failure HS202
8209420: Track membars for volatile accesses so they can be properly optimized
8209835: Aarch64: elide barriers on all volatile operations
8210425: [AArch64] sharedRuntimeTrig/sharedRuntimeTrans compiled without optimization
8211064: [AArch64] Interpreter and c1 don't correctly handle jboolean results in native calls
8211233: MemBarNode::trailing_membar() and MemBarNode::leading_membar() need to handle dying subgraphs better
8213134: AArch64: vector shift failed with MaxVectorSize=8
8213419: [AArch64] C2 may hang in MulLNode::Ideal()/MulINode::Ideal() with gcc 8.2.1
8214857: "bad trailing membar" assert failure at memnode.cpp:3220
8215951: AArch64: jtreg test vmTestbase/nsk/jvmti/PopFrame/popframe005 segfaults
8215961: jdk/jfr/event/os/TestCPUInformation.java fails on AArch64
8216350: AArch64: monitor unlock fast path not called
8216989: CardTableBarrierSetAssembler::gen_write_ref_array_post_barrier() does not check for zero length on AARCH64
8217368: AArch64: C2 recursive stack locking optimisation not triggered
8218185: aarch64: missing LoadStore barrier in TemplateTable::putfield_or_static
8219011: Implement MacroAssembler::warn method on AArch64
8219635: aarch64: missing LoadStore barrier in TemplateTable::fast_storefield
8221220: AArch64: Add StoreStore membar explicitly for Volatile Writes in TemplateTable
8221658: aarch64: add necessary predicate for ubfx patterns
8224671: AArch64: mauve System.arraycopy test failure
8224828: aarch64: rflags is not correct after safepoint poll
8224851: AArch64: fix warnings and errors with Clang and GCC 8.3
8224880: AArch64: java/javac error with AllocatePrefetchDistance
8228400: Remove built-in AArch64 simulator
8228406: Superfluous change in chaitin.hpp
8228593: Revert explicit JDK 7 support additions
8228716: Revert InstanceKlass::print_on debug additions
8228718: Revert incorrect backport of JDK-8129757 to 8-aarch64
8228725: AArch64: Purge method call format support
8228747: Revert "unused" attribute from test_arraycopy_func
8228767: Revert ResourceMark additions
8228770: Revert development hsdis changes
8229123: Revert build fixes for aarch64/zero
8229124: Revert disassembler.cpp changes
8229145: Revert TemplateTable::bytecode() visibility change
8233839: aarch64: missing memory barrier in NewObjectArrayStub and NewTypeArrayStub
8237512: AArch64: aarch64TestHook leaks a BufferBlob
8246482: Build failures with +JFR -PCH
8247979: aarch64: missing side effect of killing flags for clearArray_reg_reg
8248219: aarch64: missing memory barrier in fast_storefield and fast_accessfield
Reviewed-by: shade, aph
author | andrew |
---|---|
date | Mon, 01 Feb 2021 03:48:36 +0000 |
parents | ddce0b7cee93 |
children | f79e943d15a7 |
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/* * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * */ #include "precompiled.hpp" #include "opto/compile.hpp" #include "opto/regmask.hpp" #if defined AD_MD_HPP # include AD_MD_HPP #elif defined TARGET_ARCH_MODEL_x86_32 # include "adfiles/ad_x86_32.hpp" #elif defined TARGET_ARCH_MODEL_x86_64 # include "adfiles/ad_x86_64.hpp" #elif defined TARGET_ARCH_MODEL_aarch64 # include "adfiles/ad_aarch64.hpp" #elif defined TARGET_ARCH_MODEL_sparc # include "adfiles/ad_sparc.hpp" #elif defined TARGET_ARCH_MODEL_zero # include "adfiles/ad_zero.hpp" #elif defined TARGET_ARCH_MODEL_ppc_64 # include "adfiles/ad_ppc_64.hpp" #endif #define RM_SIZE _RM_SIZE /* a constant private to the class RegMask */ //-------------Non-zero bit search methods used by RegMask--------------------- // Find lowest 1, or return 32 if empty int find_lowest_bit( uint32 mask ) { int n = 0; if( (mask & 0xffff) == 0 ) { mask >>= 16; n += 16; } if( (mask & 0xff) == 0 ) { mask >>= 8; n += 8; } if( (mask & 0xf) == 0 ) { mask >>= 4; n += 4; } if( (mask & 0x3) == 0 ) { mask >>= 2; n += 2; } if( (mask & 0x1) == 0 ) { mask >>= 1; n += 1; } if( mask == 0 ) { n = 32; } return n; } // Find highest 1, or return 32 if empty int find_hihghest_bit( uint32 mask ) { int n = 0; if( mask > 0xffff ) { mask >>= 16; n += 16; } if( mask > 0xff ) { mask >>= 8; n += 8; } if( mask > 0xf ) { mask >>= 4; n += 4; } if( mask > 0x3 ) { mask >>= 2; n += 2; } if( mask > 0x1 ) { mask >>= 1; n += 1; } if( mask == 0 ) { n = 32; } return n; } //------------------------------dump------------------------------------------- #ifndef PRODUCT void OptoReg::dump(int r, outputStream *st) { switch (r) { case Special: st->print("r---"); break; case Bad: st->print("rBAD"); break; default: if (r < _last_Mach_Reg) st->print("%s", Matcher::regName[r]); else st->print("rS%d",r); break; } } #endif //============================================================================= const RegMask RegMask::Empty( # define BODY(I) 0, FORALL_BODY # undef BODY 0 ); //============================================================================= bool RegMask::is_vector(uint ireg) { return (ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY); } int RegMask::num_registers(uint ireg) { switch(ireg) { case Op_VecY: return 8; case Op_VecX: return 4; case Op_VecD: case Op_RegD: case Op_RegL: #ifdef _LP64 case Op_RegP: #endif return 2; } // Op_VecS and the rest ideal registers. return 1; } //------------------------------find_first_pair-------------------------------- // Find the lowest-numbered register pair in the mask. Return the // HIGHEST register number in the pair, or BAD if no pairs. OptoReg::Name RegMask::find_first_pair() const { verify_pairs(); for( int i = 0; i < RM_SIZE; i++ ) { if( _A[i] ) { // Found some bits int bit = _A[i] & -_A[i]; // Extract low bit // Convert to bit number, return hi bit in pair return OptoReg::Name((i<<_LogWordBits)+find_lowest_bit(bit)+1); } } return OptoReg::Bad; } //------------------------------ClearToPairs----------------------------------- // Clear out partial bits; leave only bit pairs void RegMask::clear_to_pairs() { for( int i = 0; i < RM_SIZE; i++ ) { int bits = _A[i]; bits &= ((bits & 0x55555555)<<1); // 1 hi-bit set for each pair bits |= (bits>>1); // Smear 1 hi-bit into a pair _A[i] = bits; } verify_pairs(); } //------------------------------SmearToPairs----------------------------------- // Smear out partial bits; leave only bit pairs void RegMask::smear_to_pairs() { for( int i = 0; i < RM_SIZE; i++ ) { int bits = _A[i]; bits |= ((bits & 0x55555555)<<1); // Smear lo bit hi per pair bits |= ((bits & 0xAAAAAAAA)>>1); // Smear hi bit lo per pair _A[i] = bits; } verify_pairs(); } //------------------------------is_aligned_pairs------------------------------- bool RegMask::is_aligned_pairs() const { // Assert that the register mask contains only bit pairs. for( int i = 0; i < RM_SIZE; i++ ) { int bits = _A[i]; while( bits ) { // Check bits for pairing int bit = bits & -bits; // Extract low bit // Low bit is not odd means its mis-aligned. if( (bit & 0x55555555) == 0 ) return false; bits -= bit; // Remove bit from mask // Check for aligned adjacent bit if( (bits & (bit<<1)) == 0 ) return false; bits -= (bit<<1); // Remove other halve of pair } } return true; } //------------------------------is_bound1-------------------------------------- // Return TRUE if the mask contains a single bit int RegMask::is_bound1() const { if( is_AllStack() ) return false; int bit = -1; // Set to hold the one bit allowed for( int i = 0; i < RM_SIZE; i++ ) { if( _A[i] ) { // Found some bits if( bit != -1 ) return false; // Already had bits, so fail bit = _A[i] & -_A[i]; // Extract 1 bit from mask if( bit != _A[i] ) return false; // Found many bits, so fail } } // True for both the empty mask and for a single bit return true; } //------------------------------is_bound2-------------------------------------- // Return TRUE if the mask contains an adjacent pair of bits and no other bits. int RegMask::is_bound_pair() const { if( is_AllStack() ) return false; int bit = -1; // Set to hold the one bit allowed for( int i = 0; i < RM_SIZE; i++ ) { if( _A[i] ) { // Found some bits if( bit != -1 ) return false; // Already had bits, so fail bit = _A[i] & -(_A[i]); // Extract 1 bit from mask if( (bit << 1) != 0 ) { // Bit pair stays in same word? if( (bit | (bit<<1)) != _A[i] ) return false; // Require adjacent bit pair and no more bits } else { // Else its a split-pair case if( bit != _A[i] ) return false; // Found many bits, so fail i++; // Skip iteration forward if( i >= RM_SIZE || _A[i] != 1 ) return false; // Require 1 lo bit in next word } } } // True for both the empty mask and for a bit pair return true; } static int low_bits[3] = { 0x55555555, 0x11111111, 0x01010101 }; //------------------------------find_first_set--------------------------------- // Find the lowest-numbered register set in the mask. Return the // HIGHEST register number in the set, or BAD if no sets. // Works also for size 1. OptoReg::Name RegMask::find_first_set(const int size) const { verify_sets(size); for (int i = 0; i < RM_SIZE; i++) { if (_A[i]) { // Found some bits int bit = _A[i] & -_A[i]; // Extract low bit // Convert to bit number, return hi bit in pair return OptoReg::Name((i<<_LogWordBits)+find_lowest_bit(bit)+(size-1)); } } return OptoReg::Bad; } //------------------------------clear_to_sets---------------------------------- // Clear out partial bits; leave only aligned adjacent bit pairs void RegMask::clear_to_sets(const int size) { if (size == 1) return; assert(2 <= size && size <= 8, "update low bits table"); assert(is_power_of_2(size), "sanity"); int low_bits_mask = low_bits[size>>2]; for (int i = 0; i < RM_SIZE; i++) { int bits = _A[i]; int sets = (bits & low_bits_mask); for (int j = 1; j < size; j++) { sets = (bits & (sets<<1)); // filter bits which produce whole sets } sets |= (sets>>1); // Smear 1 hi-bit into a set if (size > 2) { sets |= (sets>>2); // Smear 2 hi-bits into a set if (size > 4) { sets |= (sets>>4); // Smear 4 hi-bits into a set } } _A[i] = sets; } verify_sets(size); } //------------------------------smear_to_sets---------------------------------- // Smear out partial bits to aligned adjacent bit sets void RegMask::smear_to_sets(const int size) { if (size == 1) return; assert(2 <= size && size <= 8, "update low bits table"); assert(is_power_of_2(size), "sanity"); int low_bits_mask = low_bits[size>>2]; for (int i = 0; i < RM_SIZE; i++) { int bits = _A[i]; int sets = 0; for (int j = 0; j < size; j++) { sets |= (bits & low_bits_mask); // collect partial bits bits = bits>>1; } sets |= (sets<<1); // Smear 1 lo-bit into a set if (size > 2) { sets |= (sets<<2); // Smear 2 lo-bits into a set if (size > 4) { sets |= (sets<<4); // Smear 4 lo-bits into a set } } _A[i] = sets; } verify_sets(size); } //------------------------------is_aligned_set-------------------------------- bool RegMask::is_aligned_sets(const int size) const { if (size == 1) return true; assert(2 <= size && size <= 8, "update low bits table"); assert(is_power_of_2(size), "sanity"); int low_bits_mask = low_bits[size>>2]; // Assert that the register mask contains only bit sets. for (int i = 0; i < RM_SIZE; i++) { int bits = _A[i]; while (bits) { // Check bits for pairing int bit = bits & -bits; // Extract low bit // Low bit is not odd means its mis-aligned. if ((bit & low_bits_mask) == 0) return false; // Do extra work since (bit << size) may overflow. int hi_bit = bit << (size-1); // high bit int set = hi_bit + ((hi_bit-1) & ~(bit-1)); // Check for aligned adjacent bits in this set if ((bits & set) != set) return false; bits -= set; // Remove this set } } return true; } //------------------------------is_bound_set----------------------------------- // Return TRUE if the mask contains one adjacent set of bits and no other bits. // Works also for size 1. int RegMask::is_bound_set(const int size) const { if( is_AllStack() ) return false; assert(1 <= size && size <= 8, "update low bits table"); int bit = -1; // Set to hold the one bit allowed for (int i = 0; i < RM_SIZE; i++) { if (_A[i] ) { // Found some bits if (bit != -1) return false; // Already had bits, so fail bit = _A[i] & -_A[i]; // Extract low bit from mask int hi_bit = bit << (size-1); // high bit if (hi_bit != 0) { // Bit set stays in same word? int set = hi_bit + ((hi_bit-1) & ~(bit-1)); if (set != _A[i]) return false; // Require adjacent bit set and no more bits } else { // Else its a split-set case if (((-1) & ~(bit-1)) != _A[i]) return false; // Found many bits, so fail i++; // Skip iteration forward and check high part // The lower 24 bits should be 0 since it is split case and size <= 8. int set = bit>>24; set = set & -set; // Remove sign extension. set = (((set << size) - 1) >> 8); if (i >= RM_SIZE || _A[i] != set) return false; // Require expected low bits in next word } } } // True for both the empty mask and for a bit set return true; } //------------------------------is_UP------------------------------------------ // UP means register only, Register plus stack, or stack only is DOWN bool RegMask::is_UP() const { // Quick common case check for DOWN (any stack slot is legal) if( is_AllStack() ) return false; // Slower check for any stack bits set (also DOWN) if( overlap(Matcher::STACK_ONLY_mask) ) return false; // Not DOWN, so must be UP return true; } //------------------------------Size------------------------------------------- // Compute size of register mask in bits uint RegMask::Size() const { extern uint8 bitsInByte[256]; uint sum = 0; for( int i = 0; i < RM_SIZE; i++ ) sum += bitsInByte[(_A[i]>>24) & 0xff] + bitsInByte[(_A[i]>>16) & 0xff] + bitsInByte[(_A[i]>> 8) & 0xff] + bitsInByte[ _A[i] & 0xff]; return sum; } #ifndef PRODUCT //------------------------------print------------------------------------------ void RegMask::dump(outputStream *st) const { st->print("["); RegMask rm = *this; // Structure copy into local temp OptoReg::Name start = rm.find_first_elem(); // Get a register if (OptoReg::is_valid(start)) { // Check for empty mask rm.Remove(start); // Yank from mask OptoReg::dump(start, st); // Print register OptoReg::Name last = start; // Now I have printed an initial register. // Print adjacent registers as "rX-rZ" instead of "rX,rY,rZ". // Begin looping over the remaining registers. while (1) { // OptoReg::Name reg = rm.find_first_elem(); // Get a register if (!OptoReg::is_valid(reg)) break; // Empty mask, end loop rm.Remove(reg); // Yank from mask if (last+1 == reg) { // See if they are adjacent // Adjacent registers just collect into long runs, no printing. last = reg; } else { // Ending some kind of run if (start == last) { // 1-register run; no special printing } else if (start+1 == last) { st->print(","); // 2-register run; print as "rX,rY" OptoReg::dump(last, st); } else { // Multi-register run; print as "rX-rZ" st->print("-"); OptoReg::dump(last, st); } st->print(","); // Seperate start of new run start = last = reg; // Start a new register run OptoReg::dump(start, st); // Print register } // End of if ending a register run or not } // End of while regmask not empty if (start == last) { // 1-register run; no special printing } else if (start+1 == last) { st->print(","); // 2-register run; print as "rX,rY" OptoReg::dump(last, st); } else { // Multi-register run; print as "rX-rZ" st->print("-"); OptoReg::dump(last, st); } if (rm.is_AllStack()) st->print("..."); } st->print("]"); } #endif