Mercurial > hg > icedtea8-forest > hotspot
view src/share/vm/c1/c1_FrameMap.hpp @ 10905:f57189b7648d
8257192: Integrate AArch64 JIT port into 8u
7009641: Don't fail VM when CodeCache is full
8073108: [AArch64] Use x86 and SPARC CPU instructions for GHASH acceleration
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space (AArch64 changes)
8131779: AARCH64: add Montgomery multiply intrinsic
8132875: AArch64: Fix error introduced into AArch64 CodeCache by commit for 8130309
8135018: AARCH64: Missing memory barriers for CMS collector
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
8148328: aarch64: redundant lsr instructions in stub code.
8148783: aarch64: SEGV running SpecJBB2013
8148948: aarch64: generate_copy_longs calls align() incorrectly
8149080: AArch64: Recognise disjoint array copy in stub code
8149365: aarch64: memory copy does not prefetch on backwards copy
8149907: aarch64: use load/store pair instructions in call_stub
8150038: aarch64: make use of CBZ and CBNZ when comparing narrow pointer with zero
8150045: arraycopy causes segfaults in SATB during garbage collection
8150082: aarch64: optimise small array copy
8150229: aarch64: pipeline class for several instructions is not set correctly
8150313: aarch64: optimise array copy using SIMD instructions
8150394: aarch64: add support for 8.1 LSE CAS instructions
8150652: Remove unused code in AArch64 back end
8151340: aarch64: prefetch the destination word for write prior to ldxr/stxr loops.
8151502: optimize pd_disjoint_words and pd_conjoint_words
8151775: aarch64: add support for 8.1 LSE atomic operations
8152537: aarch64: Make use of CBZ and CBNZ when comparing unsigned values with zero.
8152840: aarch64: improve _unsafe_arraycopy stub routine
8153172: aarch64: hotspot crashes after the 8.1 LSE patch is merged
8153713: aarch64: improve short array clearing using store pair
8153797: aarch64: Add Arrays.fill stub code
8154413: AArch64: Better byte behaviour
8154537: AArch64: some integer rotate instructions are never emitted
8154739: AArch64: TemplateTable::fast_xaccess loads in wrong mode
8155015: Aarch64: bad assert in spill generation code
8155100: AArch64: Relax alignment requirement for byte_map_base
8155612: Aarch64: vector nodes need to support misaligned offset
8155617: aarch64: ClearArray does not use DC ZVA
8155627: Enable SA on AArch64
8155653: TestVectorUnalignedOffset.java not pushed with 8155612
8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
8157841: aarch64: prefetch ignores cache line size
8157906: aarch64: some more integer rotate instructions are never emitted
8158913: aarch64: SEGV running Spark terasort
8159052: aarch64: optimise unaligned copies in pd_disjoint_words and pd_conjoint_words
8159063: aarch64: optimise unaligned array copy long
8160748: [AArch64] Inconsistent types for ideal_reg
8161072: AArch64: jtreg compiler/uncommontrap/TestDeoptOOM failure
8161190: AArch64: Fix overflow in immediate cmp instruction
8164113: AArch64: follow-up the fix for 8161598
8165673: AArch64: Fix JNI floating point argument handling
8167200: AArch64: Broken stack pointer adjustment in interpreter
8167421: AArch64: in one core system, fatal error: Illegal threadstate encountered
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
8168699: Validate special case invocations [AArch64 support]
8168888: Port 8160591: Improve internal array handling to AArch64.
8170100: AArch64: Crash in C1-compiled code accessing References
8170188: jtreg test compiler/types/TestMeetIncompatibleInterfaceArrays.java causes JVM crash
8170873: PPC64/aarch64: Poor StrictMath performance due to non-optimized compilation
8171537: aarch64: compiler/c1/Test6849574.java generates guarantee failure in C1
8172881: AArch64: assertion failure: the int pressure is incorrect
8173472: AArch64: C1 comparisons with null only use 32-bit instructions
8176100: [AArch64] [REDO][REDO] G1 Needs pre barrier on dereference of weak JNI handles
8177661: Correct ad rule output register types from iRegX to iRegXNoSp
8179954: AArch64: C1 and C2 volatile accesses are not sequentially consistent
8182581: aarch64: fix for crash caused by earlyret of compiled method
8183925: [AArch64] Decouple crash protection from watcher thread
8186325: AArch64: jtreg test hotspot/test/gc/g1/TestJNIWeakG1/TestJNIWeakG1.java SEGV
8187224: aarch64: some inconsistency between aarch64_ad.m4 and aarch64.ad
8189170: [AArch64] Add option to disable stack overflow checking in primordial thread for use with JNI_CreateJavaJVM
8193133: Assertion failure because 0xDEADDEAD can be in-heap
8195685: AArch64 port of 8174962: Better interface invocations
8195859: AArch64: vtableStubs gtest fails after 8174962
8196136: AArch64: Correct register use in patch for JDK-8194686
8196221: AArch64: Mistake in committed patch for JDK-8195859
8199712: [AArch64] Flight Recorder
8203481: Incorrect constraint for unextended_sp in frame:safe_for_sender
8203699: java/lang/invoke/SpecialInterfaceCall fails with SIGILL on aarch64
8205421: AARCH64: StubCodeMark should be placed after alignment
8206163: AArch64: incorrect code generation for StoreCM
8207345: Trampoline generation code reads from uninitialized memory
8207838: AArch64: Float registers incorrectly restored in JNI call
8209413: AArch64: NPE in clhsdb jstack command
8209414: [AArch64] method handle invocation does not respect JVMTI interp_only mode
8209415: Fix JVMTI test failure HS202
8209420: Track membars for volatile accesses so they can be properly optimized
8209835: Aarch64: elide barriers on all volatile operations
8210425: [AArch64] sharedRuntimeTrig/sharedRuntimeTrans compiled without optimization
8211064: [AArch64] Interpreter and c1 don't correctly handle jboolean results in native calls
8211233: MemBarNode::trailing_membar() and MemBarNode::leading_membar() need to handle dying subgraphs better
8213134: AArch64: vector shift failed with MaxVectorSize=8
8213419: [AArch64] C2 may hang in MulLNode::Ideal()/MulINode::Ideal() with gcc 8.2.1
8214857: "bad trailing membar" assert failure at memnode.cpp:3220
8215951: AArch64: jtreg test vmTestbase/nsk/jvmti/PopFrame/popframe005 segfaults
8215961: jdk/jfr/event/os/TestCPUInformation.java fails on AArch64
8216350: AArch64: monitor unlock fast path not called
8216989: CardTableBarrierSetAssembler::gen_write_ref_array_post_barrier() does not check for zero length on AARCH64
8217368: AArch64: C2 recursive stack locking optimisation not triggered
8218185: aarch64: missing LoadStore barrier in TemplateTable::putfield_or_static
8219011: Implement MacroAssembler::warn method on AArch64
8219635: aarch64: missing LoadStore barrier in TemplateTable::fast_storefield
8221220: AArch64: Add StoreStore membar explicitly for Volatile Writes in TemplateTable
8221658: aarch64: add necessary predicate for ubfx patterns
8224671: AArch64: mauve System.arraycopy test failure
8224828: aarch64: rflags is not correct after safepoint poll
8224851: AArch64: fix warnings and errors with Clang and GCC 8.3
8224880: AArch64: java/javac error with AllocatePrefetchDistance
8228400: Remove built-in AArch64 simulator
8228406: Superfluous change in chaitin.hpp
8228593: Revert explicit JDK 7 support additions
8228716: Revert InstanceKlass::print_on debug additions
8228718: Revert incorrect backport of JDK-8129757 to 8-aarch64
8228725: AArch64: Purge method call format support
8228747: Revert "unused" attribute from test_arraycopy_func
8228767: Revert ResourceMark additions
8228770: Revert development hsdis changes
8229123: Revert build fixes for aarch64/zero
8229124: Revert disassembler.cpp changes
8229145: Revert TemplateTable::bytecode() visibility change
8233839: aarch64: missing memory barrier in NewObjectArrayStub and NewTypeArrayStub
8237512: AArch64: aarch64TestHook leaks a BufferBlob
8246482: Build failures with +JFR -PCH
8247979: aarch64: missing side effect of killing flags for clearArray_reg_reg
8248219: aarch64: missing memory barrier in fast_storefield and fast_accessfield
Reviewed-by: shade, aph
author | andrew |
---|---|
date | Mon, 01 Feb 2021 03:48:36 +0000 |
parents | 39b41ab3366c |
children | f79e943d15a7 |
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/* * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * */ #ifndef SHARE_VM_C1_C1_FRAMEMAP_HPP #define SHARE_VM_C1_C1_FRAMEMAP_HPP #include "asm/assembler.hpp" #include "c1/c1_Defs.hpp" #include "c1/c1_LIR.hpp" #include "code/vmreg.hpp" #include "memory/allocation.hpp" #include "runtime/frame.hpp" #include "runtime/synchronizer.hpp" #include "utilities/globalDefinitions.hpp" class ciMethod; class CallingConvention; class BasicTypeArray; class BasicTypeList; //-------------------------------------------------------- // FrameMap //-------------------------------------------------------- // This class is responsible of mapping items (locals, monitors, spill // slots and registers to their frame location // // The monitors are specified by a consecutive index, although each monitor entry // occupies two words. The monitor_index is 0.._num_monitors // The spill index is similar to local index; it is in range 0..(open) // // The CPU registers are mapped using a fixed table; register with number 0 // is the most used one. // stack grow direction --> SP // +----------+---+----------+-------+------------------------+-----+ // |arguments | x | monitors | spill | reserved argument area | ABI | // +----------+---+----------+-------+------------------------+-----+ // // x = ABI area (SPARC) or return adress and link (i486) // ABI = ABI area (SPARC) or nothing (i486) class LIR_OprDesc; typedef LIR_OprDesc* LIR_Opr; class FrameMap : public CompilationResourceObj { public: enum { nof_cpu_regs = pd_nof_cpu_regs_frame_map, nof_fpu_regs = pd_nof_fpu_regs_frame_map, nof_cpu_regs_reg_alloc = pd_nof_cpu_regs_reg_alloc, nof_fpu_regs_reg_alloc = pd_nof_fpu_regs_reg_alloc, max_nof_caller_save_cpu_regs = pd_nof_caller_save_cpu_regs_frame_map, nof_caller_save_fpu_regs = pd_nof_caller_save_fpu_regs_frame_map, spill_slot_size_in_bytes = 4 }; #ifdef TARGET_ARCH_x86 # include "c1_FrameMap_x86.hpp" #endif #ifdef TARGET_ARCH_aarch64 # include "c1_FrameMap_aarch64.hpp" #endif #ifdef TARGET_ARCH_sparc # include "c1_FrameMap_sparc.hpp" #endif #ifdef TARGET_ARCH_arm # include "c1_FrameMap_arm.hpp" #endif #ifdef TARGET_ARCH_ppc # include "c1_FrameMap_ppc.hpp" #endif friend class LIR_OprDesc; private: static bool _init_done; static Register _cpu_rnr2reg [nof_cpu_regs]; static int _cpu_reg2rnr [nof_cpu_regs]; static LIR_Opr _caller_save_cpu_regs [max_nof_caller_save_cpu_regs]; static LIR_Opr _caller_save_fpu_regs [nof_caller_save_fpu_regs]; int _framesize; int _argcount; int _num_monitors; int _num_spills; int _reserved_argument_area_size; int _oop_map_arg_count; CallingConvention* _incoming_arguments; intArray* _argument_locations; void check_spill_index (int spill_index) const { assert(spill_index >= 0, "bad index"); } void check_monitor_index (int monitor_index) const { assert(monitor_index >= 0 && monitor_index < _num_monitors, "bad index"); } static Register cpu_rnr2reg (int rnr) { assert(_init_done, "tables not initialized"); debug_only(cpu_range_check(rnr);) return _cpu_rnr2reg[rnr]; } static int cpu_reg2rnr (Register reg) { assert(_init_done, "tables not initialized"); debug_only(cpu_range_check(reg->encoding());) return _cpu_reg2rnr[reg->encoding()]; } static void map_register(int rnr, Register reg) { debug_only(cpu_range_check(rnr);) debug_only(cpu_range_check(reg->encoding());) _cpu_rnr2reg[rnr] = reg; _cpu_reg2rnr[reg->encoding()] = rnr; } void update_reserved_argument_area_size (int size) { assert(size >= 0, "check"); _reserved_argument_area_size = MAX2(_reserved_argument_area_size, size); } protected: #ifndef PRODUCT static void cpu_range_check (int rnr) { assert(0 <= rnr && rnr < nof_cpu_regs, "cpu register number is too big"); } static void fpu_range_check (int rnr) { assert(0 <= rnr && rnr < nof_fpu_regs, "fpu register number is too big"); } #endif ByteSize sp_offset_for_monitor_base(const int idx) const; Address make_new_address(ByteSize sp_offset) const; ByteSize sp_offset_for_slot(const int idx) const; ByteSize sp_offset_for_double_slot(const int idx) const; ByteSize sp_offset_for_spill(const int idx) const; ByteSize sp_offset_for_monitor_lock(int monitor_index) const; ByteSize sp_offset_for_monitor_object(int monitor_index) const; VMReg sp_offset2vmreg(ByteSize offset) const; // platform dependent hook used to check that frame is properly // addressable on the platform. Used by sparc to verify that all // stack addresses are expressable in a simm13. bool validate_frame(); static LIR_Opr map_to_opr(BasicType type, VMRegPair* reg, bool incoming); public: // Opr representing the stack_pointer on this platform static LIR_Opr stack_pointer(); // JSR 292 static LIR_Opr method_handle_invoke_SP_save_opr(); static BasicTypeArray* signature_type_array_for(const ciMethod* method); // for outgoing calls, these also update the reserved area to // include space for arguments and any ABI area. CallingConvention* c_calling_convention(const BasicTypeArray* signature); CallingConvention* java_calling_convention(const BasicTypeArray* signature, bool outgoing); // deopt support ByteSize sp_offset_for_orig_pc() { return sp_offset_for_monitor_base(_num_monitors); } static LIR_Opr as_opr(Register r) { return LIR_OprFact::single_cpu(cpu_reg2rnr(r)); } static LIR_Opr as_oop_opr(Register r) { return LIR_OprFact::single_cpu_oop(cpu_reg2rnr(r)); } static LIR_Opr as_metadata_opr(Register r) { return LIR_OprFact::single_cpu_metadata(cpu_reg2rnr(r)); } static LIR_Opr as_address_opr(Register r) { return LIR_OprFact::single_cpu_address(cpu_reg2rnr(r)); } FrameMap(ciMethod* method, int monitors, int reserved_argument_area_size); bool finalize_frame(int nof_slots); int reserved_argument_area_size () const { return _reserved_argument_area_size; } int framesize () const { assert(_framesize != -1, "hasn't been calculated"); return _framesize; } ByteSize framesize_in_bytes () const { return in_ByteSize(framesize() * 4); } int num_monitors () const { return _num_monitors; } int num_spills () const { assert(_num_spills >= 0, "not set"); return _num_spills; } int argcount () const { assert(_argcount >= 0, "not set"); return _argcount; } int oop_map_arg_count() const { return _oop_map_arg_count; } CallingConvention* incoming_arguments() const { return _incoming_arguments; } // convenience routines Address address_for_slot(int index, int sp_adjust = 0) const { return make_new_address(sp_offset_for_slot(index) + in_ByteSize(sp_adjust)); } Address address_for_double_slot(int index, int sp_adjust = 0) const { return make_new_address(sp_offset_for_double_slot(index) + in_ByteSize(sp_adjust)); } Address address_for_monitor_lock(int monitor_index) const { return make_new_address(sp_offset_for_monitor_lock(monitor_index)); } Address address_for_monitor_object(int monitor_index) const { return make_new_address(sp_offset_for_monitor_object(monitor_index)); } // Creates Location describing desired slot and returns it via pointer // to Location object. Returns true if the stack frame offset was legal // (as defined by Location::legal_offset_in_bytes()), false otherwise. // Do not use the returned location if this returns false. bool location_for_sp_offset(ByteSize byte_offset_from_sp, Location::Type loc_type, Location* loc) const; bool location_for_monitor_lock (int monitor_index, Location* loc) const { return location_for_sp_offset(sp_offset_for_monitor_lock(monitor_index), Location::normal, loc); } bool location_for_monitor_object(int monitor_index, Location* loc) const { return location_for_sp_offset(sp_offset_for_monitor_object(monitor_index), Location::oop, loc); } bool locations_for_slot (int index, Location::Type loc_type, Location* loc, Location* second = NULL) const; VMReg slot_regname(int index) const { return sp_offset2vmreg(sp_offset_for_slot(index)); } VMReg monitor_object_regname(int monitor_index) const { return sp_offset2vmreg(sp_offset_for_monitor_object(monitor_index)); } VMReg regname(LIR_Opr opr) const; static LIR_Opr caller_save_cpu_reg_at(int i) { assert(i >= 0 && i < max_nof_caller_save_cpu_regs, "out of bounds"); return _caller_save_cpu_regs[i]; } static LIR_Opr caller_save_fpu_reg_at(int i) { assert(i >= 0 && i < nof_caller_save_fpu_regs, "out of bounds"); return _caller_save_fpu_regs[i]; } static void initialize(); }; // CallingConvention //-------------------------------------------------------- class CallingConvention: public ResourceObj { private: LIR_OprList* _args; int _reserved_stack_slots; public: CallingConvention (LIR_OprList* args, int reserved_stack_slots) : _args(args) , _reserved_stack_slots(reserved_stack_slots) {} LIR_OprList* args() { return _args; } LIR_Opr at(int i) const { return _args->at(i); } int length() const { return _args->length(); } // Indicates number of real frame slots used by arguments passed on stack. int reserved_stack_slots() const { return _reserved_stack_slots; } #ifndef PRODUCT void print () const { for (int i = 0; i < length(); i++) { at(i)->print(); } } #endif // PRODUCT }; #endif // SHARE_VM_C1_C1_FRAMEMAP_HPP