Mercurial > hg > icedtea8-forest > hotspot
view src/share/vm/asm/register.hpp @ 10905:f57189b7648d
8257192: Integrate AArch64 JIT port into 8u
7009641: Don't fail VM when CodeCache is full
8073108: [AArch64] Use x86 and SPARC CPU instructions for GHASH acceleration
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space (AArch64 changes)
8131779: AARCH64: add Montgomery multiply intrinsic
8132875: AArch64: Fix error introduced into AArch64 CodeCache by commit for 8130309
8135018: AARCH64: Missing memory barriers for CMS collector
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
8148328: aarch64: redundant lsr instructions in stub code.
8148783: aarch64: SEGV running SpecJBB2013
8148948: aarch64: generate_copy_longs calls align() incorrectly
8149080: AArch64: Recognise disjoint array copy in stub code
8149365: aarch64: memory copy does not prefetch on backwards copy
8149907: aarch64: use load/store pair instructions in call_stub
8150038: aarch64: make use of CBZ and CBNZ when comparing narrow pointer with zero
8150045: arraycopy causes segfaults in SATB during garbage collection
8150082: aarch64: optimise small array copy
8150229: aarch64: pipeline class for several instructions is not set correctly
8150313: aarch64: optimise array copy using SIMD instructions
8150394: aarch64: add support for 8.1 LSE CAS instructions
8150652: Remove unused code in AArch64 back end
8151340: aarch64: prefetch the destination word for write prior to ldxr/stxr loops.
8151502: optimize pd_disjoint_words and pd_conjoint_words
8151775: aarch64: add support for 8.1 LSE atomic operations
8152537: aarch64: Make use of CBZ and CBNZ when comparing unsigned values with zero.
8152840: aarch64: improve _unsafe_arraycopy stub routine
8153172: aarch64: hotspot crashes after the 8.1 LSE patch is merged
8153713: aarch64: improve short array clearing using store pair
8153797: aarch64: Add Arrays.fill stub code
8154413: AArch64: Better byte behaviour
8154537: AArch64: some integer rotate instructions are never emitted
8154739: AArch64: TemplateTable::fast_xaccess loads in wrong mode
8155015: Aarch64: bad assert in spill generation code
8155100: AArch64: Relax alignment requirement for byte_map_base
8155612: Aarch64: vector nodes need to support misaligned offset
8155617: aarch64: ClearArray does not use DC ZVA
8155627: Enable SA on AArch64
8155653: TestVectorUnalignedOffset.java not pushed with 8155612
8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
8157841: aarch64: prefetch ignores cache line size
8157906: aarch64: some more integer rotate instructions are never emitted
8158913: aarch64: SEGV running Spark terasort
8159052: aarch64: optimise unaligned copies in pd_disjoint_words and pd_conjoint_words
8159063: aarch64: optimise unaligned array copy long
8160748: [AArch64] Inconsistent types for ideal_reg
8161072: AArch64: jtreg compiler/uncommontrap/TestDeoptOOM failure
8161190: AArch64: Fix overflow in immediate cmp instruction
8164113: AArch64: follow-up the fix for 8161598
8165673: AArch64: Fix JNI floating point argument handling
8167200: AArch64: Broken stack pointer adjustment in interpreter
8167421: AArch64: in one core system, fatal error: Illegal threadstate encountered
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
8168699: Validate special case invocations [AArch64 support]
8168888: Port 8160591: Improve internal array handling to AArch64.
8170100: AArch64: Crash in C1-compiled code accessing References
8170188: jtreg test compiler/types/TestMeetIncompatibleInterfaceArrays.java causes JVM crash
8170873: PPC64/aarch64: Poor StrictMath performance due to non-optimized compilation
8171537: aarch64: compiler/c1/Test6849574.java generates guarantee failure in C1
8172881: AArch64: assertion failure: the int pressure is incorrect
8173472: AArch64: C1 comparisons with null only use 32-bit instructions
8176100: [AArch64] [REDO][REDO] G1 Needs pre barrier on dereference of weak JNI handles
8177661: Correct ad rule output register types from iRegX to iRegXNoSp
8179954: AArch64: C1 and C2 volatile accesses are not sequentially consistent
8182581: aarch64: fix for crash caused by earlyret of compiled method
8183925: [AArch64] Decouple crash protection from watcher thread
8186325: AArch64: jtreg test hotspot/test/gc/g1/TestJNIWeakG1/TestJNIWeakG1.java SEGV
8187224: aarch64: some inconsistency between aarch64_ad.m4 and aarch64.ad
8189170: [AArch64] Add option to disable stack overflow checking in primordial thread for use with JNI_CreateJavaJVM
8193133: Assertion failure because 0xDEADDEAD can be in-heap
8195685: AArch64 port of 8174962: Better interface invocations
8195859: AArch64: vtableStubs gtest fails after 8174962
8196136: AArch64: Correct register use in patch for JDK-8194686
8196221: AArch64: Mistake in committed patch for JDK-8195859
8199712: [AArch64] Flight Recorder
8203481: Incorrect constraint for unextended_sp in frame:safe_for_sender
8203699: java/lang/invoke/SpecialInterfaceCall fails with SIGILL on aarch64
8205421: AARCH64: StubCodeMark should be placed after alignment
8206163: AArch64: incorrect code generation for StoreCM
8207345: Trampoline generation code reads from uninitialized memory
8207838: AArch64: Float registers incorrectly restored in JNI call
8209413: AArch64: NPE in clhsdb jstack command
8209414: [AArch64] method handle invocation does not respect JVMTI interp_only mode
8209415: Fix JVMTI test failure HS202
8209420: Track membars for volatile accesses so they can be properly optimized
8209835: Aarch64: elide barriers on all volatile operations
8210425: [AArch64] sharedRuntimeTrig/sharedRuntimeTrans compiled without optimization
8211064: [AArch64] Interpreter and c1 don't correctly handle jboolean results in native calls
8211233: MemBarNode::trailing_membar() and MemBarNode::leading_membar() need to handle dying subgraphs better
8213134: AArch64: vector shift failed with MaxVectorSize=8
8213419: [AArch64] C2 may hang in MulLNode::Ideal()/MulINode::Ideal() with gcc 8.2.1
8214857: "bad trailing membar" assert failure at memnode.cpp:3220
8215951: AArch64: jtreg test vmTestbase/nsk/jvmti/PopFrame/popframe005 segfaults
8215961: jdk/jfr/event/os/TestCPUInformation.java fails on AArch64
8216350: AArch64: monitor unlock fast path not called
8216989: CardTableBarrierSetAssembler::gen_write_ref_array_post_barrier() does not check for zero length on AARCH64
8217368: AArch64: C2 recursive stack locking optimisation not triggered
8218185: aarch64: missing LoadStore barrier in TemplateTable::putfield_or_static
8219011: Implement MacroAssembler::warn method on AArch64
8219635: aarch64: missing LoadStore barrier in TemplateTable::fast_storefield
8221220: AArch64: Add StoreStore membar explicitly for Volatile Writes in TemplateTable
8221658: aarch64: add necessary predicate for ubfx patterns
8224671: AArch64: mauve System.arraycopy test failure
8224828: aarch64: rflags is not correct after safepoint poll
8224851: AArch64: fix warnings and errors with Clang and GCC 8.3
8224880: AArch64: java/javac error with AllocatePrefetchDistance
8228400: Remove built-in AArch64 simulator
8228406: Superfluous change in chaitin.hpp
8228593: Revert explicit JDK 7 support additions
8228716: Revert InstanceKlass::print_on debug additions
8228718: Revert incorrect backport of JDK-8129757 to 8-aarch64
8228725: AArch64: Purge method call format support
8228747: Revert "unused" attribute from test_arraycopy_func
8228767: Revert ResourceMark additions
8228770: Revert development hsdis changes
8229123: Revert build fixes for aarch64/zero
8229124: Revert disassembler.cpp changes
8229145: Revert TemplateTable::bytecode() visibility change
8233839: aarch64: missing memory barrier in NewObjectArrayStub and NewTypeArrayStub
8237512: AArch64: aarch64TestHook leaks a BufferBlob
8246482: Build failures with +JFR -PCH
8247979: aarch64: missing side effect of killing flags for clearArray_reg_reg
8248219: aarch64: missing memory barrier in fast_storefield and fast_accessfield
Reviewed-by: shade, aph
author | andrew |
---|---|
date | Mon, 01 Feb 2021 03:48:36 +0000 |
parents | 166d744df0de |
children | f79e943d15a7 |
line wrap: on
line source
/* * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * */ #ifndef SHARE_VM_ASM_REGISTER_HPP #define SHARE_VM_ASM_REGISTER_HPP #include "utilities/top.hpp" // Use AbstractRegister as shortcut class AbstractRegisterImpl; typedef AbstractRegisterImpl* AbstractRegister; // The super class for platform specific registers. Instead of using value objects, // registers are implemented as pointers. Subclassing is used so all registers can // use the debugging suport below. No virtual functions are used for efficiency. // They are canonicalized; i.e., registers are equal if their pointers are equal, // and vice versa. A concrete implementation may just map the register onto 'this'. class AbstractRegisterImpl { protected: int value() const { return (int)(intx)this; } }; // // Macros for use in defining Register instances. We'd like to be // able to simply define const instances of the RegisterImpl* for each // of the registers needed on a system in a header file. However many // compilers don't handle this very well and end up producing a // private definition in every file which includes the header file. // Along with the static constructors necessary for initialization it // can consume a significant amount of space in the result library. // // The following macros allow us to declare the instance in a .hpp and // produce an enumeration value which has the same number. Then in a // .cpp the the register instance can be defined using the enumeration // value. This avoids the use of static constructors and multiple // definitions per .cpp. In addition #defines for the register can be // produced so that the constant registers can be inlined. These // macros should not be used inside other macros, because you may get // multiple evaluations of the macros which can give bad results. // // Here are some example uses and expansions. Note that the macro // invocation is terminated with a ;. // // CONSTANT_REGISTER_DECLARATION(Register, G0, 0); // // extern const Register G0 ; // enum { G0_RegisterEnumValue = 0 } ; // // REGISTER_DECLARATION(Register, Gmethod, G5); // // extern const Register Gmethod ; // enum { Gmethod_RegisterEnumValue = G5_RegisterEnumValue } ; // // REGISTER_DEFINITION(Register, G0); // // const Register G0 = ( ( Register ) G0_RegisterEnumValue ) ; // #define AS_REGISTER(type,name) ((type)name##_##type##EnumValue) #define CONSTANT_REGISTER_DECLARATION(type, name, value) \ extern const type name; \ enum { name##_##type##EnumValue = (value) } #define REGISTER_DECLARATION(type, name, value) \ extern const type name; \ enum { name##_##type##EnumValue = value##_##type##EnumValue } #define REGISTER_DEFINITION(type, name) \ const type name = ((type)name##_##type##EnumValue) #ifdef TARGET_ARCH_x86 # include "register_x86.hpp" #endif #ifdef TARGET_ARCH_sparc # include "register_sparc.hpp" #endif #ifdef TARGET_ARCH_zero # include "register_zero.hpp" #endif #ifdef TARGET_ARCH_arm # include "register_arm.hpp" #endif #ifdef TARGET_ARCH_ppc # include "register_ppc.hpp" #endif #ifdef TARGET_ARCH_aarch64 # include "register_aarch64.hpp" #endif // Debugging support inline void assert_different_registers( AbstractRegister a, AbstractRegister b ) { assert( a != b, err_msg_res("registers must be different: a=" INTPTR_FORMAT ", b=" INTPTR_FORMAT "", p2i(a), p2i(b)) ); } inline void assert_different_registers( AbstractRegister a, AbstractRegister b, AbstractRegister c ) { assert( a != b && a != c && b != c, err_msg_res("registers must be different: a=" INTPTR_FORMAT ", b=" INTPTR_FORMAT ", c=" INTPTR_FORMAT "", p2i(a), p2i(b), p2i(c)) ); } inline void assert_different_registers( AbstractRegister a, AbstractRegister b, AbstractRegister c, AbstractRegister d ) { assert( a != b && a != c && a != d && b != c && b != d && c != d, err_msg_res("registers must be different: a=" INTPTR_FORMAT ", b=" INTPTR_FORMAT ", c=" INTPTR_FORMAT ", d=" INTPTR_FORMAT "", p2i(a), p2i(b), p2i(c), p2i(d)) ); } inline void assert_different_registers( AbstractRegister a, AbstractRegister b, AbstractRegister c, AbstractRegister d, AbstractRegister e ) { assert( a != b && a != c && a != d && a != e && b != c && b != d && b != e && c != d && c != e && d != e, err_msg_res("registers must be different: a=" INTPTR_FORMAT ", b=" INTPTR_FORMAT ", c=" INTPTR_FORMAT ", d=" INTPTR_FORMAT ", e=" INTPTR_FORMAT "", p2i(a), p2i(b), p2i(c), p2i(d), p2i(e)) ); } inline void assert_different_registers( AbstractRegister a, AbstractRegister b, AbstractRegister c, AbstractRegister d, AbstractRegister e, AbstractRegister f ) { assert( a != b && a != c && a != d && a != e && a != f && b != c && b != d && b != e && b != f && c != d && c != e && c != f && d != e && d != f && e != f, err_msg_res("registers must be different: a=" INTPTR_FORMAT ", b=" INTPTR_FORMAT ", c=" INTPTR_FORMAT ", d=" INTPTR_FORMAT ", e=" INTPTR_FORMAT ", f=" INTPTR_FORMAT "", p2i(a), p2i(b), p2i(c), p2i(d), p2i(e), p2i(f)) ); } inline void assert_different_registers( AbstractRegister a, AbstractRegister b, AbstractRegister c, AbstractRegister d, AbstractRegister e, AbstractRegister f, AbstractRegister g ) { assert( a != b && a != c && a != d && a != e && a != f && a != g && b != c && b != d && b != e && b != f && b != g && c != d && c != e && c != f && c != g && d != e && d != f && d != g && e != f && e != g && f != g, err_msg_res("registers must be different: a=" INTPTR_FORMAT ", b=" INTPTR_FORMAT ", c=" INTPTR_FORMAT ", d=" INTPTR_FORMAT ", e=" INTPTR_FORMAT ", f=" INTPTR_FORMAT ", g=" INTPTR_FORMAT "", p2i(a), p2i(b), p2i(c), p2i(d), p2i(e), p2i(f), p2i(g)) ); } inline void assert_different_registers( AbstractRegister a, AbstractRegister b, AbstractRegister c, AbstractRegister d, AbstractRegister e, AbstractRegister f, AbstractRegister g, AbstractRegister h ) { assert( a != b && a != c && a != d && a != e && a != f && a != g && a != h && b != c && b != d && b != e && b != f && b != g && b != h && c != d && c != e && c != f && c != g && c != h && d != e && d != f && d != g && d != h && e != f && e != g && e != h && f != g && f != h && g != h, err_msg_res("registers must be different: a=" INTPTR_FORMAT ", b=" INTPTR_FORMAT ", c=" INTPTR_FORMAT ", d=" INTPTR_FORMAT ", e=" INTPTR_FORMAT ", f=" INTPTR_FORMAT ", g=" INTPTR_FORMAT ", h=" INTPTR_FORMAT "", p2i(a), p2i(b), p2i(c), p2i(d), p2i(e), p2i(f), p2i(g), p2i(h)) ); } inline void assert_different_registers( AbstractRegister a, AbstractRegister b, AbstractRegister c, AbstractRegister d, AbstractRegister e, AbstractRegister f, AbstractRegister g, AbstractRegister h, AbstractRegister i ) { assert( a != b && a != c && a != d && a != e && a != f && a != g && a != h && a != i && b != c && b != d && b != e && b != f && b != g && b != h && b != i && c != d && c != e && c != f && c != g && c != h && c != i && d != e && d != f && d != g && d != h && d != i && e != f && e != g && e != h && e != i && f != g && f != h && f != i && g != h && g != i && h != i, err_msg_res("registers must be different: a=" INTPTR_FORMAT ", b=" INTPTR_FORMAT ", c=" INTPTR_FORMAT ", d=" INTPTR_FORMAT ", e=" INTPTR_FORMAT ", f=" INTPTR_FORMAT ", g=" INTPTR_FORMAT ", h=" INTPTR_FORMAT ", i=" INTPTR_FORMAT "", p2i(a), p2i(b), p2i(c), p2i(d), p2i(e), p2i(f), p2i(g), p2i(h), p2i(i)) ); } inline void assert_different_registers( AbstractRegister a, AbstractRegister b, AbstractRegister c, AbstractRegister d, AbstractRegister e, AbstractRegister f, AbstractRegister g, AbstractRegister h, AbstractRegister i, AbstractRegister j ) { assert( a != b && a != c && a != d && a != e && a != f && a != g && a != h && a != i && a != j && b != c && b != d && b != e && b != f && b != g && b != h && b != i && b != j && c != d && c != e && c != f && c != g && c != h && c != i && c != j && d != e && d != f && d != g && d != h && d != i && d != j && e != f && e != g && e != h && e != i && e != j && f != g && f != h && f != i && f != j && g != h && g != i && g != j && h != i && h != j && i != j, err_msg_res("registers must be different: a=" INTPTR_FORMAT ", b=" INTPTR_FORMAT ", c=" INTPTR_FORMAT ", d=" INTPTR_FORMAT ", e=" INTPTR_FORMAT ", f=" INTPTR_FORMAT ", g=" INTPTR_FORMAT ", h=" INTPTR_FORMAT ", i=" INTPTR_FORMAT ", j=" INTPTR_FORMAT "", p2i(a), p2i(b), p2i(c), p2i(d), p2i(e), p2i(f), p2i(g), p2i(h), p2i(i), p2i(j)) ); } inline void assert_different_registers( AbstractRegister a, AbstractRegister b, AbstractRegister c, AbstractRegister d, AbstractRegister e, AbstractRegister f, AbstractRegister g, AbstractRegister h, AbstractRegister i, AbstractRegister j, AbstractRegister k ) { assert( a != b && a != c && a != d && a != e && a != f && a != g && a != h && a != i && a != j && a !=k && b != c && b != d && b != e && b != f && b != g && b != h && b != i && b != j && b !=k && c != d && c != e && c != f && c != g && c != h && c != i && c != j && c !=k && d != e && d != f && d != g && d != h && d != i && d != j && d !=k && e != f && e != g && e != h && e != i && e != j && e !=k && f != g && f != h && f != i && f != j && f !=k && g != h && g != i && g != j && g !=k && h != i && h != j && h !=k && i != j && i !=k && j !=k, err_msg_res("registers must be different: a=" INTPTR_FORMAT ", b=" INTPTR_FORMAT ", c=" INTPTR_FORMAT ", d=" INTPTR_FORMAT ", e=" INTPTR_FORMAT ", f=" INTPTR_FORMAT ", g=" INTPTR_FORMAT ", h=" INTPTR_FORMAT ", i=" INTPTR_FORMAT ", j=" INTPTR_FORMAT ", k=" INTPTR_FORMAT "", p2i(a), p2i(b), p2i(c), p2i(d), p2i(e), p2i(f), p2i(g), p2i(h), p2i(i), p2i(j), p2i(k)) ); } inline void assert_different_registers( AbstractRegister a, AbstractRegister b, AbstractRegister c, AbstractRegister d, AbstractRegister e, AbstractRegister f, AbstractRegister g, AbstractRegister h, AbstractRegister i, AbstractRegister j, AbstractRegister k, AbstractRegister l ) { assert( a != b && a != c && a != d && a != e && a != f && a != g && a != h && a != i && a != j && a !=k && a !=l && b != c && b != d && b != e && b != f && b != g && b != h && b != i && b != j && b !=k && b !=l && c != d && c != e && c != f && c != g && c != h && c != i && c != j && c !=k && c !=l && d != e && d != f && d != g && d != h && d != i && d != j && d !=k && d !=l && e != f && e != g && e != h && e != i && e != j && e !=k && e !=l && f != g && f != h && f != i && f != j && f !=k && f !=l && g != h && g != i && g != j && g !=k && g !=l && h != i && h != j && h !=k && h !=l && i != j && i !=k && i !=l && j !=k && j !=l && k !=l, err_msg_res("registers must be different: a=" INTPTR_FORMAT ", b=" INTPTR_FORMAT ", c=" INTPTR_FORMAT ", d=" INTPTR_FORMAT ", e=" INTPTR_FORMAT ", f=" INTPTR_FORMAT ", g=" INTPTR_FORMAT ", h=" INTPTR_FORMAT ", i=" INTPTR_FORMAT ", j=" INTPTR_FORMAT ", k=" INTPTR_FORMAT ", l=" INTPTR_FORMAT "", p2i(a), p2i(b), p2i(c), p2i(d), p2i(e), p2i(f), p2i(g), p2i(h), p2i(i), p2i(j), p2i(k), p2i(l)) ); } #endif // SHARE_VM_ASM_REGISTER_HPP