Mercurial > hg > icedtea8-forest > hotspot
view src/cpu/aarch64/vm/register_aarch64.hpp @ 10905:f57189b7648d
8257192: Integrate AArch64 JIT port into 8u
7009641: Don't fail VM when CodeCache is full
8073108: [AArch64] Use x86 and SPARC CPU instructions for GHASH acceleration
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space (AArch64 changes)
8131779: AARCH64: add Montgomery multiply intrinsic
8132875: AArch64: Fix error introduced into AArch64 CodeCache by commit for 8130309
8135018: AARCH64: Missing memory barriers for CMS collector
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
8148328: aarch64: redundant lsr instructions in stub code.
8148783: aarch64: SEGV running SpecJBB2013
8148948: aarch64: generate_copy_longs calls align() incorrectly
8149080: AArch64: Recognise disjoint array copy in stub code
8149365: aarch64: memory copy does not prefetch on backwards copy
8149907: aarch64: use load/store pair instructions in call_stub
8150038: aarch64: make use of CBZ and CBNZ when comparing narrow pointer with zero
8150045: arraycopy causes segfaults in SATB during garbage collection
8150082: aarch64: optimise small array copy
8150229: aarch64: pipeline class for several instructions is not set correctly
8150313: aarch64: optimise array copy using SIMD instructions
8150394: aarch64: add support for 8.1 LSE CAS instructions
8150652: Remove unused code in AArch64 back end
8151340: aarch64: prefetch the destination word for write prior to ldxr/stxr loops.
8151502: optimize pd_disjoint_words and pd_conjoint_words
8151775: aarch64: add support for 8.1 LSE atomic operations
8152537: aarch64: Make use of CBZ and CBNZ when comparing unsigned values with zero.
8152840: aarch64: improve _unsafe_arraycopy stub routine
8153172: aarch64: hotspot crashes after the 8.1 LSE patch is merged
8153713: aarch64: improve short array clearing using store pair
8153797: aarch64: Add Arrays.fill stub code
8154413: AArch64: Better byte behaviour
8154537: AArch64: some integer rotate instructions are never emitted
8154739: AArch64: TemplateTable::fast_xaccess loads in wrong mode
8155015: Aarch64: bad assert in spill generation code
8155100: AArch64: Relax alignment requirement for byte_map_base
8155612: Aarch64: vector nodes need to support misaligned offset
8155617: aarch64: ClearArray does not use DC ZVA
8155627: Enable SA on AArch64
8155653: TestVectorUnalignedOffset.java not pushed with 8155612
8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
8157841: aarch64: prefetch ignores cache line size
8157906: aarch64: some more integer rotate instructions are never emitted
8158913: aarch64: SEGV running Spark terasort
8159052: aarch64: optimise unaligned copies in pd_disjoint_words and pd_conjoint_words
8159063: aarch64: optimise unaligned array copy long
8160748: [AArch64] Inconsistent types for ideal_reg
8161072: AArch64: jtreg compiler/uncommontrap/TestDeoptOOM failure
8161190: AArch64: Fix overflow in immediate cmp instruction
8164113: AArch64: follow-up the fix for 8161598
8165673: AArch64: Fix JNI floating point argument handling
8167200: AArch64: Broken stack pointer adjustment in interpreter
8167421: AArch64: in one core system, fatal error: Illegal threadstate encountered
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
8168699: Validate special case invocations [AArch64 support]
8168888: Port 8160591: Improve internal array handling to AArch64.
8170100: AArch64: Crash in C1-compiled code accessing References
8170188: jtreg test compiler/types/TestMeetIncompatibleInterfaceArrays.java causes JVM crash
8170873: PPC64/aarch64: Poor StrictMath performance due to non-optimized compilation
8171537: aarch64: compiler/c1/Test6849574.java generates guarantee failure in C1
8172881: AArch64: assertion failure: the int pressure is incorrect
8173472: AArch64: C1 comparisons with null only use 32-bit instructions
8176100: [AArch64] [REDO][REDO] G1 Needs pre barrier on dereference of weak JNI handles
8177661: Correct ad rule output register types from iRegX to iRegXNoSp
8179954: AArch64: C1 and C2 volatile accesses are not sequentially consistent
8182581: aarch64: fix for crash caused by earlyret of compiled method
8183925: [AArch64] Decouple crash protection from watcher thread
8186325: AArch64: jtreg test hotspot/test/gc/g1/TestJNIWeakG1/TestJNIWeakG1.java SEGV
8187224: aarch64: some inconsistency between aarch64_ad.m4 and aarch64.ad
8189170: [AArch64] Add option to disable stack overflow checking in primordial thread for use with JNI_CreateJavaJVM
8193133: Assertion failure because 0xDEADDEAD can be in-heap
8195685: AArch64 port of 8174962: Better interface invocations
8195859: AArch64: vtableStubs gtest fails after 8174962
8196136: AArch64: Correct register use in patch for JDK-8194686
8196221: AArch64: Mistake in committed patch for JDK-8195859
8199712: [AArch64] Flight Recorder
8203481: Incorrect constraint for unextended_sp in frame:safe_for_sender
8203699: java/lang/invoke/SpecialInterfaceCall fails with SIGILL on aarch64
8205421: AARCH64: StubCodeMark should be placed after alignment
8206163: AArch64: incorrect code generation for StoreCM
8207345: Trampoline generation code reads from uninitialized memory
8207838: AArch64: Float registers incorrectly restored in JNI call
8209413: AArch64: NPE in clhsdb jstack command
8209414: [AArch64] method handle invocation does not respect JVMTI interp_only mode
8209415: Fix JVMTI test failure HS202
8209420: Track membars for volatile accesses so they can be properly optimized
8209835: Aarch64: elide barriers on all volatile operations
8210425: [AArch64] sharedRuntimeTrig/sharedRuntimeTrans compiled without optimization
8211064: [AArch64] Interpreter and c1 don't correctly handle jboolean results in native calls
8211233: MemBarNode::trailing_membar() and MemBarNode::leading_membar() need to handle dying subgraphs better
8213134: AArch64: vector shift failed with MaxVectorSize=8
8213419: [AArch64] C2 may hang in MulLNode::Ideal()/MulINode::Ideal() with gcc 8.2.1
8214857: "bad trailing membar" assert failure at memnode.cpp:3220
8215951: AArch64: jtreg test vmTestbase/nsk/jvmti/PopFrame/popframe005 segfaults
8215961: jdk/jfr/event/os/TestCPUInformation.java fails on AArch64
8216350: AArch64: monitor unlock fast path not called
8216989: CardTableBarrierSetAssembler::gen_write_ref_array_post_barrier() does not check for zero length on AARCH64
8217368: AArch64: C2 recursive stack locking optimisation not triggered
8218185: aarch64: missing LoadStore barrier in TemplateTable::putfield_or_static
8219011: Implement MacroAssembler::warn method on AArch64
8219635: aarch64: missing LoadStore barrier in TemplateTable::fast_storefield
8221220: AArch64: Add StoreStore membar explicitly for Volatile Writes in TemplateTable
8221658: aarch64: add necessary predicate for ubfx patterns
8224671: AArch64: mauve System.arraycopy test failure
8224828: aarch64: rflags is not correct after safepoint poll
8224851: AArch64: fix warnings and errors with Clang and GCC 8.3
8224880: AArch64: java/javac error with AllocatePrefetchDistance
8228400: Remove built-in AArch64 simulator
8228406: Superfluous change in chaitin.hpp
8228593: Revert explicit JDK 7 support additions
8228716: Revert InstanceKlass::print_on debug additions
8228718: Revert incorrect backport of JDK-8129757 to 8-aarch64
8228725: AArch64: Purge method call format support
8228747: Revert "unused" attribute from test_arraycopy_func
8228767: Revert ResourceMark additions
8228770: Revert development hsdis changes
8229123: Revert build fixes for aarch64/zero
8229124: Revert disassembler.cpp changes
8229145: Revert TemplateTable::bytecode() visibility change
8233839: aarch64: missing memory barrier in NewObjectArrayStub and NewTypeArrayStub
8237512: AArch64: aarch64TestHook leaks a BufferBlob
8246482: Build failures with +JFR -PCH
8247979: aarch64: missing side effect of killing flags for clearArray_reg_reg
8248219: aarch64: missing memory barrier in fast_storefield and fast_accessfield
Reviewed-by: shade, aph
author | andrew |
---|---|
date | Mon, 01 Feb 2021 03:48:36 +0000 |
parents | |
children | f79e943d15a7 |
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/* * Copyright (c) 2013, Red Hat Inc. * Copyright (c) 2000, 2010, Oracle and/or its affiliates. * All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * */ #ifndef CPU_AARCH64_VM_REGISTER_AARCH64_HPP #define CPU_AARCH64_VM_REGISTER_AARCH64_HPP #include "asm/register.hpp" #include "vm_version_aarch64.hpp" class VMRegImpl; typedef VMRegImpl* VMReg; // Use Register as shortcut class RegisterImpl; typedef RegisterImpl* Register; inline Register as_Register(int encoding) { return (Register)(intptr_t) encoding; } class RegisterImpl: public AbstractRegisterImpl { public: enum { number_of_registers = 32, number_of_byte_registers = 32 }; // derived registers, offsets, and addresses Register successor() const { return as_Register(encoding() + 1); } // construction inline friend Register as_Register(int encoding); VMReg as_VMReg(); // accessors int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } bool has_byte_register() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_byte_registers; } const char* name() const; int encoding_nocheck() const { return (intptr_t)this; } // Return the bit which represents this register. This is intended // to be ORed into a bitmask: for usage see class RegSet below. unsigned long bit(bool should_set = true) const { return should_set ? 1 << encoding() : 0; } }; // The integer registers of the aarch64 architecture CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1)); CONSTANT_REGISTER_DECLARATION(Register, r0, (0)); CONSTANT_REGISTER_DECLARATION(Register, r1, (1)); CONSTANT_REGISTER_DECLARATION(Register, r2, (2)); CONSTANT_REGISTER_DECLARATION(Register, r3, (3)); CONSTANT_REGISTER_DECLARATION(Register, r4, (4)); CONSTANT_REGISTER_DECLARATION(Register, r5, (5)); CONSTANT_REGISTER_DECLARATION(Register, r6, (6)); CONSTANT_REGISTER_DECLARATION(Register, r7, (7)); CONSTANT_REGISTER_DECLARATION(Register, r8, (8)); CONSTANT_REGISTER_DECLARATION(Register, r9, (9)); CONSTANT_REGISTER_DECLARATION(Register, r10, (10)); CONSTANT_REGISTER_DECLARATION(Register, r11, (11)); CONSTANT_REGISTER_DECLARATION(Register, r12, (12)); CONSTANT_REGISTER_DECLARATION(Register, r13, (13)); CONSTANT_REGISTER_DECLARATION(Register, r14, (14)); CONSTANT_REGISTER_DECLARATION(Register, r15, (15)); CONSTANT_REGISTER_DECLARATION(Register, r16, (16)); CONSTANT_REGISTER_DECLARATION(Register, r17, (17)); CONSTANT_REGISTER_DECLARATION(Register, r18, (18)); CONSTANT_REGISTER_DECLARATION(Register, r19, (19)); CONSTANT_REGISTER_DECLARATION(Register, r20, (20)); CONSTANT_REGISTER_DECLARATION(Register, r21, (21)); CONSTANT_REGISTER_DECLARATION(Register, r22, (22)); CONSTANT_REGISTER_DECLARATION(Register, r23, (23)); CONSTANT_REGISTER_DECLARATION(Register, r24, (24)); CONSTANT_REGISTER_DECLARATION(Register, r25, (25)); CONSTANT_REGISTER_DECLARATION(Register, r26, (26)); CONSTANT_REGISTER_DECLARATION(Register, r27, (27)); CONSTANT_REGISTER_DECLARATION(Register, r28, (28)); CONSTANT_REGISTER_DECLARATION(Register, r29, (29)); CONSTANT_REGISTER_DECLARATION(Register, r30, (30)); CONSTANT_REGISTER_DECLARATION(Register, r31_sp, (31)); CONSTANT_REGISTER_DECLARATION(Register, zr, (32)); CONSTANT_REGISTER_DECLARATION(Register, sp, (33)); // Used as a filler in instructions where a register field is unused. const Register dummy_reg = r31_sp; // Use FloatRegister as shortcut class FloatRegisterImpl; typedef FloatRegisterImpl* FloatRegister; inline FloatRegister as_FloatRegister(int encoding) { return (FloatRegister)(intptr_t) encoding; } // The implementation of floating point registers for the architecture class FloatRegisterImpl: public AbstractRegisterImpl { public: enum { number_of_registers = 32 }; // construction inline friend FloatRegister as_FloatRegister(int encoding); VMReg as_VMReg(); // derived registers, offsets, and addresses FloatRegister successor() const { return as_FloatRegister(encoding() + 1); } // accessors int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } int encoding_nocheck() const { return (intptr_t)this; } bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } const char* name() const; }; // The float registers of the AARCH64 architecture CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v0 , ( 0)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v1 , ( 1)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v2 , ( 2)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v3 , ( 3)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v4 , ( 4)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v5 , ( 5)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v6 , ( 6)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v7 , ( 7)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v8 , ( 8)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v9 , ( 9)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v10 , (10)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v11 , (11)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v12 , (12)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v13 , (13)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v14 , (14)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v15 , (15)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v16 , (16)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v17 , (17)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v18 , (18)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v19 , (19)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v20 , (20)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v21 , (21)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v22 , (22)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v23 , (23)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v24 , (24)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v25 , (25)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v26 , (26)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v27 , (27)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v28 , (28)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v29 , (29)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v30 , (30)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v31 , (31)); // Need to know the total number of registers of all sorts for SharedInfo. // Define a class that exports it. class ConcreteRegisterImpl : public AbstractRegisterImpl { public: enum { // A big enough number for C2: all the registers plus flags // This number must be large enough to cover REG_COUNT (defined by c2) registers. // There is no requirement that any ordering here matches any ordering c2 gives // it's optoregs. number_of_registers = (2 * RegisterImpl::number_of_registers + 4 * FloatRegisterImpl::number_of_registers + 1) // flags }; // added to make it compile static const int max_gpr; static const int max_fpr; }; // A set of registers class RegSet { uint32_t _bitset; RegSet(uint32_t bitset) : _bitset(bitset) { } public: RegSet() : _bitset(0) { } RegSet(Register r1) : _bitset(r1->bit()) { } RegSet operator+(const RegSet aSet) const { RegSet result(_bitset | aSet._bitset); return result; } RegSet operator-(const RegSet aSet) const { RegSet result(_bitset & ~aSet._bitset); return result; } RegSet &operator+=(const RegSet aSet) { *this = *this + aSet; return *this; } static RegSet of(Register r1) { return RegSet(r1); } static RegSet of(Register r1, Register r2) { return of(r1) + r2; } static RegSet of(Register r1, Register r2, Register r3) { return of(r1, r2) + r3; } static RegSet of(Register r1, Register r2, Register r3, Register r4) { return of(r1, r2, r3) + r4; } static RegSet range(Register start, Register end) { uint32_t bits = ~0; bits <<= start->encoding(); bits <<= 31 - end->encoding(); bits >>= 31 - end->encoding(); return RegSet(bits); } uint32_t bits() const { return _bitset; } }; #endif // CPU_AARCH64_VM_REGISTER_AARCH64_HPP