Mercurial > hg > icedtea8-forest > hotspot
view src/cpu/aarch64/vm/nativeInst_aarch64.hpp @ 10905:f57189b7648d
8257192: Integrate AArch64 JIT port into 8u
7009641: Don't fail VM when CodeCache is full
8073108: [AArch64] Use x86 and SPARC CPU instructions for GHASH acceleration
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space (AArch64 changes)
8131779: AARCH64: add Montgomery multiply intrinsic
8132875: AArch64: Fix error introduced into AArch64 CodeCache by commit for 8130309
8135018: AARCH64: Missing memory barriers for CMS collector
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
8148328: aarch64: redundant lsr instructions in stub code.
8148783: aarch64: SEGV running SpecJBB2013
8148948: aarch64: generate_copy_longs calls align() incorrectly
8149080: AArch64: Recognise disjoint array copy in stub code
8149365: aarch64: memory copy does not prefetch on backwards copy
8149907: aarch64: use load/store pair instructions in call_stub
8150038: aarch64: make use of CBZ and CBNZ when comparing narrow pointer with zero
8150045: arraycopy causes segfaults in SATB during garbage collection
8150082: aarch64: optimise small array copy
8150229: aarch64: pipeline class for several instructions is not set correctly
8150313: aarch64: optimise array copy using SIMD instructions
8150394: aarch64: add support for 8.1 LSE CAS instructions
8150652: Remove unused code in AArch64 back end
8151340: aarch64: prefetch the destination word for write prior to ldxr/stxr loops.
8151502: optimize pd_disjoint_words and pd_conjoint_words
8151775: aarch64: add support for 8.1 LSE atomic operations
8152537: aarch64: Make use of CBZ and CBNZ when comparing unsigned values with zero.
8152840: aarch64: improve _unsafe_arraycopy stub routine
8153172: aarch64: hotspot crashes after the 8.1 LSE patch is merged
8153713: aarch64: improve short array clearing using store pair
8153797: aarch64: Add Arrays.fill stub code
8154413: AArch64: Better byte behaviour
8154537: AArch64: some integer rotate instructions are never emitted
8154739: AArch64: TemplateTable::fast_xaccess loads in wrong mode
8155015: Aarch64: bad assert in spill generation code
8155100: AArch64: Relax alignment requirement for byte_map_base
8155612: Aarch64: vector nodes need to support misaligned offset
8155617: aarch64: ClearArray does not use DC ZVA
8155627: Enable SA on AArch64
8155653: TestVectorUnalignedOffset.java not pushed with 8155612
8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
8157841: aarch64: prefetch ignores cache line size
8157906: aarch64: some more integer rotate instructions are never emitted
8158913: aarch64: SEGV running Spark terasort
8159052: aarch64: optimise unaligned copies in pd_disjoint_words and pd_conjoint_words
8159063: aarch64: optimise unaligned array copy long
8160748: [AArch64] Inconsistent types for ideal_reg
8161072: AArch64: jtreg compiler/uncommontrap/TestDeoptOOM failure
8161190: AArch64: Fix overflow in immediate cmp instruction
8164113: AArch64: follow-up the fix for 8161598
8165673: AArch64: Fix JNI floating point argument handling
8167200: AArch64: Broken stack pointer adjustment in interpreter
8167421: AArch64: in one core system, fatal error: Illegal threadstate encountered
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
8168699: Validate special case invocations [AArch64 support]
8168888: Port 8160591: Improve internal array handling to AArch64.
8170100: AArch64: Crash in C1-compiled code accessing References
8170188: jtreg test compiler/types/TestMeetIncompatibleInterfaceArrays.java causes JVM crash
8170873: PPC64/aarch64: Poor StrictMath performance due to non-optimized compilation
8171537: aarch64: compiler/c1/Test6849574.java generates guarantee failure in C1
8172881: AArch64: assertion failure: the int pressure is incorrect
8173472: AArch64: C1 comparisons with null only use 32-bit instructions
8176100: [AArch64] [REDO][REDO] G1 Needs pre barrier on dereference of weak JNI handles
8177661: Correct ad rule output register types from iRegX to iRegXNoSp
8179954: AArch64: C1 and C2 volatile accesses are not sequentially consistent
8182581: aarch64: fix for crash caused by earlyret of compiled method
8183925: [AArch64] Decouple crash protection from watcher thread
8186325: AArch64: jtreg test hotspot/test/gc/g1/TestJNIWeakG1/TestJNIWeakG1.java SEGV
8187224: aarch64: some inconsistency between aarch64_ad.m4 and aarch64.ad
8189170: [AArch64] Add option to disable stack overflow checking in primordial thread for use with JNI_CreateJavaJVM
8193133: Assertion failure because 0xDEADDEAD can be in-heap
8195685: AArch64 port of 8174962: Better interface invocations
8195859: AArch64: vtableStubs gtest fails after 8174962
8196136: AArch64: Correct register use in patch for JDK-8194686
8196221: AArch64: Mistake in committed patch for JDK-8195859
8199712: [AArch64] Flight Recorder
8203481: Incorrect constraint for unextended_sp in frame:safe_for_sender
8203699: java/lang/invoke/SpecialInterfaceCall fails with SIGILL on aarch64
8205421: AARCH64: StubCodeMark should be placed after alignment
8206163: AArch64: incorrect code generation for StoreCM
8207345: Trampoline generation code reads from uninitialized memory
8207838: AArch64: Float registers incorrectly restored in JNI call
8209413: AArch64: NPE in clhsdb jstack command
8209414: [AArch64] method handle invocation does not respect JVMTI interp_only mode
8209415: Fix JVMTI test failure HS202
8209420: Track membars for volatile accesses so they can be properly optimized
8209835: Aarch64: elide barriers on all volatile operations
8210425: [AArch64] sharedRuntimeTrig/sharedRuntimeTrans compiled without optimization
8211064: [AArch64] Interpreter and c1 don't correctly handle jboolean results in native calls
8211233: MemBarNode::trailing_membar() and MemBarNode::leading_membar() need to handle dying subgraphs better
8213134: AArch64: vector shift failed with MaxVectorSize=8
8213419: [AArch64] C2 may hang in MulLNode::Ideal()/MulINode::Ideal() with gcc 8.2.1
8214857: "bad trailing membar" assert failure at memnode.cpp:3220
8215951: AArch64: jtreg test vmTestbase/nsk/jvmti/PopFrame/popframe005 segfaults
8215961: jdk/jfr/event/os/TestCPUInformation.java fails on AArch64
8216350: AArch64: monitor unlock fast path not called
8216989: CardTableBarrierSetAssembler::gen_write_ref_array_post_barrier() does not check for zero length on AARCH64
8217368: AArch64: C2 recursive stack locking optimisation not triggered
8218185: aarch64: missing LoadStore barrier in TemplateTable::putfield_or_static
8219011: Implement MacroAssembler::warn method on AArch64
8219635: aarch64: missing LoadStore barrier in TemplateTable::fast_storefield
8221220: AArch64: Add StoreStore membar explicitly for Volatile Writes in TemplateTable
8221658: aarch64: add necessary predicate for ubfx patterns
8224671: AArch64: mauve System.arraycopy test failure
8224828: aarch64: rflags is not correct after safepoint poll
8224851: AArch64: fix warnings and errors with Clang and GCC 8.3
8224880: AArch64: java/javac error with AllocatePrefetchDistance
8228400: Remove built-in AArch64 simulator
8228406: Superfluous change in chaitin.hpp
8228593: Revert explicit JDK 7 support additions
8228716: Revert InstanceKlass::print_on debug additions
8228718: Revert incorrect backport of JDK-8129757 to 8-aarch64
8228725: AArch64: Purge method call format support
8228747: Revert "unused" attribute from test_arraycopy_func
8228767: Revert ResourceMark additions
8228770: Revert development hsdis changes
8229123: Revert build fixes for aarch64/zero
8229124: Revert disassembler.cpp changes
8229145: Revert TemplateTable::bytecode() visibility change
8233839: aarch64: missing memory barrier in NewObjectArrayStub and NewTypeArrayStub
8237512: AArch64: aarch64TestHook leaks a BufferBlob
8246482: Build failures with +JFR -PCH
8247979: aarch64: missing side effect of killing flags for clearArray_reg_reg
8248219: aarch64: missing memory barrier in fast_storefield and fast_accessfield
Reviewed-by: shade, aph
author | andrew |
---|---|
date | Mon, 01 Feb 2021 03:48:36 +0000 |
parents | |
children | f79e943d15a7 |
line wrap: on
line source
/* * Copyright (c) 2013, Red Hat Inc. * Copyright (c) 1997, 2011, Oracle and/or its affiliates. * All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * */ #ifndef CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP #define CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP #include "asm/assembler.hpp" #include "memory/allocation.hpp" #include "runtime/icache.hpp" #include "runtime/os.hpp" #include "utilities/top.hpp" // We have interfaces for the following instructions: // - NativeInstruction // - - NativeCall // - - NativeMovConstReg // - - NativeMovConstRegPatching // - - NativeMovRegMem // - - NativeMovRegMemPatching // - - NativeJump // - - NativeIllegalOpCode // - - NativeGeneralJump // - - NativeReturn // - - NativeReturnX (return with argument) // - - NativePushConst // - - NativeTstRegMem // The base class for different kinds of native instruction abstractions. // Provides the primitive operations to manipulate code relative to this. class NativeInstruction VALUE_OBJ_CLASS_SPEC { friend class Relocation; friend bool is_NativeCallTrampolineStub_at(address); public: enum { instruction_size = 4 }; inline bool is_nop(); bool is_dtrace_trap(); inline bool is_illegal(); inline bool is_return(); bool is_jump(); inline bool is_jump_or_nop(); inline bool is_cond_jump(); bool is_safepoint_poll(); inline bool is_mov_literal64(); bool is_movz(); bool is_movk(); bool is_sigill_zombie_not_entrant(); protected: address addr_at(int offset) const { return address(this) + offset; } s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); } u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); } jint int_at(int offset) const { return *(jint*) addr_at(offset); } juint uint_at(int offset) const { return *(juint*) addr_at(offset); } address ptr_at(int offset) const { return *(address*) addr_at(offset); } oop oop_at (int offset) const { return *(oop*) addr_at(offset); } void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; } void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; } void set_uint_at(int offset, jint i) { *(juint*)addr_at(offset) = i; } void set_ptr_at (int offset, address ptr) { *(address*) addr_at(offset) = ptr; } void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; } public: // unit test stuff static void test() {} // override for testing inline friend NativeInstruction* nativeInstruction_at(address address); static bool is_adrp_at(address instr); static bool is_ldr_literal_at(address instr); static bool is_ldrw_to_zr(address instr); static bool maybe_cpool_ref(address instr) { return is_adrp_at(instr) || is_ldr_literal_at(instr); } }; inline NativeInstruction* nativeInstruction_at(address address) { return (NativeInstruction*)address; } // The natural type of an AArch64 instruction is uint32_t inline NativeInstruction* nativeInstruction_at(uint32_t *address) { return (NativeInstruction*)address; } inline NativeCall* nativeCall_at(address address); // The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off // instructions (used to manipulate inline caches, primitive & dll calls, etc.). class NativeCall: public NativeInstruction { public: enum Aarch64_specific_constants { instruction_size = 4, instruction_offset = 0, displacement_offset = 0, return_address_offset = 4 }; enum { cache_line_size = BytesPerWord }; // conservative estimate! address instruction_address() const { return addr_at(instruction_offset); } address next_instruction_address() const { return addr_at(return_address_offset); } int displacement() const { return (int_at(displacement_offset) << 6) >> 4; } address displacement_address() const { return addr_at(displacement_offset); } address return_address() const { return addr_at(return_address_offset); } address destination() const; void set_destination(address dest) { int offset = dest - instruction_address(); unsigned int insn = 0b100101 << 26; assert((offset & 3) == 0, "should be"); offset >>= 2; offset &= (1 << 26) - 1; // mask off insn part insn |= offset; set_int_at(displacement_offset, insn); } void verify_alignment() { ; } void verify(); void print(); // Creation inline friend NativeCall* nativeCall_at(address address); inline friend NativeCall* nativeCall_before(address return_address); static bool is_call_at(address instr) { const uint32_t insn = (*(uint32_t*)instr); return (insn >> 26) == 0b100101; } static bool is_call_before(address return_address) { return is_call_at(return_address - NativeCall::return_address_offset); } // MT-safe patching of a call instruction. static void insert(address code_pos, address entry); static void replace_mt_safe(address instr_addr, address code_buffer); // Similar to replace_mt_safe, but just changes the destination. The // important thing is that free-running threads are able to execute // this call instruction at all times. If the call is an immediate BL // instruction we can simply rely on atomicity of 32-bit writes to // make sure other threads will see no intermediate states. // We cannot rely on locks here, since the free-running threads must run at // full speed. // // Used in the runtime linkage of calls; see class CompiledIC. // (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.) // The parameter assert_lock disables the assertion during code generation. void set_destination_mt_safe(address dest, bool assert_lock = true); address get_trampoline(); }; inline NativeCall* nativeCall_at(address address) { NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset); #ifdef ASSERT call->verify(); #endif return call; } inline NativeCall* nativeCall_before(address return_address) { NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset); #ifdef ASSERT call->verify(); #endif return call; } // An interface for accessing/manipulating native mov reg, imm instructions. // (used to manipulate inlined 64-bit data calls, etc.) class NativeMovConstReg: public NativeInstruction { public: enum Aarch64_specific_constants { instruction_size = 3 * 4, // movz, movk, movk. See movptr(). instruction_offset = 0, displacement_offset = 0, }; address instruction_address() const { return addr_at(instruction_offset); } address next_instruction_address() const { if (nativeInstruction_at(instruction_address())->is_movz()) // Assume movz, movk, movk return addr_at(instruction_size); else if (is_adrp_at(instruction_address())) return addr_at(2*4); else if (is_ldr_literal_at(instruction_address())) return(addr_at(4)); assert(false, "Unknown instruction in NativeMovConstReg"); return NULL; } intptr_t data() const; void set_data(intptr_t x); void flush() { if (! maybe_cpool_ref(instruction_address())) { ICache::invalidate_range(instruction_address(), instruction_size); } } void verify(); void print(); // unit test stuff static void test() {} // Creation inline friend NativeMovConstReg* nativeMovConstReg_at(address address); inline friend NativeMovConstReg* nativeMovConstReg_before(address address); }; inline NativeMovConstReg* nativeMovConstReg_at(address address) { NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset); #ifdef ASSERT test->verify(); #endif return test; } inline NativeMovConstReg* nativeMovConstReg_before(address address) { NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset); #ifdef ASSERT test->verify(); #endif return test; } class NativeMovConstRegPatching: public NativeMovConstReg { private: friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset); #ifdef ASSERT test->verify(); #endif return test; } }; // An interface for accessing/manipulating native moves of the form: // mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem) // mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg // mov[s/z]x[w/b/q] [reg + offset], reg // fld_s [reg+offset] // fld_d [reg+offset] // fstp_s [reg + offset] // fstp_d [reg + offset] // mov_literal64 scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch) // // Warning: These routines must be able to handle any instruction sequences // that are generated as a result of the load/store byte,word,long // macros. For example: The load_unsigned_byte instruction generates // an xor reg,reg inst prior to generating the movb instruction. This // class must skip the xor instruction. class NativeMovRegMem: public NativeInstruction { enum AArch64_specific_constants { instruction_size = 4, instruction_offset = 0, data_offset = 0, next_instruction_offset = 4 }; public: // helper int instruction_start() const; address instruction_address() const; address next_instruction_address() const; int offset() const; void set_offset(int x); void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); } void verify(); void print (); // unit test stuff static void test() {} private: inline friend NativeMovRegMem* nativeMovRegMem_at (address address); }; inline NativeMovRegMem* nativeMovRegMem_at (address address) { NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset); #ifdef ASSERT test->verify(); #endif return test; } class NativeMovRegMemPatching: public NativeMovRegMem { private: friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {Unimplemented(); return 0; } }; // An interface for accessing/manipulating native leal instruction of form: // leal reg, [reg + offset] class NativeLoadAddress: public NativeMovRegMem { static const bool has_rex = true; static const int rex_size = 1; public: void verify(); void print (); // unit test stuff static void test() {} }; class NativeJump: public NativeInstruction { public: enum AArch64_specific_constants { instruction_size = 4, instruction_offset = 0, data_offset = 0, next_instruction_offset = 4 }; address instruction_address() const { return addr_at(instruction_offset); } address next_instruction_address() const { return addr_at(instruction_size); } address jump_destination() const; void set_jump_destination(address dest); // Creation inline friend NativeJump* nativeJump_at(address address); void verify(); // Unit testing stuff static void test() {} // Insertion of native jump instruction static void insert(address code_pos, address entry); // MT-safe insertion of native jump at verified method entry static void check_verified_entry_alignment(address entry, address verified_entry); static void patch_verified_entry(address entry, address verified_entry, address dest); }; inline NativeJump* nativeJump_at(address address) { NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset); #ifdef ASSERT jump->verify(); #endif return jump; } class NativeGeneralJump: public NativeJump { public: enum AArch64_specific_constants { instruction_size = 4 * 4, instruction_offset = 0, data_offset = 0, next_instruction_offset = 4 * 4 }; static void insert_unconditional(address code_pos, address entry); static void replace_mt_safe(address instr_addr, address code_buffer); static void verify(); }; inline NativeGeneralJump* nativeGeneralJump_at(address address) { NativeGeneralJump* jump = (NativeGeneralJump*)(address); debug_only(jump->verify();) return jump; } class NativePopReg : public NativeInstruction { public: // Insert a pop instruction static void insert(address code_pos, Register reg); }; class NativeIllegalInstruction: public NativeInstruction { public: // Insert illegal opcode as specific address static void insert(address code_pos); }; // return instruction that does not pop values of the stack class NativeReturn: public NativeInstruction { public: }; // return instruction that does pop values of the stack class NativeReturnX: public NativeInstruction { public: }; // Simple test vs memory class NativeTstRegMem: public NativeInstruction { public: }; inline bool NativeInstruction::is_nop() { uint32_t insn = *(uint32_t*)addr_at(0); return insn == 0xd503201f; } inline bool NativeInstruction::is_jump() { uint32_t insn = *(uint32_t*)addr_at(0); if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { // Unconditional branch (immediate) return true; } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { // Conditional branch (immediate) return true; } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { // Compare & branch (immediate) return true; } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { // Test & branch (immediate) return true; } else return false; } inline bool NativeInstruction::is_jump_or_nop() { return is_nop() || is_jump(); } // Call trampoline stubs. class NativeCallTrampolineStub : public NativeInstruction { public: enum AArch64_specific_constants { instruction_size = 4 * 4, instruction_offset = 0, data_offset = 2 * 4, next_instruction_offset = 4 * 4 }; address destination(nmethod *nm = NULL) const; void set_destination(address new_destination); ptrdiff_t destination_offset() const; }; inline bool is_NativeCallTrampolineStub_at(address addr) { // Ensure that the stub is exactly // ldr xscratch1, L // br xscratch1 // L: uint32_t *i = (uint32_t *)addr; return i[0] == 0x58000048 && i[1] == 0xd61f0100; } inline NativeCallTrampolineStub* nativeCallTrampolineStub_at(address addr) { assert(is_NativeCallTrampolineStub_at(addr), "no call trampoline found"); return (NativeCallTrampolineStub*)addr; } #endif // CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP