Mercurial > hg > icedtea8-forest > hotspot
view src/cpu/aarch64/vm/nativeInst_aarch64.cpp @ 10905:f57189b7648d
8257192: Integrate AArch64 JIT port into 8u
7009641: Don't fail VM when CodeCache is full
8073108: [AArch64] Use x86 and SPARC CPU instructions for GHASH acceleration
8130309: Need to bailout cleanly if creation of stubs fails when codecache is out of space (AArch64 changes)
8131779: AARCH64: add Montgomery multiply intrinsic
8132875: AArch64: Fix error introduced into AArch64 CodeCache by commit for 8130309
8135018: AARCH64: Missing memory barriers for CMS collector
8145320: Create unsafe_arraycopy and generic_arraycopy for AArch64
8148328: aarch64: redundant lsr instructions in stub code.
8148783: aarch64: SEGV running SpecJBB2013
8148948: aarch64: generate_copy_longs calls align() incorrectly
8149080: AArch64: Recognise disjoint array copy in stub code
8149365: aarch64: memory copy does not prefetch on backwards copy
8149907: aarch64: use load/store pair instructions in call_stub
8150038: aarch64: make use of CBZ and CBNZ when comparing narrow pointer with zero
8150045: arraycopy causes segfaults in SATB during garbage collection
8150082: aarch64: optimise small array copy
8150229: aarch64: pipeline class for several instructions is not set correctly
8150313: aarch64: optimise array copy using SIMD instructions
8150394: aarch64: add support for 8.1 LSE CAS instructions
8150652: Remove unused code in AArch64 back end
8151340: aarch64: prefetch the destination word for write prior to ldxr/stxr loops.
8151502: optimize pd_disjoint_words and pd_conjoint_words
8151775: aarch64: add support for 8.1 LSE atomic operations
8152537: aarch64: Make use of CBZ and CBNZ when comparing unsigned values with zero.
8152840: aarch64: improve _unsafe_arraycopy stub routine
8153172: aarch64: hotspot crashes after the 8.1 LSE patch is merged
8153713: aarch64: improve short array clearing using store pair
8153797: aarch64: Add Arrays.fill stub code
8154413: AArch64: Better byte behaviour
8154537: AArch64: some integer rotate instructions are never emitted
8154739: AArch64: TemplateTable::fast_xaccess loads in wrong mode
8155015: Aarch64: bad assert in spill generation code
8155100: AArch64: Relax alignment requirement for byte_map_base
8155612: Aarch64: vector nodes need to support misaligned offset
8155617: aarch64: ClearArray does not use DC ZVA
8155627: Enable SA on AArch64
8155653: TestVectorUnalignedOffset.java not pushed with 8155612
8156731: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
8157841: aarch64: prefetch ignores cache line size
8157906: aarch64: some more integer rotate instructions are never emitted
8158913: aarch64: SEGV running Spark terasort
8159052: aarch64: optimise unaligned copies in pd_disjoint_words and pd_conjoint_words
8159063: aarch64: optimise unaligned array copy long
8160748: [AArch64] Inconsistent types for ideal_reg
8161072: AArch64: jtreg compiler/uncommontrap/TestDeoptOOM failure
8161190: AArch64: Fix overflow in immediate cmp instruction
8164113: AArch64: follow-up the fix for 8161598
8165673: AArch64: Fix JNI floating point argument handling
8167200: AArch64: Broken stack pointer adjustment in interpreter
8167421: AArch64: in one core system, fatal error: Illegal threadstate encountered
8167595: AArch64: SEGV in stub code cipherBlockChaining_decryptAESCrypt
8168699: Validate special case invocations [AArch64 support]
8168888: Port 8160591: Improve internal array handling to AArch64.
8170100: AArch64: Crash in C1-compiled code accessing References
8170188: jtreg test compiler/types/TestMeetIncompatibleInterfaceArrays.java causes JVM crash
8170873: PPC64/aarch64: Poor StrictMath performance due to non-optimized compilation
8171537: aarch64: compiler/c1/Test6849574.java generates guarantee failure in C1
8172881: AArch64: assertion failure: the int pressure is incorrect
8173472: AArch64: C1 comparisons with null only use 32-bit instructions
8176100: [AArch64] [REDO][REDO] G1 Needs pre barrier on dereference of weak JNI handles
8177661: Correct ad rule output register types from iRegX to iRegXNoSp
8179954: AArch64: C1 and C2 volatile accesses are not sequentially consistent
8182581: aarch64: fix for crash caused by earlyret of compiled method
8183925: [AArch64] Decouple crash protection from watcher thread
8186325: AArch64: jtreg test hotspot/test/gc/g1/TestJNIWeakG1/TestJNIWeakG1.java SEGV
8187224: aarch64: some inconsistency between aarch64_ad.m4 and aarch64.ad
8189170: [AArch64] Add option to disable stack overflow checking in primordial thread for use with JNI_CreateJavaJVM
8193133: Assertion failure because 0xDEADDEAD can be in-heap
8195685: AArch64 port of 8174962: Better interface invocations
8195859: AArch64: vtableStubs gtest fails after 8174962
8196136: AArch64: Correct register use in patch for JDK-8194686
8196221: AArch64: Mistake in committed patch for JDK-8195859
8199712: [AArch64] Flight Recorder
8203481: Incorrect constraint for unextended_sp in frame:safe_for_sender
8203699: java/lang/invoke/SpecialInterfaceCall fails with SIGILL on aarch64
8205421: AARCH64: StubCodeMark should be placed after alignment
8206163: AArch64: incorrect code generation for StoreCM
8207345: Trampoline generation code reads from uninitialized memory
8207838: AArch64: Float registers incorrectly restored in JNI call
8209413: AArch64: NPE in clhsdb jstack command
8209414: [AArch64] method handle invocation does not respect JVMTI interp_only mode
8209415: Fix JVMTI test failure HS202
8209420: Track membars for volatile accesses so they can be properly optimized
8209835: Aarch64: elide barriers on all volatile operations
8210425: [AArch64] sharedRuntimeTrig/sharedRuntimeTrans compiled without optimization
8211064: [AArch64] Interpreter and c1 don't correctly handle jboolean results in native calls
8211233: MemBarNode::trailing_membar() and MemBarNode::leading_membar() need to handle dying subgraphs better
8213134: AArch64: vector shift failed with MaxVectorSize=8
8213419: [AArch64] C2 may hang in MulLNode::Ideal()/MulINode::Ideal() with gcc 8.2.1
8214857: "bad trailing membar" assert failure at memnode.cpp:3220
8215951: AArch64: jtreg test vmTestbase/nsk/jvmti/PopFrame/popframe005 segfaults
8215961: jdk/jfr/event/os/TestCPUInformation.java fails on AArch64
8216350: AArch64: monitor unlock fast path not called
8216989: CardTableBarrierSetAssembler::gen_write_ref_array_post_barrier() does not check for zero length on AARCH64
8217368: AArch64: C2 recursive stack locking optimisation not triggered
8218185: aarch64: missing LoadStore barrier in TemplateTable::putfield_or_static
8219011: Implement MacroAssembler::warn method on AArch64
8219635: aarch64: missing LoadStore barrier in TemplateTable::fast_storefield
8221220: AArch64: Add StoreStore membar explicitly for Volatile Writes in TemplateTable
8221658: aarch64: add necessary predicate for ubfx patterns
8224671: AArch64: mauve System.arraycopy test failure
8224828: aarch64: rflags is not correct after safepoint poll
8224851: AArch64: fix warnings and errors with Clang and GCC 8.3
8224880: AArch64: java/javac error with AllocatePrefetchDistance
8228400: Remove built-in AArch64 simulator
8228406: Superfluous change in chaitin.hpp
8228593: Revert explicit JDK 7 support additions
8228716: Revert InstanceKlass::print_on debug additions
8228718: Revert incorrect backport of JDK-8129757 to 8-aarch64
8228725: AArch64: Purge method call format support
8228747: Revert "unused" attribute from test_arraycopy_func
8228767: Revert ResourceMark additions
8228770: Revert development hsdis changes
8229123: Revert build fixes for aarch64/zero
8229124: Revert disassembler.cpp changes
8229145: Revert TemplateTable::bytecode() visibility change
8233839: aarch64: missing memory barrier in NewObjectArrayStub and NewTypeArrayStub
8237512: AArch64: aarch64TestHook leaks a BufferBlob
8246482: Build failures with +JFR -PCH
8247979: aarch64: missing side effect of killing flags for clearArray_reg_reg
8248219: aarch64: missing memory barrier in fast_storefield and fast_accessfield
Reviewed-by: shade, aph
author | andrew |
---|---|
date | Mon, 01 Feb 2021 03:48:36 +0000 |
parents | |
children | f79e943d15a7 |
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/* * Copyright (c) 2013, Red Hat Inc. * Copyright (c) 1997, 2010, Oracle and/or its affiliates. * All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * */ #include "precompiled.hpp" #include "asm/macroAssembler.hpp" #include "memory/resourceArea.hpp" #include "nativeInst_aarch64.hpp" #include "oops/oop.inline.hpp" #include "runtime/handles.hpp" #include "runtime/sharedRuntime.hpp" #include "runtime/stubRoutines.hpp" #include "utilities/ostream.hpp" #ifdef COMPILER1 #include "c1/c1_Runtime1.hpp" #endif void NativeCall::verify() { ; } address NativeCall::destination() const { address addr = (address)this; address destination = instruction_address() + displacement(); // Do we use a trampoline stub for this call? CodeBlob* cb = CodeCache::find_blob_unsafe(addr); // Else we get assertion if nmethod is zombie. assert(cb && cb->is_nmethod(), "sanity"); nmethod *nm = (nmethod *)cb; if (nm->stub_contains(destination) && is_NativeCallTrampolineStub_at(destination)) { // Yes we do, so get the destination from the trampoline stub. const address trampoline_stub_addr = destination; destination = nativeCallTrampolineStub_at(trampoline_stub_addr)->destination(); } return destination; } // Similar to replace_mt_safe, but just changes the destination. The // important thing is that free-running threads are able to execute this // call instruction at all times. // // Used in the runtime linkage of calls; see class CompiledIC. // // Add parameter assert_lock to switch off assertion // during code generation, where no patching lock is needed. void NativeCall::set_destination_mt_safe(address dest, bool assert_lock) { assert(!assert_lock || (Patching_lock->is_locked() || SafepointSynchronize::is_at_safepoint()), "concurrent code patching"); ResourceMark rm; int code_size = NativeInstruction::instruction_size; address addr_call = addr_at(0); assert(NativeCall::is_call_at(addr_call), "unexpected code at call site"); // Patch the constant in the call's trampoline stub. address trampoline_stub_addr = get_trampoline(); if (trampoline_stub_addr != NULL) { assert (! is_NativeCallTrampolineStub_at(dest), "chained trampolines"); nativeCallTrampolineStub_at(trampoline_stub_addr)->set_destination(dest); } // Patch the call. if (Assembler::reachable_from_branch_at(addr_call, dest)) { set_destination(dest); } else { assert (trampoline_stub_addr != NULL, "we need a trampoline"); set_destination(trampoline_stub_addr); } ICache::invalidate_range(addr_call, instruction_size); } address NativeCall::get_trampoline() { address call_addr = addr_at(0); CodeBlob *code = CodeCache::find_blob(call_addr); assert(code != NULL, "Could not find the containing code blob"); address bl_destination = MacroAssembler::pd_call_destination(call_addr); if (code->content_contains(bl_destination) && is_NativeCallTrampolineStub_at(bl_destination)) return bl_destination; // If the codeBlob is not a nmethod, this is because we get here from the // CodeBlob constructor, which is called within the nmethod constructor. return trampoline_stub_Relocation::get_trampoline_for(call_addr, (nmethod*)code); } // Inserts a native call instruction at a given pc void NativeCall::insert(address code_pos, address entry) { Unimplemented(); } //------------------------------------------------------------------- void NativeMovConstReg::verify() { // make sure code pattern is actually mov reg64, imm64 instructions } intptr_t NativeMovConstReg::data() const { // das(uint64_t(instruction_address()),2); address addr = MacroAssembler::target_addr_for_insn(instruction_address()); if (maybe_cpool_ref(instruction_address())) { return *(intptr_t*)addr; } else { return (intptr_t)addr; } } void NativeMovConstReg::set_data(intptr_t x) { if (maybe_cpool_ref(instruction_address())) { address addr = MacroAssembler::target_addr_for_insn(instruction_address()); *(intptr_t*)addr = x; } else { MacroAssembler::pd_patch_instruction(instruction_address(), (address)x); ICache::invalidate_range(instruction_address(), instruction_size); } }; void NativeMovConstReg::print() { tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT, p2i(instruction_address()), data()); } //------------------------------------------------------------------- address NativeMovRegMem::instruction_address() const { return addr_at(instruction_offset); } int NativeMovRegMem::offset() const { address pc = instruction_address(); unsigned insn = *(unsigned*)pc; if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { address addr = MacroAssembler::target_addr_for_insn(pc); return *addr; } else { return (int)(intptr_t)MacroAssembler::target_addr_for_insn(instruction_address()); } } void NativeMovRegMem::set_offset(int x) { address pc = instruction_address(); unsigned insn = *(unsigned*)pc; if (maybe_cpool_ref(pc)) { address addr = MacroAssembler::target_addr_for_insn(pc); *(long*)addr = x; } else { MacroAssembler::pd_patch_instruction(pc, (address)intptr_t(x)); ICache::invalidate_range(instruction_address(), instruction_size); } } void NativeMovRegMem::verify() { #ifdef ASSERT address dest = MacroAssembler::target_addr_for_insn(instruction_address()); #endif } //-------------------------------------------------------------------------------- void NativeJump::verify() { ; } void NativeJump::check_verified_entry_alignment(address entry, address verified_entry) { } address NativeJump::jump_destination() const { address dest = MacroAssembler::target_addr_for_insn(instruction_address()); // We use jump to self as the unresolved address which the inline // cache code (and relocs) know about // return -1 if jump to self dest = (dest == (address) this) ? (address) -1 : dest; return dest; } void NativeJump::set_jump_destination(address dest) { // We use jump to self as the unresolved address which the inline // cache code (and relocs) know about if (dest == (address) -1) dest = instruction_address(); MacroAssembler::pd_patch_instruction(instruction_address(), dest); ICache::invalidate_range(instruction_address(), instruction_size); }; //------------------------------------------------------------------- bool NativeInstruction::is_safepoint_poll() { // a safepoint_poll is implemented in two steps as either // // adrp(reg, polling_page); // ldr(zr, [reg, #offset]); // // or // // mov(reg, polling_page); // ldr(zr, [reg, #offset]); // // however, we cannot rely on the polling page address load always // directly preceding the read from the page. C1 does that but C2 // has to do the load and read as two independent instruction // generation steps. that's because with a single macro sequence the // generic C2 code can only add the oop map before the mov/adrp and // the trap handler expects an oop map to be associated with the // load. with the load scheuled as a prior step the oop map goes // where it is needed. // // so all we can do here is check that marked instruction is a load // word to zr return is_ldrw_to_zr(address(this)); } bool NativeInstruction::is_adrp_at(address instr) { unsigned insn = *(unsigned*)instr; return (Instruction_aarch64::extract(insn, 31, 24) & 0b10011111) == 0b10010000; } bool NativeInstruction::is_ldr_literal_at(address instr) { unsigned insn = *(unsigned*)instr; return (Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000; } bool NativeInstruction::is_ldrw_to_zr(address instr) { unsigned insn = *(unsigned*)instr; return (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && Instruction_aarch64::extract(insn, 4, 0) == 0b11111); } bool NativeInstruction::is_movz() { return Instruction_aarch64::extract(int_at(0), 30, 23) == 0b10100101; } bool NativeInstruction::is_movk() { return Instruction_aarch64::extract(int_at(0), 30, 23) == 0b11100101; } bool NativeInstruction::is_sigill_zombie_not_entrant() { return uint_at(0) == 0xd4bbd5a1; // dcps1 #0xdead } void NativeIllegalInstruction::insert(address code_pos) { *(juint*)code_pos = 0xd4bbd5a1; // dcps1 #0xdead } //------------------------------------------------------------------- // MT safe inserting of a jump over a jump or a nop (used by // nmethod::makeZombie) void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) { assert(dest == SharedRuntime::get_handle_wrong_method_stub(), "expected fixed destination of patch"); assert(nativeInstruction_at(verified_entry)->is_jump_or_nop() || nativeInstruction_at(verified_entry)->is_sigill_zombie_not_entrant(), "Aarch64 cannot replace non-jump with jump"); // Patch this nmethod atomically. if (Assembler::reachable_from_branch_at(verified_entry, dest)) { ptrdiff_t disp = dest - verified_entry; guarantee(disp < 1 << 27 && disp > - (1 << 27), "branch overflow"); unsigned int insn = (0b000101 << 26) | ((disp >> 2) & 0x3ffffff); *(unsigned int*)verified_entry = insn; } else { // We use an illegal instruction for marking a method as // not_entrant or zombie. NativeIllegalInstruction::insert(verified_entry); } ICache::invalidate_range(verified_entry, instruction_size); } void NativeGeneralJump::verify() { } void NativeGeneralJump::insert_unconditional(address code_pos, address entry) { NativeGeneralJump* n_jump = (NativeGeneralJump*)code_pos; CodeBuffer cb(code_pos, instruction_size); MacroAssembler a(&cb); a.movptr(rscratch1, (uintptr_t)entry); a.br(rscratch1); ICache::invalidate_range(code_pos, instruction_size); } // MT-safe patching of a long jump instruction. void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) { ShouldNotCallThis(); } bool NativeInstruction::is_dtrace_trap() { return false; } address NativeCallTrampolineStub::destination(nmethod *nm) const { return ptr_at(data_offset); } void NativeCallTrampolineStub::set_destination(address new_destination) { set_ptr_at(data_offset, new_destination); OrderAccess::release(); }